SU1219972A1 - Threshold device - Google Patents

Abstract

The invention relates to the field of measurement technology. It can be used for threshold voltage control when building embedded automatic control systems made using elements of digital computing. The aim of the invention is to simplify the device. The device contains a transformer 1 with windings 2, 3 and 4, a diode 5, a voltage divider 7, inputs 8 and 9 of the device, a control unit 10 with inputs 11 and 12, a threshold element 14, a trigger 15, a device output 18, a potential source output 19 Gshtani, the general output 20 of the transformer 1 windings, the capacitor 6, the resistor 13. To achieve the set task, the threshold element 14 is made in the form of a zero-organ.1 Il. with

Description

The invention relates to the field of measurement technology and can be used for threshold voltage control in the construction of embedded automatic control systems made using elements of digital computer technology.

The object of the present invention is to simplify the device.

The drawing shows a diagram of the device.

The device contains a three-winding transformer 1, windings 2-4 of transformer 1, diode 5, capacitor 6, voltage divider 7, inputs 8, 9 of the device, control unit 10, first and second outputs 11 and 12 of control unit 10, resistor 13, a threshold element in the form of a null organ 14, a D-flip-flop 15, an information input 16 and a sync input 17 of the D-flip-flop 15, an output 18 of the device, a potential output 19 of the power supply, a common output 20 of the windings ZIL of the transformer 1.

The winding 2 of the transformer 1 through the diode 5 is connected in parallel to the capacitor 6, the outputs of which. connected to voltage divider 7. The windings 3 and 4 of the transformer 1 are connected in series and according to. The second terminal of the winding 4 is connected to the potential terminal 19 of the power supply. The common terminal 20 of the windings 3 and 4 of the transformer 1 is connected via a resistor 13 to the first output P of the control unit 10. The second terminal of the winding 3 is connected to the input of the null organ 14, the output of which is connected to the information input 16 of the D-flip-flop 15. The second output 12 of the control unit 10 is connected to the synchronizing input 17 of the D-flip-flop 15 You are: $ 18 D-flip-flop 15 is device output. Inputs 8 and 9 are device inputs. .

The device works as follows.

A negative pulse pulse (level O) from the output 11 of the control unit 10 through the windings 2 and 4 of the transformer 1 is fed to a series-connected capacitor 6 and a diode 5. If the voltage on the winding 2 of transformer 1 is higher than the voltage on the capacitor 6, the diode 5 is unlocked

which leads to the limitation of the voltage on the winding 2 at the level

r.

(one)

where K is the transfer coefficient of the divider 7; Uff is the voltage drop across the open diode 5;

value (

neither

10 I input voltage value. The voltage change on the capacitor 6 during the action of the clock pulse is negligible, which is achieved by an appropriate choice of the pulse duration and capacitance of the capacitor 6.

The windings 4, 3 of the transformer 1 are set according to the voltage

-and

2-4

ZJ (2)

and - b. ± - .and ,,

to

(3)

2-4

where Kj and K are the transformation ratios of the transformer 1 between the windings of 2.4 and 3.4 transformers, respectively.

On the limiting resistor 13, the difference between the voltages E f, –4, –1 is distinguished — for sufficiently small values

4- L

the voltage at the input of the null organ 14 after the delivery of the clock pulse will remain positive, and the O level will remain at its output. At sufficiently large values of Ug, the condition

45

and +,

(four)

which taking into account (1) - (3) can be represented as

Kj.-4 l + k, 4

EG. and

(five)

The voltage at the input of the null organ 14 will become negative, and at its output the level 1 will be set for the duration of the clock pulse. 55 With a further increase. . the voltage depending on it on the capacitor 6 can exceed U-, In this case the diode 5 will remain locked

Tymi, on the first and third windings 3, 4 is formed the total voltage

and + and (1 + -k,)

E,

and condition (4) will be fulfilled, as a result of which the output of the null organ 14 will set the level |. The triggering pulse of positive polarity (level 1) at the output of the 12. block 10 will result in the output of the D-flip-flop ..15 level at its information entry,

The formation of a gating pulse during the action of a clock pulse leads to the establishment of a level 1 device at output 18 when condition (5) is satisfied and level O when it is not satisfied. After the end of the strobe pulse, the voltage level at the output 18 does not change and will be maintained by the D-trigger 15 until a similar pulse appears in the next cycle. After the end of the clock pulse and transients, the circuit elements return to their original state. In subsequent cycles, the operation of the circuit is repeated.

Thus, when the voltage U exceeds the threshold value (i.e. when the condition (5) is fulfilled), a uniform logic level I is formed at the output 18 of the device, in the opposite case the level O.

The individual elements of the proposed device can be performed as follows.

In the multichannel version of the device and using unified transformers, the installation in each channel of a given threshold level is achieved by selecting the parameters of the voltage divider 7. The device allows the use of common to all channels of the control unit 10, in which quality can be used, for example, a pulse generator, made on the basis of digital ICs. To eliminate the possibility of the appearance at the output 18 of the device in each cycle of its operation a short pulse with a level O due to a signal delay at the information input of the D-flip-flop 15 from 199972

about the signal at its sync-input, the leading edge of the strobe pulse must be delayed relative to the clock. Rear

5 fronts of the indicated pulses can be formed simultaneously. Due to the delay in the chain of the propagation of the clock pulse, the voltage change at the output of the null organ 14 will begin

JO after termination of the strobe pulse. When performing D-flip-flop 15 with dynamic control (or two-stage), the clock and gating pulses can be generated one at a time, for example, on the forward and inverse outputs of one logic element. In a particular implementation, pulses of the synchronization device of the digital part of the system are used as clock and gating pulses.

This technical solution simplifies the known threshold device, made with galvanic 25 isolation from the object of control.

Claims (1)

Invention Formula A threshold device comprising 30 a three-winding transformer, the first winding of which is connected through a diode in parallel to a capacitor, the terminals of which are the inputs of the device, a DC power source, a control unit, a resistor and a threshold element, which is different from In order to simplify, the threshold element is designed as a null organ, the second and third .Q windings of the transformer are connected in series and according to, the common output of said windings is connected to the first resistor with the first control unit code, the second output the second winding of the transformer is connected to the potential output of the power source, the second output of the third winding of the transformer is connected to the first input of the null organ, the second input of which is connected to the common bus of the device, the output of the null organ is connected to the information input of the D-trigger device inputted in is connected to the second output of the control unit, and the output is the output of the threshold device. 45 50