RU1826122C - Digital phase-frequency discriminator - Google Patents

Abstract

Usage: radio engineering, digital phase locked loop systems. SUMMARY OF THE INVENTION: a digital frequency-phase discriminator comprises a counter 1, an input signal pulse block 4 and a pulse counter, a static register 8, a prohibition block 7, two EXCLUSIVE OR elements 8, 9. D-triggers 10-15 and three elements AND NOT 17-19. The device provides sequential recording of the states of the outputs of the first and second elements EXCLUSIVE OR 8 and 9, respectively, in the third and fourth D-flip-flops 10 and 11, and then recording the states of the output bits of counter 1 in the static register 6, which increases the stability of operation. This ensures that the frequency comparison mode is switched off in the immediate vicinity of the equality of the frequencies of the input and reference signals, which reduces the transition time of the frequency comparison mode to the phase comparison mode. 2 ill.

Description

The invention relates to radio engineering, in particular to radio automation and pulse technology. The invention can be used in digital phase locked loop systems.

An object of the invention is to increase stability and shorten the transition time from the frequency comparison mode to the phase comparison mode.

In FIG. 1 shows a structural circuit diagram of a digital frequency-phase discriminator; in FIG. Figure 2 shows the time diagrams that explain its operation: a - time diagram of the output code of the CCHFD, b - time diagram of the output of the i-ro bit of the static register, c - time diagram of the output of the (t + 1) th bit of the static register, d - time diagram of the inverse output (i +1) -ro bit of the static register, d - time diagram of the output of the fourth D-trigger, e

is the time diagram of the output of the Kth bit of the static register, g is the time chart of the output of the (K + 1) th bit of the static register, h is the time diagram of the inverse output of the (K + 1) th bit of the static register, and is the time output diagram of the third D-flip-flop, k is the timing diagram of the output of the first D-flip-flop, l is the timing diagram of the output of the second D-flip-flop, m is the timing diagram of the inverse output of the fifth D-flip-flop, n is the timing diagram of the inverse output of the sixth D-flip-flop, o - time chart of the output of the first element AND NOT, n - timing diagram of the output of the second AND-NOT element, p is the timing diagram of the output of the third AND-NOT element.

The digital frequency-phase detector (Fig. 1) contains a counter 1, the input of the reference pulses 2, the input of the counting pulses 3. block impulses input signal

With

with

oo o o

1ChE

Yu

to counting pulses (PSU) 4, the input pulse of the input signal 5, static register b, block prohibition 7, two elements EXCLUSIVE OR 8. 9, six D-flip-flops 10-15, element OR 16 and three elements NAND 17-19 . The zeroing input R and the counting input T of the counter 1 are respectively inputs of the reference 2 and counting 3 pulses. The first and second inputs of the PSU 4 are connected respectively to the input 5 of the digital frequency-phase discriminator and the input 3 of the counting pulses. The first output of the PSU 4 is connected to the C-inputs of the third D-trigger 10 and the fourth D-trigger 11. The second output of the PSU 4 is connected to the C-input of the register information recording 6, the information inputs of which are connected to the corresponding outputs of the counter 1. outputs K bits of the static register 6 are connected to the inputs of the prohibition block 7, the outputs of K-ro and the 1st bit of the static register 7 are connected to the first inputs, respectively, of the first element EXCLUSIVE OR 8 and the second element EXCLUSIVE OR 9. The output of the elements EXCLUSIVE OR 8 and 9 are connected to О -input m respectively actually the third D-trigger 10 and the fourth D-trigger 11. The output of the third D-trigger 10 is connected to the D-inputs of the first O-trigger 12 and the second D-trigger 13, the C-input of the first D-trigger 12 is connected to the output (K + 1} -th digit of the static register 7. The inverse output of the (K + 1) -th digit of the static register 7 is connected to the second input of the first element EXCLUSIVE OR 8, with the C-output of the second D-trigger 13 and the first input of the IL element And 16. The output of the fourth D-flip-flop 11 is connected to the D-inputs of the fifth D-flip-flop 14 and the sixth D-flip-flop 15, the C-input of the first D-t igger 14 is connected to the output of the (i + 1) -th bit of the static register 7. The inverse output (i + 1) -ro of the bit of the static register 7 is connected to the second input of the second EXCLUSIVE OR element 9 and to the C-input of the sixth D-trigger 15. The direct output of the first D-trigger 12 is connected to the first input of the first AND-NOT 17 element and the inverse R-input of the sixth D-trigger 15. The direct output of the second D-trigger 13 is connected to the second input of the first AND-NOT 17 element and the inverse R-input of the fifth D-flip-flop 14. The output of the first AND-NOT 17 element is connected to the inverse R-input of the first D-flip-flop 12 and W cerned D-flip-flop 13. The inverted output of the fifth D-flip-flop 14 and the grained alkaline D-flip-flop 15 are connected to the inverse: E 8-0hodamy respectively the first D-flip-flop 12 and the second D-flip-flop 13. The inverted output of the first flip-flop O

0

5

0

5

0

5

0

5

0

5

12 and the second D-trigger 13 are connected respectively to the first and second inputs of the second AND-NOT element 18, the output of which is connected to the control input of the inhibit block 7 and the second input of the OR element 16. The output of the OR element 16 is connected to the first input of the third AND element NOT 19, the second input of the third AND-NOT 19 element is connected to the inverse output of the second D-flip-flop 13. The output of the third AND-NOT 19 element is the sign output of the digital frequency-phase discriminator. The output of the second AND-NOT element 18 and the output of the inhibit block 7 are outputs of the significant bits of the digital frequency-phase discriminator.

The proposed digital frequency-phase discriminator operates as follows.

The reference pulses from input 2 to input R of setting zero of counter 1 increase O at its output bits. The counting input T of counter 1 from input 3 receives a continuous sequence of counting pulses, under the influence of which the states of the output bits of counter 1 change. The frequency of the counting pulses is determined by the expression: 2k-I

mid -

-1

iK + 1

t

where 2 -1 is the capacity of the counter 1; T is the period of the reference pulses.

BP 4, which receives a sequence of counting pulses, provides the allocation of the first integer counting pulse at the first output, and the second integer counting pulse following the pulse of the input signal arriving at input 5 of the digital frequency-phase discriminator at the second output.

Following the input pulse, the first whole counting pulse records the states of the outputs of the first element EXCLUSIVE OR. 8 and the second element EXCLUSIVE OR 9, respectively, to the third D-trigger 10 and fourth D-trigger 11, and the second whole counting pulse records the state the output bits of counter 1 to the static register 6. A binary code is generated at the output of this register, the value of N of which is proportional to the phase difference of the input and reference pulses.

In the synchronism mode, when the phase difference of the pulses of the input and the reference signal passes through l (which corresponds to the zero value of the phase characteristic of the CCFD), the output switches (K + 1) hro of the sign bit of the static

register 6 from G to O or from O to G, depending on the direction of the phase difference between the input and the reference signal. At the same time, the K least significant bits of the static register 6 are switched from zero to single or from single to zero, respectively, depending on the direction of the phase difference between the pulses of the input and reference signals. In this case, as a result of the contention of the signal edges at the inputs of the first EXCLUSIVE OR 8 element, a pulsed interference of a single level appears. However, sequentially recording first the state of the output of the first EXCLUSIVE OR 8 element to the third D-flip-flop 10, and then the states of the output bits of the counter 1 in the static register 6, carried out using the output pulses of the BP 4, coming from the input signal pulse, eliminates the possibility switching on the first D-flip-flop 12 or the second D-flip-flop 13 against pulse interference of a single level.

If the frequency of the pulses of the input signal arriving at input 5 is greater than the frequency of the reference pulses arriving at input 2 (fBx ton), then the phase difference of these signals decreases from cycle to cycle in the direction from 2 tg to O, while the value of the binary code N decreases the output of the digital frequency-phase discriminator (Fig. 2A). When the phase difference of the input and reference signals reaches 0 ° at the time ti, and the value of the binary code at the output of the CDCHF reaches the value of Mob.mex. there is an abrupt change in the phase difference of the input signals from 0 ° to 2 tg. At the same time, the (K + 1) th digit of the static register 6 is switched from O to 1 (Fig. 2g), by means of which 1 is recorded from the output of the third D-trigger 10 (Fig. 2i) to the first D-trigger 12.

The timing diagram of the third D-flip-flop 10 (Fig. 2i) is formed using an EXCLUSIVE OR 8 element, the inputs of which receive signals from the output of the K-th (Fig. 2e) and the inverse output of the (K + 1) -th (Fig. 2z) bits of the static register 6. At the direct output of the D-flip-flop 12 appears 1 (Fig. 2k), and at the inverse - О, which causes the appearance of Г at the output of the second AND-NOT 18 element (Fig. 2p), t. e. in the most significant bit of the output code of the CDFD. This 1 will disable the least significant bits of the output code of the CDFD coming through the prohibition block 7, and will hold Г at the output of the OR element 16. At the output of the third

element AND NOT 19. i.e. O is set in the sign bit of the output code of the CCFD (Fig. 2p). CCFD switched to the frequency comparison mode with the O sign.

In the frequency comparison mode 1, the direct output of the first D-flip-flop 12, arriving at the inverse R-input of the sixth D-flip-flop 15, removes its zeroing. By reducing the frequency detuning, the rate of change of the phase difference of the input and reference signals decreases, and at time t2, the frequencies of the input and reference signals become equal in magnitude, the rate of change of the phase difference is zero, after

which changes the sign of the frequency difference and begins to increase from cycle to cycle, the phase difference of the input and reference signals in the direction from 0 to 2 l:. At time t2 there is an abrupt phase shift by

n signal at the output of the fourth D-flip-flop 11 (Fig. 2e) relative to the signal from the inverse output (i + 1) -ro of the category (Fig. 2d) of the static register 6, which are respectively supplied to the D- and C-inputs of the sixth

D-flip-flop 15. The timing diagram of the output of the fourth D-flip-flop 11 (Fig. 2e) is generated using an EXCLUSIVE OR 9 element, the outputs of which receive signals from the i-ro output (Fig. 26)

and inverse output (i + 1} -ro (Fig. 2d) of bits of the static register 6. At time t.3, the inverse output of the (+1} -th bit of the static register b is switched from O to 1 (Fig. 2d) ), with

by means of which 1 is recorded from the output of the fourth D-flip-flop 11 (Fig. 2e) to the sixth D-flip-flop 15. A zero pulse from the inverse output of the sixth D-flip-flop 15 (Fig. 2n), acting on the inverse S-input

the second D-trigger 13. installs at its output 1 (Fig. 2L). Single levels at the outputs of the first AND-NOT element 17 cause a zero-level pulse to appear at its output, with the help of which the D-flip-flops 12 and 13 are turned off first, and then the sixth D-flip-flop 15. At the output of the second AND-NOT element 18 (Fig. 2p) appears O, and at the output of the third AND-NOT 19 element (Fig. 2p) - 1. Occurs

disabling frequency comparison mode. The CDPD enters phase comparison mode and sets the synchronism mode.

In the frequency comparison mode on the interval ti ... t3J, the i least significant bits of the static register 6 are repeatedly switched from zero to single or from single to zero depending on the direction of the phase difference between the pulses of the input and reference signals. In this case, as a result of the contention of the signal edges at the inputs of the second EXCLUSIVE OR 9 element, a pulsed single-level interference appears, which can cause a false transition from the frequency comparison mode to the phase comparison mode. However, the sequential recording of the first state of the output of the second EXCLUSIVE OR 9 element to the fourth D-flip-flop 11, and then the states of the output bits of the counter 1 in the static register b, carried out using the output pulses of the BP 4 coming from the input pulse, includes the possibility switching on from a pulsed interference unit level of the sixth D-flip-flop 15 or the fifth D-flip-flop 14 depending on the direction of the phase difference of the input signals.

Similarly, the operation of the CCFD occurs when the frequency of the input pulses is less than the reference (fex ton). Only in this case, the phase difference of the input signals first increases from cycle to cycle in the direction from 0 to 2 L and the transition to the frequency comparison mode is carried out after turning on the second D-flip-flop 13, and the transition to the phase comparison mode occurs after changing the sign of the frequency difference. when the phase difference of the input and reference signals begins to decrease from cycle to cycle in the direction from 2 p to 0. At this moment, an abrupt phase shift occurs on the signal at the output of the fourth D-trigger 11 relative to the signal from the output of (i + 1) -ro bit statically b of the register, which arrive respectively on the D- and C-D- inputs of the fifth flip-flop 14.

Timing diagrams of the output of the fourth D-trshter 11 and the output of the (i + 1) -ro bit of the static register 6 correspond to the diagrams shown in FIG. 2difig. 2c on the interval ti ... t2J. The fifth D-flip-flop 14 is turned on and the zero pulse from its inverse output, acting on the inverse S-input of the first D-flip-flop 12, sets 1 at its output. Single levels at the inputs of the first AND-NOT 17 element cause a zero-level pulse to appear at its output, by means of which first the D-flip-flops 12 and 13 are turned off, and then the fifth D-flip-flop 14, Frequency comparison mode is turned off. The CCFD goes into phase comparison mode. Turning off the frequency comparison mode in the proposed discriminator is carried out in the immediate vicinity of the equality of the frequencies of the input and reference signals, which leads to a significant reduction in the transition time from the frequency comparison mode to the phase comparison mode.

The value of i should be within the range of 1 i K-1, with a decrease in I having a beneficial effect on reducing the transition time from the frequency comparison mode to the phase comparison mode.

Using the invention will allow

0 in comparison with the known one, reduce the duration and amplitude of the phase error ejection and, therefore, increase the speed of frequency-phase locked loop systems.

5 Based on this technical proposal, a model of a digital frequency-phase discriminator was made. His tests were conducted. The test results are positive.

Claims (1)

0 Claims A digital frequency-phase discriminator comprising a series-connected counter, the input and output of the reset of which are respectively the input 5 counting pulses and a reference pulse input, a static register and a block of prohibition, the first and second D-flip-flops, the D-inputs of which are combined, the C-inputs are connected respectively to the direct and inverse outputs of the (К-Н) -th digit of the static register, the first AND-NOT element, the inputs of which are connected to the direct outputs of the first and second D-flip-flops, and the output to the inverse R-inputs of the first and second 5 About triggers, the second AND-NOT element, the input of which is connected to the inverse outputs of the first and second D-triggers, the OR element in series, whose inputs are connected to the inverse output 0 (K-M) -th sign bit of the static register and the output of the second AND-NOT element, and the third AND-NOT element, the other input of which is connected to the inverse output of the second D-trigger, as well as the first element EXCLUSIVE OR ONLY, one input which and the control input of the prohibition block are connected to the inverse output of the (K + 1) -th digit of the static register, the output of the block is inhibited and the output of the second AND-NOT element 0 are outputs of significant bits of a digital frequency-phase discriminator, and the output of the third AND-NOT element is its output of a signed bit, characterized in that, in order to increase stability and reduce the transition time from the frequency comparison mode in the phase comparison mode, the third D-trigger is introduced into it. connected between the output of the first EXCLUSIVE OR element, the other input of which is connected to the K-ro output of the static register bit, and the combined D-inputs of the first and second D-triggers, the second EXCLUSIVE OR element connected in series, the inputs of which are connected to the output of the 1st, where (1 I K -1} and the inverse output of the (I + 1) -th bit of the static register, and the fourth D-trigger, the fifth and sixth D-triggers, the D-inputs of which are connected to the direct output of the fourth D-trigger , С- inputs - to the direct and inverse outputs of the (I + 1) -th category is static th register, the inverted R-input - to forward and outputs of the first and second D-flip-flops, the inverse outputs of the fifth and sixth D-flip-flops are connected to the inverse S-inputs of the first and second D-flip-flops, respectively, as well as a block for coupling pulses of the input signal to the counting pulses, one input of which is connected to the input of the counting pulses , the other is the input of the digital frequency-phase discriminator, the first output is connected to the C-inputs of the third and fourth D-flip-flops, and the second output is connected to the write enable input of the static register. Fig. { /1 m // i ft- .. L - / Figure 2