RU1807524C - Buffer storage - Google Patents

Abstract

The invention relates to computing and automation and can be used in various devices for processing and transmitting information. The purpose of the invention is to simplify the device. The device is intended for buffer storage of input information and output to processing (accumulation) devices when coordinating the operating speeds of input and output devices. The device comprises a memory unit, a write decoder, a read decoder, a write address counter, a read address counter, a write / read permission control counter, first and second AND elements, an EXCLUSIVE OR element, corresponding communications. By reversing the control counter and changing the setup code, two matching blocks were eliminated, which simplified the design of the device. 1 ill.

Description

The invention relates to pulse and computer technology and can be used in various information processing and transmission devices.

The purpose of the invention is to simplify the circuit of the device.

The drawing shows a functional diagram of the device.

The buffer storage device contains: 1 - a drive unit, 2 - a read address counter, 3 - a write address counter, 4 - a reverse counter, 5, 6 - read and write address decoders, 7 - an EXCLUSIVE OR element, 8 - an installation bus, 9, 10 - AND elements, 11 - write control bus, 12 - write data bus, 13 - read data bus, 14 - read control bus.

Buffer storage device operates as follows.

Before starting work on the bus 8, an installation pulse arrives, resetting the counters 2 and 3 and setting the counter 4 to a state in which 1 is set at all outputs (at the input of the parallel preset code record). The size of the counter 4 is taken 2 more than the bit network of the drive to control the operation of the device. At the same time, during the initial installation, the high-order bits of the counter, combined through the EXCLUSIVE OR element, form an enable signal for writing, and the high-order bit prohibits reading (the buffer is empty). When a write pulse arrives, counter 4 is set to the zero state in which reading is allowed (and writing), if the next pulse is reading, then after it counter 4 is set to a state in which reading is prohibited by the oldest bit

house, and recording is allowed. Consider a situation in which all the bits of counter 4, except for the older ones, are set to 1. If a write pulse arrives, then counter 4 will go into the state when 2n + 1 - bit is set to 1 and prohibit recording (buffer full). The rest of the operation is similar to the prototype.

Thus, while maintaining the operation of the device, the circuit implementation is simpler than in the prototype,

Claims (1)

SUMMARY OF THE INVENTION A buffer memory device comprising a memory unit, a write decoder, a read decoder, a write address counter, a read address counter, a control counter, the first and second AND elements, the setting inputs of the write and read address counters and the control counter being combined and being an input the device settings, the input of the direct count of the control counter and the count input of the write address counter are combined and connected to the output of the first AND element, the first input of which is the recording input of the device, the second input of the first AND element is a write disable input of the device, the read inhibit input of which is the first input of the second element And, the second input of which is the read input of the device, the output of the second element And is connected to the counting input of the read address counter, the outputs of which are connected to the corresponding inputs of the read decoder, the outputs of which are connected to the read address inputs a memory unit, the outputs of which are the information outputs of a device, the information inputs of which are the information inputs of a memory unit, the address entries of which are connected to the outputs of the recording decoder, the inputs of which are connected to the outputs of the counter of the recording address, characterized in that, in order to simplify the device, an EXCLUSIVE OR element is inserted into it, the output of which is connected to the second input of the first element AND, the penultimate output of the control counter is connected to the first input of the element EXCLUSIVE OR, whose second input and the first input of the second AND element combined and connected to the last output of the control counter, the input of the countdown of which is connected to the output of the second element I.  (Јyvep wcr) -ЈЈ. eleven / 3 ff “N L Zlpr zp (polo) W / usg - / 4f 3) 1 / I