RU1798921C - Conveyer converter from code of number system of remainder classes to position code - Google Patents

Abstract

The invention relates to the field of computer engineering and can be used in equipment operating in positional-residual number systems. The aim of the invention is to increase productivity. The converter contains in each cascade 1 a memory unit 6, a positional adder 7, a register 9 and a subtractor 8 in the aggregate of modules 2 il.

Description

Sri 2

The invention relates to computer technology and can be used in computers operating in a number system in residual classes (MSCR) to convert the number of numbers represented in the MSCC into a positional code,

The aim of the invention is to reduce the computational time by using a conveyor structure in constructing the converter.

FIG. 1 shows a block diagram of a converter: FIG. 2 is a structural diagram of the Kth cascade (K 1, 2, ..., M, where M is the total number of cascades).

The converter contains a conversion cascade 1, a clock input 2 connected to all the clock inputs of the cascades, information inputs 3. Inputs З.Х.К and 5.К (X К, К + 1, ..., М - number of a group of residues) ow are respectively the inputs of the residues and the sum of the Kth cascade, and its outputs of the residues and the sum are the outputs Z.T.K + 1 and 5.K + 1, respectively (TK + 1, K + 2, .. ,, M) . The cascade contains a block 6.K of memory, a binary adder 7.K, a subtractor 8.K for the totality of modules and a register 9.K,

The cascade works as follows. To the input of Z.K.K. connected to the input of the block, B.K., the analyzed group of residues is fed, At the outputs of block 6.K, the same number is generated, but in different number systems:, at the output connected to the adder, - in the positional code, at the output connected to the subtractor, in the SSC. At the outputs of the subtractor and the adder, a difference is formed, respectively, in the aggregate of modules older than the analyzed group and the sums in the position code, which, with the arrival of a clock pulse at input 2, are recorded in register 9.K and fed to the input of the next stage. When constructing the converter, you can exclude the adder from the first stage and the subtractor from the last. Thus, in each cascade, a decrease in the initial number presented in the QCMS occurs, and the sum in the position code coming from previous cascades increases by the same amount. After conversion, sequentially in all stages of the output of the latter, the number represented in the QCMS will decrease to zero, and the sum will increase to a positional number numerically equal to the original number in the QCMS. Since, during one cycle, the conversion of a given number occurs in only one stage and does not affect the state of other stages, in other stages simultaneously, in the same cycle, conversion can occur

other numbers. When processing the stream of numbers, a new number is supplied to the input of the device in each clock cycle, and the converted number is removed from the output (it must be taken into account that

the conversion result is generated after M clocks after applying this number to the input of the converter).

The table shows an example of programming the memory blocks of a converter that converts from SSOK with modules P1 2, P2 3, PZ 5, P4 7 to a binary positional decimal code 8-4-2-1 when using three stages converting into groups residues: the first - by P1 and. P2, second - by

rz, the third - in RA.

Consider the example of converting a single number, presented in the RMSF with modules P1 2, P2 3, P3 5, P4 7, and 197 (1,2,2,1) juice.

in the first clock cycle, this number is fed to the input of the first stage, while at the input of the memory block, the residues by modules P1 and P2, respectively equal to 1 and 10, are received, at the output of the memory block we get subtracted

(000, 101) and the term 101. At the output of the subtracter, we get “2-О- - # subt (010, 001) juice - (000, 101) juice (010, 011) juice.

With the arrival of the second clock pulse, the difference (010, 011) and the term (101) are recorded in the register of the first stage, and the remainder modulo RP equal to (010) will be transferred to the memory block of the second stage. At the output of the memory block, we obtain the subtracted 101 and the term 01 0010, at the output of the subtractor U1, at the output of the adder, 01 0111.

With the arrival of the third clock pulse, the difference and the sum received in this stage are recorded in the register of the second stage. In the memory block of the third stage

the remainder modulo Р4 equal to 101, at the output of the memory block we get 1 1000 0000, at the output of the adder - (01 0111) 2nd + (1 1000 OOOOJ2-10 О 1001 0111) 2-10 197. After the arrival of the fourth clock pulse the result of the calculation is written to the register of the third stage and will be output to the device.

The conversion time in one cascade is:

Tk T1 + T2 + TK, where Tt is the sampling time of the memory unit.

T2 is the greater of the delay times of the adder and subtracter, TK is the register delay time.

The minimum possible tact TT for the converter will be the maximum of the cascade conversion times (usually

last cascade), it will be less than in the prototype, because there at this time at least the delay times of the multiplexers are added,

The singular conversion time is determined as follows:

Tr.r. M TT, which is less than what is required in the prototype.

The advantages of the apparatus of the present invention are manifested when working with streams of numbers. In this case, the processing time of a stream of A numbers will be equal to:

Tp.p. M TT + (A-1) TT (M + A-1) TT. and the average conversion time of one number in the stream:

Tsr.r. (1 + (M-1) / A)

With the increase in the number of numbers in the stream Tsr.r. tends to TT, which is already more than N times less than that required for conversion of the prototype, where N M is the number of conversion clocks in the prototype.

Total hardware costs are equal to:

 c-lc ,.

. I 1

where Ci - hardware costs for the 1st stage,

Ci C1 + -C2 + C3 + C4, where C1. C2, C3, C4 - hardware costs for the memory unit, adder, subtractor and register of the 1st stage.

This shows that the total cost of any cascade is less than the cost of the prototype, and you can write:

S M Ser N Ref.

where Ser is the average total cost per stage of the proposed device,

Spr - hardware costs for the prototype, Spr Ser.

This shows that when constructing a machine that works in a QMS with large data flows necessary for output, it is economically feasible to use the proposed device, because in order to obtain the same speed as in the proposed device, it is necessary to connect in parallel at least N devices operating according to the prototype principle.

Claims (1)

The claims A conveyor converter of numbers from the number system code in residual classes to a position code containing in each stage a memory block, a position adder and a register, the first output of the memory block of each stage of the converter being connected to the input of the first 5th term component of the position adder of the same stage of the converter , the output of the positional adder of each stage of the converter is connected to the first information input of the register group. 0 of the same cascade of the converter, the clock input of the converter is connected to the write enable input of the register of each cascade of the converter, characterized in that, in order to increase productivity5, each cascade of the converter contains a subtractor in the aggregate of modules, the second output of the memory block each stage of the converter is connected to the input of the subtracted subtractor by the totality of the modules of the same stage of the converter, the outputs of the group of the subtractor by the set of modules of each stage of the converter are connected Nena respectively, to data inputs except pervo5 th, the register groups of the same stage converter, a logic-zero input, the converter is connected to the second summand vhodom.vtoro- positional adder of the first stage of the transducer, the first 0 the information input of the converter group is connected to the address input of the memory block of the first stage of the converter, the information inputs, except for the first one, the group of the converter are connected respectively to the inputs of the decremented one, the group of the subtractor according to the set of modules of the first stage of the converter, the first output of the register group of the last stage of the converter is the output converter, the first output of the register group of the k-th (to 1-M-1, M is the number of groups of simultaneously converted residues) of the converter cascade is connected with the input of the second term of the positional adder 5 (k + 1) -ro cascade of the converter, the second output of the register group of the k-ro cascade of the converter is connected to the address input of the memory block (k + 1) -ro of the cascade of the converter, from the third no (M-k-M) -n the outputs of the group 0 register k-ro of the cascade of the converter are connected respectively to the inputs of the reduced group of the subtractor according to the set of modules (k + 1) -ro of the cascade of the converter. FIG. /