SU807317A1 - Device for solving algebraic equation systems - Google Patents

Description

(54) DEVICE FOR SOLVING SYSTEMS OF ALGEBRAIC EQUATIONS

one

The invention relates to computing and can be used to solve systems of algebraic equations.

A device is known that allows to obtain the values of variables corresponding to the solution of a given system of linear algebraic equations / representing a set of combinational decision nodes, such as a multi-bit multiplier by a constant coefficient, a multi-bit adder, a multi-bit integrator, etc., connected between In accordance with the mathematical description of the problem being solved, the solution is found as an established transition process. feedback circuit 1,

However, the use of discrete logic elements to build the above set of combinational decision nodes and operating in feedback schemes does not always allow the circuit to become stable because of the occurrence of congestion caused by the spread of the delay parameters of the logic elements.

The closest in technical essence to the present invention is a device consisting of the first and second groups of adders, the first and second groups of combinational scale nodes and inverters, the device inputs are connected to the inputs of inverters and the first inputs of the adders of the first group, the outputs of the Inventors are connected with the first inputs of the adders of the second group, the outputs of the first and second groups of combinational scale nodes are connected respectively with the second inputs of the sum of 5 tori of the first and second groups, the outputs of the totalizers of the second the second group are connected to third inputs of the adders of the first group, and the outputs of the adders of the first group (connected to a first input

0 and the second group of combinational large-scale tabular nodes 2.

The disadvantage of this device is the narrow class of tasks

5, due to the occurrence and generation due to the congresses in the circuit, caused by the variation of the delay parameters of the logic elements.

The purpose of the invention is the expansion of the class of tasks.

0 The goal is achieved by the fact that the device containing the first and second groups of adders, the first and second scale nodes and elements are NOT, the device inputs are connected directly to the first inputs of the first group adders and through the corresponding elements NOT to the first inputs the adders of the second group, the outputs of the scale nodes of the first and second groups are connected respectively to the second inputs of the adders of the first second group, the outputs of the adders of the second group are connected to the third inputs of the adders of the first group , a group of D-flip-flops, a group of comparators, a switch, a group of delay elements and a generator of single pulses are introduced, the outputs of the adders of the first group are connected to the first inputs of the group comparators and to the first inputs of the D-flip-flops of the group, the outputs of which are connected to the outputs of the device, the second inputs of the group comparators and to the inputs of the scaled nodes of the first and second groups, the comparators of the group are connected to the corresponding inputs of the comparator, the outputs of which are connected to the first-end inputs of the group delay elements, interconnected in series, the output of the latter of the delay element is connected to the input of a generator of single pulses, the output of which is connected to the second inputs of the D-flip-flops of the group. The drawing shows a block diagram of the device. The device contains inputs 1 and 2 of the HE 3 elements, the first 4-7 and the second 8-11 groups of large-scale nodes, the first group of adders 12 and 122, the second group of adders 12 and 12, the group of D-flip-flops 15, the group of comparators 16, the switch 17 , a group of delay elements 18, a generator of 19 single pulses and outputs 13 and 14 of the device. The device works as follows. The highest bits of the values of the right-hand side F are fed to the inputs 1 of the device; - FYJ of a given system of equations represented in the matrix D as X Bv + F / The lower bits of the values of the right-hand side F - F {equation systems (1) arrive at the inputs 2 of the device (1) At the outputs 13 of the device, the values of the higher bits of the desired vector of unknowns Equation (1) xt) - x and at outputs 14 of the device, the output of the low-order bits x - x. The first group of combinational scale nodes 4–7 multiplies the unknown vector x by the coefficients of the matrix B of the system of equations (1), and the second group of combinational scale nodes 8–11 multiplies the desired vector of variables x by the coefficients of the matrix A defined by expression A E - B (2) At the adder 12-j, the partial products of the desired vector of variables x are summed by the coefficients of the first row of the matrix A, defined by expression (2) with the inverted value of the component free Lenov F. The adder 12 performs the summation of the partial products of the desired vector of variables x by the coefficients of the nth row of the matrix A with the inverted value of the components of the free members of P, where n is the order of the solved system of equations. On the adder 12, the partial products of the desired vector of variables x are added by the coefficients the first row of the matrix B, defined by expression (1), with q lowest bits of the sum obtained on the adder 12. and with the value of the coefficients of the free members F, the adder 122 summarizes the partial products of the desired vector of variables x by the coefficients of the nth row of the matrix B with q lower-order digits of the sum obtained on the adder 12 and with the value of the component of the free members F, B the desired state the output of the group of D-flip-flops 15 is written the vector of initial approximations °. Upon arrival at the inputs: 1 and 2 devices of the vector of the right-hand side F of equation (1), at the outputs of the first group of adders 12. and 122 are generated during the transient time in the circuit of the device, the intermediate value of the vector x. The comparators group 16 produces a one-by-one comparison of the vector components at the output of the D-flip-flop group 15 and the vector component at the input of the D-flip-flop group 15 x, and as soon as a change in any bit of the D-flip-flop 15 group occurs, the corresponding comparator 16 generates a mismatch signal which arrives at the switch 17. The switch 17 transmits a mismatch signal to the corresponding input of the delayed elements connected in series between each other. The delayed mismatch signal from the output of a series-connected group of delay elements 18 is fed to the input of a single pulse generator 19, which produces a control sync pulse input to the second inputs (synchronization inputs) of the group

D-flip-flops 15 and record the intermediate value of the code x to the D-flip-flops group 15. A new state of the outputs of the D-flip-flops group 15 is fed through a feedback circuit to the inputs of the first and second groups of combinational scale nodes and after the time of transients in the circuit diagram, the outputs of the first group of adders 12 and 12jj work out a new value of intermediate code X, which is compared on the group of comparators 16 with the code value x on the outputs of the group of D-flip-flops 15, and so on. The process is repeated until the equality of the code values at the inputs and outputs of the D-flip-flop group 15 is established.

To prevent the circuit from malfunctioning, the following restrictions on the parameters of the group of delay elements 18 must be observed:

1. The front pulse of the output of the generator 19 single pulses, determined by the delay time of the delay elements 18, should appear after the transients at all outputs of the first group of adders 12 and 123. This condition is satisfied by the following relations

p-1

Lr: T-2d, l

t T .... p PH 3 -I

where Tp (, 2 ..., p) is some parameter j-ro of the information output of the first group of adders 12, and 12 / j defined by the relation

(Bcp cpr

.-iniax

T; max

t + o /

Where

the maximum time Pe1 WCSX running process on the 1st output of the first group of adders 12 and 12.2; the minimum transition time for the w-in process after the output of the first group of adders 12 and 122;

the minimum W4H delay time in the group of comparators 16 and the generator 19 of single pulses; the maximum switching time oix of the D-flip-flop; maximum variation of the time interval for simultaneous arrival of information at inputs 1 and 2 of the device;

,: C) sh.5 is the longest transient process time of the entire set of MaKCHMaAbHbix values of the duration of transient processes at the i-th output

the first group of adders (, 2, ... p) with ij j; p is a value that is numerically equal to the product of the number of bits of the representation of the desired variables by the order of the solved system of equations.

2, Races between conditions caused by the fact that during one transition, in the first process in the first 4-7 and during

o the second 8-11 groups of scale nodes and adders 12, 122, 2, 124, a generator of 19 single pulses outputs a series of clock pulses arriving at the second inputs of the D-trig 5 Gerov 15 group. This limitation is removed by selecting the duration of the clock pulses generated by the generator 19 of single pulses according to the following relationship

0

C (4r "ax-t, - jyi-in,) + (ti ,,) + T) vnoix Dmin

-D is the sync pulse pulse duration from the generator output of 19 single pulses of 5 ows;

the maximum running time of a running process in one of the comparators of the group of comparators 16 and the generator 19 of single pulses;

- minimum time switch DVnW D-flip-flop. The use of additional elements and new connections between them favorably distinguishes the proposed device for solving systems of algebraic equations from the known, since it allows one to find a solution for

0 of a wider class of tasks by eliminating the generation in the device circuit caused by the spread of the parameters of delays in logic elements, which increases the pattern of application of such devices.

five

Claims (2)

Invention Formula Device for solving systems 0 algebraic equations containing the first and second groups of adders, the first and second groups of scale nodes and elements of the NV, and the inputs of the device are connected directly to the first inputs of the adders of the first group and, through the corresponding elements, NOT to the inputs of the second group, outputs of scale nodes first and second Group 0 is connected respectively to the second inputs of the adders of the first and second groups, the outputs of the adders of the second group are connected to the third inputs of the adders of the first group. 65 featured what, f in order to expand the class of tasks, rpi r D-flip-flops, a group of comparators, a switch, a group of delay elements and a single pulse generator are entered into the device, the outputs of the adders of the first group are connected to the first inputs of the comparators of the group and the first inputs of the D-flip-flops of the group, outputs which are connected to the outputs of the device, to the second inputs of the group comparators and to the inputs of the scale nodes of the first and second groups, the outputs of the group comparators are connected to the corresponding inputs of the switch, the outputs of which are connected s to the first inputs of the group delay elements interconnected in series, the last delay element output coupled to an input of the single pulse generator, whose output is connected to the second inputs / D-triggers. groups. Sources of information taken into account in the examination .one. USSR Author's Certificate 428405, class G 06 F 7/34. 1974. 2. USSR author's certificate for application No. 2506823 / 1S-24, cl. G 06 F 15/32, 1978 (prototype).