RU2805259C1 - Code-to-frequency converter - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: code-to-frequency converter contains input 1 of reference frequency F₀, output 2 F_out of the converter, input bus 3 N_G, binary multipliers 4 and 5 with digital inputs 6 N_p and 7 N_k, while each binary multiplier 4 and 5 consists of first 8 and second 9 binary counters and first 10 and second 11 multiplexers, respectively. The converter also contains reversing binary counter 12 and write input WR 13, connected to the corresponding input of reversing counter 12, the digital input of which is connected to input bus 3 N_G, the summing input is with the output of first 4 binary multiplier, and the subtracting input of reversing counter 12 is combined with output 2 F_out of the converter and with the output of second 5 binary multiplier, while the digital output of counter 12 N_k connected to digital input 7 of second binary multiplier 5.

EFFECT: simplification of the code-to-frequency conversion device with automatic compensation without correction.

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Description

The claimed technical solution relates to automation and computer technology, as well as to automatic control systems and can find application in numerical control systems, in measuring and computing devices and in the creation of elements of impulse neural networks, in particular prototypes of impulse neurons.

A device is known [RF Patent No. 2006918, IPC G 06 F 7/68, 1994] that implements the formation of an output frequency proportional to the input code, containing a binary counter, a delay element, an n-channel multiplexer, the first and second AND elements, a trigger and a pulse shaper, the first the input of the first AND element is connected to the output of the delay element, the outputs of the bits of the binary counter are connected to the corresponding address inputs of the n-channel multiplexer, the zero information input of which is connected to the control input of the converter, and the information inputs are connected to the inputs of the corresponding bits of the digital input of the converter, the first information input connected to the counting input of the binary counter and the output of the second AND element, the first input of which is connected to the input of the reference frequency, to the input of the pulse shaper and to the strobe input of the n-channel multiplexer, with an expansion input, a transfer output, an information input, an operating mode setting input, and a counting input The trigger input and reset input are connected functionally accordingly.

The disadvantage of the converter is the inability to influence the output frequency to reduce the error.

Of the analogues, the closest in terms of set of characteristics and technical essence is the code-to-frequency converter [RF Patent No. 2285946, publ. 10.20.2006], which was chosen as a prototype.

In the prototype, the conversion error is reduced due to the introduction of digital correction of the additive and multiplicative components.

A code-to-frequency converter containing a reference frequency input F ₀ , an output F out _{of the} converter, an input bus N _G , binary multipliers with digital inputs N _p and N _k , wherein each binary multiplier consists of the first and second binary counters, and the first and second multiplexers, respectively, and the outputs of the bits of the first and second binary counters are connected to the corresponding address inputs of the first and second multiplexers, the information inputs of which are the corresponding digital inputs N _p and N _k binary multipliers, and the reference frequency input F ₀ of the converter is connected to the clock inputs F of the first and the second binary multipliers, simultaneously being the clocking inputs of the first and second binary counters, as well as zero information inputs of the first and second multiplexers, respectively, while the outputs of the multiplexers F _y1 and F _y2 are simultaneously the outputs of the first and second binary multipliers, respectively.

In addition, the converter contains a third binary counter, three inverters, three comparators, a third multiplexer, an AND element, second and third input lines, all input lines are connected to the corresponding comparators, which are controlled by the third binary counter, and their outputs are connected, respectively, to the third inverter and a third binary counter, with the first input of the AND element, with the second input of the AND element, while the output of the AND element is connected to the zero input of a two-channel multiplexer, the first and second outputs of which are connected to the outputs of the first and second binary multipliers, respectively, and the output of this multiplexer is the output the entire converter, and the first and second inverters are included in the circuits of the lower digits of the converted and correcting codes, respectively, and the output of the third inverter is connected to the second input of the third binary counter, and the third input of this third counter is combined with the input of the reference frequency of the converter.

The prototype works as follows.

Let the number of bits of the first binary multiplier be four, and the second – two. Let all binary counters be in the zero state at the initial moment of time, and an input pulse sequence is supplied to the input of the reference frequency F ₀ , under the influence of which the binary counters can change their output values. The most significant (sign) bit a ₁ of the input converted code N _p is supplied to the input of the first inverter, and the correction code _N to the input of the second inverter.

Thus, codes are supplied to the digital inputs of the first and second binary multipliers And respectively. The first binary counter sequentially in time generates at its output values in the range from 0 to 2 ⁿ -1 = 15, and the second counter – from 0 to 2 ^to -1 = 3. The output values of the first binary counter are the address inputs of the first multiplexer.

So, when the output value of the first binary counter is equal to “0”, “2”, “4”, “6”, “8”, “10”, “12” or “14”, a pulse will be inserted into the output uneven pulse sequence F _y1 reference frequency F ₀ of the converter, if . With the input value of the first binary counter equal to “1”, “5”, “9” or “13”, a pulse will be inserted into the output uneven pulse sequence F _y1 if a ₂ = 1. With the output value of the first binary counter equal to “3 "or "11", a pulse will be inserted into the output uneven pulse sequence F _y1 if a ₃ = 1. When the output value of the first binary counter is equal to "7", a pulse will be inserted into the output uneven pulse sequence F _y1 if a ₄ = 1. The output pulse sequence F _y1 at the output of the first binary multiplier is characterized by the frequency

,

where i is the number of the digit of the converted code N _pr .

The output values of the second binary counter are the address inputs of the second multiplexer. Thus, when the output value of the second binary counter is equal to “0” or “2”, a pulse of the reference frequency F ₀ of the converter will be inserted into the output uneven sequence of pulses F _y2 , if b̄ ₁ = 1. When the output value of the second binary counter is equal to “1” , a pulse will be inserted into the output uneven pulse sequence F _y2 if b ₂ = 1. The output pulse sequence F _y2 at the output of the second binary multiplier is characterized by frequency

,

where j is the number of the digit of the correction code N _corr .

The capacity of the third binary counter is n+1. This counter generates sequentially in time values at its output in the range from 0 to 2 ⁿ + 2 ^k –1 = 19, and the first comparator accordingly limits the range of changes in the output values of the third counter. If the output value of the third binary counter is less than 2 ⁿ + 2 ^k –1 = 19, then a single signal is generated at the output of the first comparator, which serves as the count enable signal for the third binary counter. Otherwise, a zero signal is generated at the output of the first comparator. The third inverter inverts the signal from the output of the third comparator. With a zero signal at the output of the first comparator, the output signal of the third inverter is equal to one. When the output signal of the third inverter is equal to one, the third binary counter is reset to zero, after which the counting process resumes.

The second comparator compares the output value of the third binary counter with the constant T _N –1 = 15. The third comparator compares the output value of the third binary counter with the constant T _N + T _K = 20. The AND element combines the results of the comparison of the second and third comparators. If the output value of the third binary counter is greater than the value T _N –1 = 15 and at the same time less than the value T _N + T _K = 20, then a single signal is supplied to the zero information input of the third multiplexer, otherwise a signal equal to zero is supplied, and the output frequency-pulse flow converter becomes the output stream of the first binary multiplier. When the signal at the zero information input of the third multiplexer is equal to one, the output frequency-pulse stream of the converter becomes the output frequency-pulse stream of the second binary multiplier. Thus, the output sequence of pulses F _{out of} the converter is characterized by a frequency

.

At the same time, the use of digital correction makes it possible to reduce the additive and multiplicative components of the conversion error.

The disadvantage of the prototype is the complexity of organizing external correction.

The problem to be solved by the claimed invention is to simplify the device by organizing internal compensating feedback when generating an output pulse flow.

The technical result is the simplification of the code-to-frequency conversion device with automatic compensation without correction.

The specified technical result is achieved due to the fact that in the code-to-frequency converter containing the reference frequency input F ₀ , the output F _out. converter, input bus N _G , binary multipliers with digital inputs N _p and N _k , wherein each binary multiplier consists of the first and second binary counters, and the first and second multiplexers, respectively, and the outputs of the bits of the first and second binary counters are connected to the corresponding address inputs of the first and second multiplexers, the information inputs of which are the corresponding digital inputs N _p and N _k binary multipliers, and the reference frequency input F ₀ of the converter is connected to the clock inputs F of the first and second binary multipliers, simultaneously being the clock inputs of the first and second binary counters, as well as zero information inputs of the first and second multiplexers, respectively, while the outputs of the multiplexers F _y1 and F _y2 are simultaneously the outputs of the first and second binary multipliers, respectively, an up/down binary counter and a write input WR are introduced, connected to the corresponding input of the up/down counter, the digital input of which is connected with the input bus N _G , the summing input is with the output F _y1 of the multiplexer, and the subtracting input of the up/down counter is combined with the output F _{out of} the converter and with the output F _y2 of the multiplexer, while the digital output of the counter N _is connected to the digital input of the second binary multiplier.

The essence of the proposed invention is to create a code-to-frequency converter without initial complex adjustments using an iterative method for implementing the averaging operator by functionally generalizing the process of converting code to frequency, both for the feedforward circuit and for the feedback circuit.

The essence of the proposed invention is illustrated by drawings, where in Fig. 1 shows a functional diagram of the proposed code-to-frequency converter;

in fig. Figure 2 shows examples of circuit testing, which was carried out using VerilogHDL device modules synthesized using the Quartus Prime CAD system; during modeling, the bit depth was set to 8; Fig. 2a shows the device’s response to the influence of a signal during decrement, and Fig. 2b - when the values of counter CT2 are incremented.

Code-to-frequency converter (Fig. 1), containing input 1 of the reference frequency F ₀ , output 2 F _{out of} the converter, input bus 3 N _G , binary multipliers 4 and 5 with digital inputs 6 N _p and 7 N _k , with each binary multiplier 4 and 5 consists of the first 8 and second 9 binary counters, and the first 10 and second 11 multiplexers, respectively, and the outputs of the bits of the first 8 and second 9 binary counters are connected to the corresponding address inputs of the first 10 and second 11 multiplexers, the information inputs of which are the corresponding digital inputs 6 N _p and 7 N _{k of} binary multipliers 4 and 5, and input 1 of the reference frequency F ₀ of the converter is connected to the clock inputs F of the first 4 and second 5 binary multipliers, which are simultaneously the clock inputs of the first 8 and second 9 binary counters, and also zero information inputs of the first 10 and second 11 multiplexers, respectively, while the outputs of the multiplexers 10 F _y1 and 11 F _y2 are simultaneously the outputs of the first 4 and second 5 binary multipliers, respectively.

In addition, the converter contains a reversing binary counter 12 and a write input WR 13, connected to the corresponding input of the reversing counter 12, the digital input of which is connected to the input bus 3 N _G , the summing input is connected to the output of the first 4 binary multiplier, and the subtracting input of the reversing counter 12 combined with the output 2 F _{out of} the converter and with the output of the second 5 binary multiplier, while the digital output of the counter 12 N _is connected to the digital input 7 of the second binary multiplier 5.

The device works as follows.

Input 1 of the converter receives a pulse sequence with a reference frequency F ₀ . Based on the signal to input WR 13, the code _NG is written from input bus 3 to the up/down counter 12.

Let the number of bits of binary multipliers 4 and 5 be n, and binary counters 8 and 9 be in the zero state. Under the influence of the reference frequency F _0, binary counters can change their output values.

Thus, codes a ₁ , a _2, a ₃ , ... _, a _n and b ₁ , b ₂ , b ₃ , ..., b _n are supplied to the digital inputs of the first 6 and second 7 binary multipliers 4 and 5, respectively. The first 8 and second 9 binary counters, sequentially in time, generate at their outputs values in the range from 0 to 2 ⁿ –1, which are the address inputs of the first 10 and second 11 multiplexers, respectively.

So, for example, with the output values of the first 8 binary counter equal to “0”, “2”, “4”, “6”, “8”, “10”, “12” or “14”, the output uneven pulse sequence F _y1, a pulse of the reference frequency F ₀ of the converter will be inserted if a ₁ = 1. When the input value of the first 8 binary counter is equal to “1”, “5”, “9” or “13”, a pulse will be inserted into the output uneven pulse sequence F _y1 if a ₂ = 1. With the output value of the first 8 binary counter equal to “3” or “11”, a pulse will be inserted into the output uneven pulse sequence F _y1 if a ₃ = 1. With the output value of the first 8 binary counter equal to “7 ", a pulse will be inserted into the output uneven pulse sequence F _y1 if a ₄ = 1. The output pulse sequence F _y1 at the output of the first 4 binary multiplier is characterized by frequency

,

where i is the number of the digit of the converted code N _p .

The output values of the second 9 binary counter are the address inputs of the second 11 multiplexer. So, for example, with the output value of the second 9 binary counter equal to “0”, “2”, “4”, “6”, “8”, “10”, “12” or “14”, the output uneven pulse sequence F _y2 a pulse of the reference frequency F ₀ of the converter will be inserted if b ₁ = 1. When the output value of the second 9 binary counter is equal to “1”, “5”, “9” or “13”, a pulse will be inserted into the output uneven pulse sequence F _y2 , if b ₂ = 1.

Further, similarly to the first 4 binary multiplier, the output sequence of pulses F _y2 at the output of the second 5 binary multiplier is characterized by frequency

,

where j is the number of the digit of the compensating code _Nk .

The output frequency-pulse stream of the second 5 binary multiplier becomes the frequency-pulse output 2 of the converter.

Thus, the output sequence of pulses F _{out of} the converter is characterized by a frequency

.

The operation of the converter is based on the principle of automatic compensation of frequency-pulse sequences, implemented using negative feedback, and a reversing counter is used as a comparison circuit that generates an error signal in the feedback loop, with the help of which frequencies are subtracted and the resulting difference is integrated with the output result in the form of a binary code to control the binary multiplier that produces the output frequency.

The condition for dynamic equilibrium of the converter is the equality of the increments of the codes of the adding and subtracting circuits in the reversing counter ΔN ₊ = ΔN _- .

As a result, the average values of the frequencies of pulse sequences F _y1 and F _y2 per cycle T _c of the unevenness interval are equal to each other F _y1 = F _y2 , and no external correction is required

.

The timing diagram (Fig. 2a) shows the response of the device to the influence of the WR signal at G=64, A=32. At the moment of 180 ns, the number 64 is loaded into the counter, which is gradually decremented to the value 31, after which the code value on the counter averaged over the period of operation of the device is 32. At the beginning of operation, the intensity of the pulses at the output of the device (at the output of the second binary multiplier 5, in the diagram the signal F_11) corresponds to an average value of 64, gradually decreasing to a value of 31/32.

In fig. Figure 2b shows the device’s response to the influence of the WR signal at G=32, A=64. At 180 ns, the number 32 is loaded into the counter, which is gradually incremented to the value 61, after which the code value on the counter averaged over the period of operation of the device is 61/62. At the beginning of operation, the intensity of the pulses at the output of the device (at the output of the second binary multiplier 5, signal F_11 in the diagram) corresponds to an average value of 32, gradually decreasing to a value of 61/62.

The proposed converter, in comparison with the prototype, is a simpler device - in the distinctive part it contains only one up/down counter and a WR write input, while in the prototype the distinctive part includes a binary counter, three inverters, three comparators, a multiplexer, an AND element, two input tires.

Claims (1)

A code-to-frequency converter comprising a reference frequency input, a converter output, an input bus and two binary multipliers with digital inputs, wherein each binary multiplier consists of a first and second binary counter and a first and second multiplexer, respectively, and the bit outputs of the first and second binary counters connected to the corresponding address inputs of the first and second multiplexers, the information inputs of which are the corresponding digital inputs of binary multipliers, and the reference frequency input of the converter is connected to the clock inputs of the first and second binary multipliers, which are simultaneously the clock inputs of the first and second binary counters, as well as zero information inputs of the first and second multiplexers, respectively, while the outputs of the multiplexers are simultaneously the outputs of the first and second binary multipliers, respectively, characterized in that the converter additionally contains an up/down binary counter and a write input connected to the corresponding input of the up/down counter, the digital input of which is connected to the input bus, the summing input is with the output of the first binary multiplier, and the subtracting input of the up/down counter is combined with the output of the converter and with the output of the second binary multiplier, while the digital output of the counter is connected to the digital input of the second binary multiplier.