RU1791955C - Frequency multiplier - Google Patents

Abstract

Relate invention; to the field of automation and computer engineering. Whole. ,;. . . /. 2 v of the invention is a simplification. The frequency multiplier comprises a frequency divider 1, a period meter 2, a digital subband code generator 3, a controllable one, a frequency divider 4, a code converter 5, and a digital switch 6. The object of the invention is achieved by simplifying the operation algorithm, simplifying the implementation of blocks and inter-block communications. 1 ill.

Description

The invention relates to the field of automation and computer engineering and can be used in devices for frequency measurements.

The aim of the invention is to simplify:

The drawing shows a structural circuit of a frequency multiplier.

The frequency multiplier comprises a frequency divider 1, a period meter 2, a digital subband 3 code generator, a controlled frequency divider 4, a code converter 5, a digital switch b, a counting input 7, an information input 8 and an output 9.

The frequency multiplier operates as follows.

Frequency divider 1 divides the frequency of pulses foi from the counting input of frequency divider 1 by the number K, which determines the multiplication factor. The meter 2 of the period Tf of the input signal from the information input 8 forms a digital equivalent (, 2 ...) of this period by counting pulses f02 foi / K. Thus, at its output during each

of the subsequent period TC-i of the input signal, information on the value of the previous period T of the input signal is presented in the form of digital equivalents. This equivalent is formed by counting the pulses from the output of the frequency divider 1. The number of bits of the digital equivalent NI is determined by the expression q s + n, where s is the number of low order bits, n is the number of high order bits connected to the code converter 5. When

etomr 1od2 g-p-b where fH4 is the value

fhlHK

frequency of the lower limit of the frequency range of the input signal of the frequency multiplier. Besides,

J

| Yu

Jot

ate

(Oh yeah

hf

foi

to

S Iog2 -

fa

foi

to

where ffi4 is the frequency value of the upper boundary of the frequency range of the input signal. Thus, with - fx fen the change

NJ is implemented in the s lower order bits of the measurer 2 of the period, and the higher s-th bit is always logical 1. When

k l. f., where j - 0,1,2.: .., n, corresponding to 2 m 2 /. Significantly older bits than. the meter is 2 periods, numbered s + j, and the logical 1 level of the oldest of the bits s + j will determine the sub-range of the input signal in each of its periods Ti. Thus, the code converter 5 performs the function of eating the Domer’s value of the frequency sub- / pelvis: bxWn: bYW signal according to the code value, n start and w-bits of the number Ni, as well as its rio s-th digit, also connected to the code converter 5 . Moreover, the most senior category of the meter of the 2nd period has the highest priority. As a result, with any change in the frequency fx, logical 1 will occur only on one (n + 1) -m output of code converter 5. Digital code generator 3 provides division of the digital equivalent of NI by 2t by shifting the NI code to the lower bits per l bits, where | i is the bit number of the code S with logical 1 of the highest priority. Thus, the ratio of the clock frequency of the pulses of the controlled frequency divider 4 is determined by the ratio; NI

lower D - according to whether the frequency fx belongs to one or another subband. At the same time, one of the signals of the frequency divider 1 will pass to the output of the digital switch 6 in accordance with the subband number fx - no to the signal of the code converter 5. The pulse frequency at the inputs of the digital switch 6 is also set according to the two- to-one principle by connecting with the corresponding digital outputs ( and the input) of the frequency divider 1. In this case, the frequency of the output signal of the digital switch 6 is determined by the expression fK foi / y. Thus, the period of the output signal (bus 9) is determined by the expression TBb, x (Ni / y); 1 / fK Ni / fol.

Since Ni Ti f0i / K, we have Thy

T | / K. Therefore, the multiplication coefficient K is const over the entire range of variation of fx. Moreover, the conversion error with the simplicity of the device does not exceed the maximum value sufficient for frequency measurements over the entire range of variation of fx. With the described F9 nk; ionization algorithm, asking for the implementation of all the blocks makes it easier to communicate between all the blocks.

5formula and zobretten,

A frequency multiplier comprising a divider; frequency, period meter, the counting input of which is connected to the clock output of the frequency divider, and a controlled divider

0 frequency, while the counting chord of the frequency divider is the input of the clock signal of the frequency multiplier, the information input of the period meter is the information input of the multiplier

5 frequencies, and the output of the controlled frequency divider by the output of the frequency multiplier, and this is so that, for the sake of simplicity, a code converter is inserted, and between the bit output of the period meter and the counted input of the controlled delhi. - frequency bodies are introduced in series, a digital subband code generator and a digital switch are connected, a bit information input of which

5 is connected to: the bit output of the frequency divider, the information input of the code converter is connected to the bit output of the period meter, the control input is to the output of the digital code driver of the sub-range, and the output is to the information input of the controlled frequency divider.