SU1448410A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to a pulse technique and can be used in radio devices for generating a frequency grid. The purpose of the invention is to provide a uniform grid of synthesized frequencies, which is achieved by introducing 4 switch 7, a splitter 8 frequency with a variable division factor, EIKA AND offset frequency. In addition to this, the device contains a frequency divider 1 with a variable division factor, and a pulse-phase detector 2 low-pass filter 3 that controls the 4th oscillator 4, the mixer 5, and the frequency multiplier 6, 1-Ш1.

Description

rnsh

The invention relates to a pulse technique and can be used in radio devices for generating a frequency grid.

The purpose of the invention is to provide a uniform grid of synthesized frequencies.

In the drawing, an electrical circuit is proposed for the proposed digital frequency synthesizer.

The digital frequency synthesizer contains serially connected first frequency divider 1 with variable frequency.

dividing ratio (dKD), pulse-phase detector (RND) 2, t5 low-pass filter 3 (HF), controlled oscillator 4 and mixer 5 as well as frequency multiplier 6, switch 7, second divider 5 frequencies with variable division factor 20 (DPKD), D-flip-flop 9, the direct and the versatile of which are connected respectively to the first and second control inputs of the switch 7, the first input of which is AKA-4eH to the output of the 25-switch 5 and to the input y of the shock 6 often w, the output of which is connected to the input of the second dKD 8, the code of which is connected to the BtopoMy switchboard input and

7, the output of which is connected to the clock input of the D-trigger, 9, and to the input of the first DKK I, whose output is also connected to the reset input of the B-trigger 9, whose information input is connected to the bus of the logical unit. 35 Wto {№ of inputs of IFD2 and mixer 5 co-fSf-tKBHa with tires 10 and 1, respectively, with the backhopper frequency and frequency of bias. Walk of the refueling generator 4 of the trains with output bus 12. 40

) Your first frequency synthesizer works well. The signal from the JPIKQ I video output is fed to the input of sat | Dus 9 and sets it to the zero state. The B-flip-flop 5, in its turn, switches the switch 7 to the position in which the DCPD 8 nocTjwaeT has one Sh1-pulse to the input DGT and to the clock input Gtrkgger 9c. But at the end of the impulse, the D-flip-flop goes to one state and switches the switch 7 to a position at which a periodic signal arrives at the input of the DP1SH I and the clock input of the D-flip-flop 9 with W} 1 of the mixer 5. In this way, during one period of the DCPD 1 emitting frequency, one pulse from the DCPD output arrives at its input.

8, separated from the previous one by

magnitude and (N - 1) impulse with

Trch period, where T h - the period of the signal at the output of the mixer 5; n is the multiplication factor multiplier 6; K - installation code DPKD 8; S is the DAKD installation code 1. Then the period of the DPKD 1 output signal is equal to

 dpkA- T „, (“ - 1) + T ,, (N +

P

flnKA IF

Learn that

   d „nt T-GT

PKA number 01

we get

KP

f "ak f APKA (M +" (,,,

where f is the oscillator output frequency 1}

fo, is the frequency of the bias on the bus. And since in the steady-state mode the FSH ring

41 "4D fc"

where f-rt is the reference frequency on bus 10.

- ““ n (+

K p p

) t

01

The sequence of the shushul shushulov 1 st | yu shuhls is uniform, therefore, the secondary ones were higher than the fractionality of the p nemat coefficient in the output signal of the device.

The grid pitch of the digital frequency synthesizer is equal to -) / If necessary, obtaining an output frequency multiple of the reference frequency f of the digital frequency synthesizer, the setup code K of the DPCD 8 takes the same multiplication factor n of the multiplier 6.

At the same time, the device’s 1 frequency is equal to

btsh

a f

N + f

01

3144841

If it is necessary to obtain an output frequency, not a multiple of the reference frequency, the K code arriving at the inputs of the DOCD 8 installation, takes values that are not multiples of the multiplication factor n of the multiplier 6. At the same time, at K n, the device grid spacing is negative, and at K 7 n positive. When К О, the output frequency of the device is equal to.

-out

f, n (N - 1) + f

01 "

The number of synthesized frequencies with 4V "xsirovannon the value of N and the value of O K p is equal to (n + 1). Since the input of the multiplier frequency is equal to

pch

-Vn

Ot

That multiplier 6 can operate at sufficiently large n, limited only by the speed of the DPCD 8 and the single-stage reorganization of the output charts of the digital frequency synthesizer.

Claims (1)

Invention Formula A digital frequency synthesizer containing serially connected first frequency divider with variable coefficients about five 0 25 zo 0- the fission factor, a pulse phase detector, the second input of which is connected to the reference frequency bus, a low-pass filter, a controlled oscillator, the output of which is connected to the output bus and a mixer, and a frequency multiplier, characterized in that in order to provide a uniform grid of synthesized frequencies , a, a switch, a second frequency divider with a variable division factor, an offset frequency bus and a B-trigger, the direct and inverse outputs of which are connected to the first and second control inputs of the comm The device, the first signal input of which is connected to the output of the mixer, is connected to the frequency multiplier, the output of which is connected to the second signal input of the switch, the output of which is connected to the clock input of the D-trigger and to the input the first frequency divider with leremeins is a division factor, the output of which is connected to the reset input of the D-flip-flop and the information input of which is connected to the bus of the unit level, while the second input of the mixer is connected to the wide frequency offset .