RU1784110C - Device for commutation of pulse trains - Google Patents

Abstract

A device for switching pulse sequences relates to pulse technology, in particular, devices for switching pulse sequences, and can be used for switching in digital information transmission systems in order to reduce the error of switching pulse sequences. The device for switching pulse sequences contains switches 25, 26, 27. flip-flops 8, 9 AND-elements 10, 11, 12, elements HE 14, 15 counters 1 2, 3. 4, 5. 6, 7 pulses, input buses 16 , 17, 18, 19 pulse sequences, output buses 22, 23, 24. bus 20 clock pulses, bus 21 control, element And 13. 2 ill.

Description

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The invention relates to pulse technology, in particular to devices for switching pulse sequences, and may find application for switching in digital information transmission systems.

An object of the invention is to reduce pulse switching error.

In FIG. 1 is a functional diagram of a device for switching pulse sequences: FIG. 2 is a timing diagram describing its operation. The device for switching pulse sequences contains the first, second, third, fourth, fifth, sixth and seventh counters 1, 2, 3, 4, 5, 6 and 7, triggers 8 and 9, the first , second, third elements AND-NOT 10, 11, 12, element AND 13, first, second elements NOT 14.15, first, second, third and fourth input buses 16, T7, 18 and 19, input bus 20 clock pulses, control input bus 21 and the first, second and third output buses 22, 23 and 24. The outputs of the first, second and third bits of the first counter 1 are connected respectively to the first, second, and third address inputs of the first, second, and third switches 25, 26, and 27, the outputs of which are connected respectively to the first inputs of the first, second, and third elements of NAND 10, 11, and 12, respectively. The first, second, and third elements AND-NOT 10, 11 and 12 are connected respectively to the first, second and third output buses 22, 23 and 24 and are connected by the second inputs to the output of the And 13 element, the first input of which is connected to the output of the third bit of the second counter 2 and connected by the second trigger output 8, which is connected n the first input to the output of the fourth bit of the third counter 3 and is connected to the second input with the fourth bit of the second counter 2 connected to the synchronization input of the second trigger 9 and to the synchronization input of the fourth counter 4. The fourth counter 4 is connected to the output of the fourth bit with the input the resolution of the second counter 2 and is connected by the permission input to the fourth-digit output of the fifth counter 5, connected to the zero setting input of the second trigger 9 and to the resolution input of the sixth counter bis the seventh resolution input counter 7. The synchronization input of the seventh counter 7 is connected to its fourth output, connected to the synchronization input of the first counter 1. The first counter 1 is connected to the zero setting input with the direct output of the second trigger 9 and connected to the fourth address by the fourth output - to the first inputs of the first and second switches 25 and 26 and to the input of the element NOT

14, Element NOT 14 is connected by the output to the fourth address input of the third switch 27 connected to the first, second, third and fourth information inputs, respectively, to the first, second,

0 third and fourth input buses 16, 17, 18 and 19 of pulse sequences connected respectively to the first, second, third and fourth information inputs of the first switch 25 and

5 connected respectively to the fifth, sixth, seventh and eighth information inputs of the second switch 26. In this case, the enable input of the fifth counter 5 is connected to the input bus 20 clock

0 pulses.

The control input bus 21 is connected to the zero setting inputs of the sixth and seventh counters 6 and 7 and to the zero setting input of the third counter 3 connected

5 by the output of the fourth bit to the synchronization input of the sixth counter 6. In this case, the sixth counter 6 is connected by the fourth bit output to the enable input of the third counter 3, and the element 15 is connected by the output to the zero setting inputs of the second and fourth counters 2 and 4 and connected by the input to the control input bus 21.

The first, second, third and fourth information inputs of the second switch

5 26, fifth, sixth, seventh and eighth information inputs of the first and third switches 25 and 27, the enable input of the first counter 1 and the information input of the second trigger 9 are connected to bus 28

0 level of a logical unit, Zero setting input and synchronization input of the fifth counter 5, synchronization inputs of the second 2 and third 3 counters, unit setting input of the second trigger 9 and power inputs of the first, second and third switches 25, 26 and 27 are connected to the common bus 29 (logical level zero bus).

The operation of the device for switching pulse sequences occurs

0 as follows. Timing diagrams (see Fig. 2) characterize the signals on the input control bus 21 (see Fig. 2a), at the output of the element HE 15 (see Fig. 26), at the output of the third bit of the second counter 2

5 (see Fig. 2c), at the output of the fourth bit of the second counter 2 (see Fig. 2d), at the output of the fourth bit of the third counter 3 (see Fig. 2e), at the output of the And 13 element (see Fig. 2e) and at the direct output of trigger 9 (see Fig. 2g).

The device is intended for converting a decimal code of a telephone network subscriber number to a binary digital code. A pulse train is received from the input bus 20 clock pulses, which is extracted from the digital stream entering the digital telephone network from the digital switching station. The control bus 21 receives pulses generated in the payphone by a disk dialer when dialing the number of the called subscriber. The first, second, third, and fourth input buses 16, 17, 18, 19 receive pulse sequences that have the same repetition period, but differ either in pulse duration or in phase. By a signal on the OUTBOARD control bus 21, the signal of one of the input buses 16. 17, 18, 19 of the pulse sequences is supplied to one of the output buses 22, 23 and 24.

Bursts of pulses are received through the control input bus 21, in which the number of pulses corresponds to one of the digits of the called subscriber’s number. In this case, the duration of each pulse is 50 ms, and the pulse repetition period in the group of pulses (in the presence of two or more pulses in the packet) is 100 ms. From the control input bus 21, pulses are fed to the inputs of the zero setting of the third, sixth and seventh C meters 3 b and 7 and to the input of the element HE 15 from the output of which, after inversion (see Fig. 2a), they are fed to the inputs of the zero setting of the second and fourth counters 2 and 4. In this case, the seventh counter 7 eliminates the bounce at the boundaries of the pulses arriving at it from the input control bus 21. When a logical zero is set on the control input bus 21, the input for setting the zero of the seventh counter 7 is released. To the input of the resolution of which is fed a pulse train from the fourth bit of the fifth counter 5, which divides the sequence of clock pulses eight times input bus 20 clock pulses. A pulse appears at the output of the fourth bit of the seventh counter 7, which stops the seventh counter and resets the first counter 1. At the output of the first, second, third, and fourth bits of the first counter 1, a binary code is set corresponding to the number of pulses in the pulse train at the input bus 21 control. The code r of the outputs of the first, second, third bits of the first counter 1 is supplied to the first second, third inputs of the first second and third switches 25, 26 and 27; the code from the fourth bit of the counter 1 is applied to the fourth inputs of the first and second switches 25 and 26 directly. and to the fourth input 5 of the third switch 27 through the element NOT 14, depending on the state of the first, second, third and fourth address inputs of the first, second and third switches 25, 26 and 27, one of the pulse trains contains one of the pulse sequences , P 16, 17, 18, 19 pulse trains flowing along the first, second, third, and fourth input buses

5 After the appearance of the level of a logical unit on the input control bus 21, the sixth element HE 15 forms a logic zero level (see Fig. 26), which releases the inputs of the zero setting of the second and fourth counters 2 and 4, and after counting the output of the fourth digit of the second counter 2, there is a difference that flips the trigger 9, which resets the first counter 1 The signal from the output of the fourth time5 of the second counter 2 (Fig. 2c) is supplied to the input of the installation of the trigger unit 8, the signal from the direct output of which affects the second input element and I13, to the first input of which a signal is passed that is neither from the output of the third bit of the second counter 2 (see Fig. 2d) The signal from the output of the element And 13 (see Fig. 2e) is fed to the second inputs of the first, second, and third elements NOT 10, 11 and 12. Moreover, on

5, the first, second or third output bus 22 23 and 24 passes one of the sequences of pulses arriving on the first, BTOPQH. third and fourth input buses 16 17. 18 and 19 sequences of pulses 0 sov. Permission for the passage of impulse sequences is provided by the second and fourth counters 2 and 4 through trigger 8, element And 13. The third and sixth counters 3 and b prohibit the passage of 5 pulse sequences to the first, second or third output buses 22, 23 and 24, if on the input bus 21 control there is a level of logical zero for a time exceeding the specified

0 time interval.

Claims (1)

SUMMARY OF THE INVENTION A device for switching pulse sequences, comprising 5 a first pulse counter connected to the outputs of the first, second, third and fourth bits, respectively, to the first, second, third and fourth address inputs of the first relay connected by information inputs to corresponding input pulses of pulse sequences, second, third, fourth, fifth, sixth, seventh pulse counters, first and second elements NOT, first, second, third elements NAND, element And, second and third switches, control bus, clock bus pulses, three output buses, distinguishing with that. that, in order to reduce the switching error of pulse sequences when decimal code is converted to binary code, the first and second triggers are introduced into it, while the output of the first trigger is connected to the zero input of the first counter connected by the outputs of the first, second and third bits with the corresponding address inputs of the second and third switches, and the fourth bit output with the fourth address input of the second switch and through the first power supply NOT with the fourth bit input of the third switch, sub a single first, second, third and fourth information inputs respectively to the first, second, third and fourth input buses and respectively to the fifth, sixth, seventh and eighth information input of the second switch, the output of the second trigger is connected to the first input of the element I. the second input of which connected to the output of the third bit of the second pulse counter, and the output to the first inputs of the first, second, third Y-NOT elements that are connected ILJTTUr are divided by the second inputs to the outputs of the first, second, and third switches, respectively, and the outputs are respectively of the first, second, and third output buses, the clock bus is connected to the resolution input of the fifth counter, connected by the fourth-digit output to the fourth, sixth, and seventh resolution inputs pulse counters, the fourth-digit output of the seventh pulse counter is connected to the synchronization input of the first pulse counter and to its synchronization input, and the installation input zero is connected to the control bus and connected to the inputs of the zero setting of the sixth and third pulse counters, and through the second element NOT to the inputs of the zero setting of the second and fourth pulse counter connected to the fourth bit output to the resolution input of the second pulse counter, the fourth bit output of which is connected with the synchronization input of the fourth pulse counter, the first trigger connected to the zero input to the output of the fourth bit of the fifth pulse counter, and the synchronization input to the fourth bit output of the second count the pulse counter and the unit setup input of the second trigger, the zero setting input of which is connected to the fourth bit output of the third pulse counter connected by the fourth bit output to the resolution input of the sixth pulse counter. L