RU1780035C - Apparatus for measuring active and reactive power - Google Patents

Abstract

Usage: the construction of measuring transducers of active and reactive power. The inventive device contains a calibrated resistor 1, two ADCs 2 and 3, a multiplier 4. two adders 5 and 6, a zero-organ 7, a generator 8 of the reference frequency, two counters 9 and 10, a delay element 11, register 12, block 13 code comparisons, two triggers 14 and 15. 1-3-4-5: 7-11-9-12-13-14-10-6; 8-9-13: 11-14-4; 14-3; 14-2: 11-15-6: 14-4-6: 2-4.2 ill. M > & '00 s • h looо8СЛ

Description

The invention relates to electrical engineering and can be used in automation and energy, for example, for the implementation of measuring transducers of active and reactive power. A device is known for measuring active reactive power, comprising discrete voltage and current converters, input signal sampling units, memory cells, combiners, accumulators and multipliers 1. A disadvantage of the known device is its complexity and low accuracy. The closest technical solution to the invention is a device for measuring active and reactive power, comprising a calibrated resistor, an analog-to-digital converter, a switch, a register, a multiplier, accumulating adders and a control unit containing a zero-organ, a reference frequency generator, a counter, a delay element , register, code comparison scheme, and triggers 2. The disadvantage of the prototype is the low accuracy of reactive power conversion. Indeed, for the sinusoidal input signals U (t) UmSin (Di, i (t) ImSin (() {+ for a constant NUMBER n of their discretizations for the period (), the readings of the active and reactive power are respectively equal; P2 knImUmCoS (f). Q2 k w ImUmSin p where k is the proportionality coefficient. In other words, the maximum reading P2 (at Cos p exceeds the maximum reading Q2 (at Sin at 1) is half-time, where. The aim of the invention is to improve the accuracy of measurement. that in a device for measuring active and reactive power, containing a calibrated first analog-to-digital converter, multiplier, first and second accumulating adders, zero-organ, reference frequency generator, first counter, delay element, register, code comparison unit, first and second triggers, and the input of the zero-organ connected to the input bus voltage, synchronization input - to the output of the reference frequency generator, also connected to the input of the first counter, and the output to the input of the register record and through the delay element to the zero inputs of the first counter, the first and second triggers, ml outputs The upper bits of the first counter are connected to the first inputs of the code comparison unit, the high-order outputs are connected via a register to the second inputs of the code comparison block, the output of which is connected to the counting input of the first trigger, the direct output of which is connected to the clock input of the first analog-to-digital converter and recording inputs of the first and second accumulating adders, and the inverse - with the installation input to the unit of the second trigger, whose direct output is connected to the zero inputs of the first and second accumulating adders The outputs of the first analog-to-digital converter are connected to the first inputs of the multiplier, the outputs of which are connected to the inputs of the first and second accumulative adders, the outputs of which are the outputs of the device, a second counter and a second analog-to-digital converter are additionally introduced. the input of which is connected to the second output of the calibrated resistor and to the current input bus, the clock input to the clock output of the first analog-to-digital converter, and the outputs to the second input of the m multiplier, the recording input of which is connected to the inverse output of the first trigger, the input of the second counter is connected with the inverse output of the first trigger, the zero input - with the direct output of the second trigger, and the high-order output - with the input of the choice of the operating mode of the second accumulating adder, in addition, the input of the first analog-to-digital the inverter is connected to the input voltage bus. The new device elements revealed in comparison with the prototype are known from various sources of information. So, in the particular case of implementation, the second analog-to-digital converter is made according to the K1107PVZ ADC circuit (see Basin V.M., Kuchinskas I.D., Marcink vich.yus A.-I, K, Ultrafast six-bit ADCs K1107PVZA, B .-, Electron and industry. 1985, rh 7, p. 33, Fig. 3) with connected sources of / - reference voltage. The significance of the differences of the solution lies in the fact. that the introduction of a second analog-to-digital converter and a second counter provided an increase in the accuracy of reactive power measurements by a factor of раз., where η is the number of input signal discretizations for the period, and n. 3.14. Solutions with a similar combination of 1-: the known elements are not o5 -iapy.iceHO. therefore, the claimed solution has novelty and significant differences.

Fig. 1 is a diagram of an apparatus for measuring active and reactive power; Fig. 2 is a timing chart illustrating its operation.

The device (figure 1) contains a calibrated resistor 1, analog-to-digital converters 2 and 3. multiplier 4. accumulating adders 5 and 6, zero-organ 7, generator 8 of the reference frequency, counters 9 and 10, element 11 delay, register 12. code comparison unit 13, triggers 14 and 15. The input of the analog-to-digital converter 2 is connected to the input voltage bus, the input of the analog-to-digital converter 3 through a calibrated resistor to the current input bus. The clock inputs of analog-to-digital converters 2 and 3 are connected to the direct output of the trigger 14, also connected to the recording inputs of the accumulating adders 5 and 6, and the outputs, respectively, to the first and second inputs of the multiplier 4. The recording input of the multiplier 4 is connected to the inverse output of the trigger 14, and the outputs - with the inputs of the accumulating adders 5 and 6. The outputs of these adders are the outputs of the device, and the outputs of the zero setting are connected to the direct output of the trigger 15. The output of the high-order bit of the counter 10 is connected to the input of the selection of the accumulation mode the adder 6. The input of the zero-organ 7 is connected to the input voltage bus, the synchronization input to the output of the reference frequency generator 8, also connected to the input of the counter 9, and the output to the input of the register 12 and through the delay element 11 to the inputs zeroing counter 9 and trigger 14 and 15. The low-order outputs of counter 9 are connected to the first inputs of the code comparison unit 13, the high-order outputs, through register 12, are connected to the second inputs of the code comparison block 13, the output of which is connected to the counting input of the trigger 14. Inverse trigger output and 14 is connected to the setting input of a flip-flop unit 15 and the input of counter 10, output flip-flop 15 is connected to the set input of the counter 10 to zero.

In a particular device implemented, analog-to-digital converter 2 is similar to analog-to-digital converter 1. Multiplier 4 is built on the basis of the 1В02ВРЗ chip (bKO.347.253TU7), which is included in the transparency mode of the input registers and enables the output of information (see Microprocessors and microprocessor sets of integrated circuits: Handbook / Under the editorship of V.A. Shakhnov. - M .: Radio and communications. 1988, v. 2, p. 71, fig. 12.17).

. The accumulating adders 5 and 6 are built on the basis of a combinational adder (see Alekseenko A, G., Shagurina I.I., Microcircuitry, - M .: Radio and communications, 1982, p. 124, Fig. 3.12.b), the outputs of which connected to the inputs of an additional register, the recording input of which is an input

0 records accumulating adder, and the outputs of the outputs of the latter and connected to the second inputs of the combinational adder. The accumulating adder 5 is included in the addition mode,

5 As a zero-organ 7 used

Schmitt trigger with an output connected to the C-input of the D-flip-flop, the D-input of which is connected to the power bus, and the direct output and R-input, respectively, with the D-input and inverse output of the second D-flip-flop, C- and R- the inputs of which are connected to the synchronization input of a null organ, and the direct output is the output of a null organ.

The code comparison circuit 13 is built on

5 based on the K555SP1 microcircuit (6KO, 348.289 TUZ) (see. Application of integrated circuits in electronic computing. Reference: Edited by B.N. Fayzulaev, B.V. Tarabrina. - M.: Radio and communications, 1987 ,

0 s 355, Fig, A2.71).

Measurement of active and reactive power in the proposed device is carried out for each period of the signals of the controlled electric network, allocated to adjacent voltage transitions U (t) through zero in one direction, at the beginning of the next period Tx (Fig.2.a) by a zero-organ 7, a pulse is generated (Fig. 2, b), synchronized with the pulse of the reference sequence from the output of the reference frequency generator 8, which transfers the code 1/2 of the step DТх of the sampling of input signals from the higher order bits to the register 12 of the register ika 9 and the installation after a delay time as determined by the element 11, the counter 9 and flip-flops 14, 15 to the zero state. During the Tx unit 13 compares LTH / 2 code with the current code

0 low-order bits of counter 9, to the input of which pulses of the reference repetition rate are received from the output of generator 8, When the codes are equal, a pulse is generated that limits the next 1/2 step

Claims (1)

5 discretization of input signals (figure 2, c). The trigger 14 divides the pulse repetition rate from the output of the code comparison unit 13 by 2, thereby highlighting the current sampling steps L Tx of the input signals (Fig. 2d). And the counter 10 divides the pulse repetition rate from the output of the trigger 14 by n / 2, where n is the number uiafOB of sampling the input signals for the period, thereby extracting four quarters ri. Gz. P . r / i period Tx (figure 2, d). During the first half-step of the next Q-ro) sampling step (Fig. 2, d; trigger 14 is at zero), the converters 2 and 3 select and convert into a digital code, respectively, the current value Uj of the input voltage u (t) and the current value ij of the input current i (t) multiplied by the resistance R of the calibrated resistor 1. During the second half-step of the current (j-ro) sampling step (Fig. 2d; trigger 14 in unit), the converters 2 and 3 go into storage mode. In this case, the codes Uj and R-ij from their outputs go to the inputs of the multiplier 4 and are multiplied by them, after which the product code is entered in the register on the positive edge at the inverse output of trigger 14 (negative at the forward output of trigger 14 - Fig. 2, d) multiplier product 4. During the first half-step of the next 0 + 1) -th sampling step (Fig. 2, d), the product code Uj and R-ij is added to the contents of adder 5 and added to the contents of adder 6, if this sampling step belongs to intervals n and gz (figure 2, d), or subtracted from soda compression adder 6, if this sampling step belongs to the intervals G2 and G4 (FIG.2, d). As a result of these operations, for the jth power reference point, the contents of adders 5 and 6 are changed respectively by P kUmSin W tj-lmSin (w ti-y5). Q Riley Q -kUmSin a) tj lmSin (r /.) Tj-th (p). (2) where k is the coefficient of proportionality, and by the end of the period Tx with LTx, х Tx is respectively PI - fl) dt - -cos. -K gTxLo Tx / 2 .11 / Q lt; f ° Q yes + /; ::% o (ol + +), 0 (t) dt; Jm UmSin (f. During the current period Tx of the input signals 8, the counter 9 accumulates the number Txfo of pulses by the reference frequency fo from the output of the generator 8. At the beginning of the next period of the input signals, the contents Txfo / 2n of the high-order bits of the counter 9 are transferred to the register 12 and determines 1/2 of the sampling steps of this period. In addition, at the beginning of the last trigger pulse 15, a control pulse is generated (Fig. 2, f), resetting the adders 5, 6 and counter 10 to zero on its positive edge, thereby preparing them for work in this period. my device for measuring active and reactive power compares favorably with the prototype, because by introducing a second analog-to-digital converter and a second counter it can significantly increase the accuracy of measuring reactive power. Indeed, as can be seen from a comparison of expressions (1) and (3). taking into account the fact that the sampling step in the prototype is two times longer than the sampling step in the proposed device, since the analog-to-digital converter of the prototype must perform two transforms during the sampling step nor, and the proposed device is only one, i.e., n 2p, the accuracy of measuring the active power remains unchanged. As for the measurement of reactive power, then, as can be seen from the comparison of expressions (1) and (3), the accuracy of its measurement by the proposed device increases compared to the accuracy of the prototype in Qi / Q2 n /, 7z times, with n 1000 Qi / Q2 100. An increase in the accuracy of measuring reactive power, in turn, leads to improved regulation of the generated and consumed power, and consequently, to energy savings. SUMMARY OF THE INVENTION A device for measuring active and reactive power, comprising a calibrated resistor, a first analog-to-digital converter, a multiplier, a first and second accumulative adders, a zero-organ, a reference frequency generator, a first counter, a delay element, a code comparison unit, the first and second triggers moreover, the input of the zero-organ is connected to the input voltage bus, the synchronization input is to the output of the reference frequency generator, also connected to the input of the first counter, and the output is to the input of the register record and via delay time - to the installation inputs in О of the first counter, the first and second triggers, the low-order outputs of the first counter are connected to the first inputs of the code comparison unit, the high-order outputs through the register are connected to the second inputs of the code comparison unit, the output of which is connected to the counting input the first trigger, the direct output of which is connected to the clock input of the first analog-to-digital converter and the recording inputs of the first and second accumulative adders, and the inverse - with the setup input 1 of the second trigger, the direct output to connected to the inputs of the installation in O of the first and second accumulating adders, the outputs of the first analog-to-digital converter are connected to the first inputs of the multiplier, the outputs of which are connected to the inputs of the first and second accumulating adders, the outputs of which are outputs of a device in order to increase the measurement accuracy, a second counter and a second analog-to-digital converter are introduced into it, the input of which is connected to the second output of the calibrated resistor and the input bus current, the clock input is to the clock input of the first analog-to-digital converter, and the outputs are to the second inputs of the multiplier, the recording input of which is connected to the inverse output of the first trigger and the input of the second counter, the zero input - with the direct input of the second trigger, and the high-order output - with the input of the choice of the operating mode of the second accumulating adder, in addition, the input of the first analog-to-digital converter is connected to the input voltage bus. lLШLУll.УJUULMMJL. nT; T T n TivrbrLrLrT; ri r ruTJiJn.