RO81821B1 - Process for manufacturing field effect integrated transistor with junction gate - Google Patents

Process for manufacturing field effect integrated transistor with junction gate

Info

Publication number
RO81821B1
RO81821B1 RO109297A RO10929782A RO81821B1 RO 81821 B1 RO81821 B1 RO 81821B1 RO 109297 A RO109297 A RO 109297A RO 10929782 A RO10929782 A RO 10929782A RO 81821 B1 RO81821 B1 RO 81821B1
Authority
RO
Romania
Prior art keywords
field effect
junction gate
manufacturing field
integrated transistor
effect integrated
Prior art date
Application number
RO109297A
Other languages
Romanian (ro)
Other versions
RO81821A2 (en
Inventor
Florin Gaiseanu
Marian Badila
Ion Ghita
Original Assignee
Centrul De Cercetare Stiintifica Si Inginerie Tehnologica Pentru Semiconductoare
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centrul De Cercetare Stiintifica Si Inginerie Tehnologica Pentru Semiconductoare filed Critical Centrul De Cercetare Stiintifica Si Inginerie Tehnologica Pentru Semiconductoare
Priority to RO82109297A priority Critical patent/RO81821A2/en
Publication of RO81821B1 publication Critical patent/RO81821B1/en
Publication of RO81821A2 publication Critical patent/RO81821A2/en

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  • Junction Field-Effect Transistors (AREA)

Abstract

Inventia se refera la un procedeu de fabricatie pentru tranzistoare cu efect de câmp cu poarta jonctiune integrate, integrate cu jonctiune pn. Procedeul, conform inventiei, prevede utilizarea unei implantari ionice sau o difuzie de tip opus tipului de conductie a canalului, urmate de o redistributie termica în cazul utilizarii implantarii si de o corodare izotropa urmata de o redistributie termica în cazul difuziei pentru realizarea de insule dopate cu impuritati cu concentratie maxima de 10 la -16 cm la -3 sub stratul epitaxial.The invention relates to a manufacturing process for field-effect transistors with integrated junction gate integrated with pn junction. The process according to the invention provides for the use of ionic implantation or diffusion of the type of conduction of the channel, followed by a thermal redistribution in the case of implantation use and an isotropic corrosion followed by a thermal redistribution in the case of diffusion for the formation of doped islets with impurities with a maximum concentration of 10 to -16 cm at -3 under the epitaxial layer.

RO82109297A 1982-12-11 1982-12-11 MANUFACTURING PROCEDURE FOR CIMP EFFECT TRANSMITTERS WITH INTEGRATED WARRANTY RO81821A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
RO82109297A RO81821A2 (en) 1982-12-11 1982-12-11 MANUFACTURING PROCEDURE FOR CIMP EFFECT TRANSMITTERS WITH INTEGRATED WARRANTY

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
RO82109297A RO81821A2 (en) 1982-12-11 1982-12-11 MANUFACTURING PROCEDURE FOR CIMP EFFECT TRANSMITTERS WITH INTEGRATED WARRANTY

Publications (2)

Publication Number Publication Date
RO81821B1 true RO81821B1 (en) 1983-07-30
RO81821A2 RO81821A2 (en) 1983-08-03

Family

ID=20112354

Family Applications (1)

Application Number Title Priority Date Filing Date
RO82109297A RO81821A2 (en) 1982-12-11 1982-12-11 MANUFACTURING PROCEDURE FOR CIMP EFFECT TRANSMITTERS WITH INTEGRATED WARRANTY

Country Status (1)

Country Link
RO (1) RO81821A2 (en)

Also Published As

Publication number Publication date
RO81821A2 (en) 1983-08-03

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