PT724228E - Metodo para montagem de um modulo electronico no corpo de um cartao - Google Patents

Metodo para montagem de um modulo electronico no corpo de um cartao

Info

Publication number
PT724228E
PT724228E PT96101004T PT96101004T PT724228E PT 724228 E PT724228 E PT 724228E PT 96101004 T PT96101004 T PT 96101004T PT 96101004 T PT96101004 T PT 96101004T PT 724228 E PT724228 E PT 724228E
Authority
PT
Portugal
Prior art keywords
card
module
mounting
electronic module
recess
Prior art date
Application number
PT96101004T
Other languages
English (en)
Inventor
Thomas Tarantino
Original Assignee
Giesecke & Devrient Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=7752376&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=PT724228(E) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Giesecke & Devrient Gmbh filed Critical Giesecke & Devrient Gmbh
Publication of PT724228E publication Critical patent/PT724228E/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
PT96101004T 1995-01-26 1996-01-24 Metodo para montagem de um modulo electronico no corpo de um cartao PT724228E (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19502398A DE19502398A1 (de) 1995-01-26 1995-01-26 Verfahren zur Montage eines elektronischen Moduls in einem Kartenkörper

Publications (1)

Publication Number Publication Date
PT724228E true PT724228E (pt) 2003-08-29

Family

ID=7752376

Family Applications (1)

Application Number Title Priority Date Filing Date
PT96101004T PT724228E (pt) 1995-01-26 1996-01-24 Metodo para montagem de um modulo electronico no corpo de um cartao

Country Status (9)

Country Link
US (1) US5951810A (pt)
EP (1) EP0724228B2 (pt)
JP (1) JPH08258471A (pt)
AT (1) ATE237168T1 (pt)
DE (2) DE19502398A1 (pt)
DK (1) DK0724228T3 (pt)
ES (1) ES2192210T5 (pt)
PT (1) PT724228E (pt)
ZA (1) ZA96543B (pt)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19637213C1 (de) * 1996-08-22 1998-02-19 Pav Card Gmbh Verfahren und Fügewerkzeug zum Herstellen einer Chipkarte
DE19921230B4 (de) * 1999-05-07 2009-04-02 Giesecke & Devrient Gmbh Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten
FR2794552B1 (fr) * 1999-06-03 2001-08-31 Gemplus Card Int Procede de collage a chaud d'un module electronique dans une carte a puce
DE10110939B4 (de) * 2001-03-07 2004-07-08 Mühlbauer Ag Verfahren und Vorrichtung zum Heißpressverbinden eines Chipmoduls mit einem Trägersubstrat
US20040144472A1 (en) 2003-01-24 2004-07-29 G & D Cardtech, Inc. Process for manufacturing laminated plastic products
US6857552B2 (en) * 2003-04-17 2005-02-22 Intercard Limited Method and apparatus for making smart card solder contacts
DE102004041035B4 (de) * 2004-04-14 2010-04-29 Steinhauser, Jürgen Verfahren zum Befestigen von Bauteilen auf einem Substrat
US20060146271A1 (en) * 2005-01-04 2006-07-06 Pennaz Thomas J Universal display module
US7599192B2 (en) * 2005-04-11 2009-10-06 Aveso, Inc. Layered structure with printed elements
US7821794B2 (en) * 2005-04-11 2010-10-26 Aveso, Inc. Layered label structure with timer
DE102018112476B4 (de) 2017-06-02 2022-01-27 Ulrich Lang Verfahren und Fertigungsanlage zum Herstellen eines Foliensubstrats
WO2019224364A1 (de) 2018-05-24 2019-11-28 Ulrich Lang Verfahren und fertigungsanlage zum herstellen eines foliensubstrats

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3166462A (en) * 1961-11-01 1965-01-19 Fr Hesser Maschinenfabrik Ag F Method and apparatus for heat sealing packages
US3600248A (en) * 1966-07-13 1971-08-17 Mojonnier Inc Albert Method for heat sealing thermoplastic bodies
US3692608A (en) * 1971-01-20 1972-09-19 Nasco Ind Inc Sealing means and method
US3951713A (en) * 1973-12-19 1976-04-20 Fortin Laminating Corporation Method and apparatus for insulating electrically conductive elements
DE3029939A1 (de) * 1980-08-07 1982-03-25 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit ic-baustein und verfahren zu ihrer herstellung
DE3466108D1 (en) * 1983-06-09 1987-10-15 Flonic Sa Method of producing memory cards, and cards obtained thereby
US4543147A (en) * 1984-08-20 1985-09-24 Tetrahedron Associates, Inc. Laminating process and apparatus
FR2579799B1 (fr) * 1985-03-28 1990-06-22 Flonic Sa Procede de fabrication de cartes a memoire electronique et cartes obtenues suivant ledit procede
DE3639630A1 (de) * 1986-11-20 1988-06-01 Gao Ges Automation Org Datentraeger mit integriertem schaltkreis und verfahren zur herstellung desselben
JPS6433749A (en) * 1987-07-30 1989-02-03 Toshiba Corp Manufacture for tracking channel of optical recording card
FR2629236B1 (fr) * 1988-03-22 1991-09-27 Schlumberger Ind Sa Procede de realisation d'une carte a memoire electronique et carte telle qu'obtenue par la mise en oeuvre dudit procede
CA2025295C (en) * 1989-09-16 1993-11-02 Ryoichi Yamamoto Magnetic card manufacturing arrangement
JP2687661B2 (ja) * 1990-03-26 1997-12-08 三菱電機株式会社 Ｉｃカードの製造方法
DE4040770C2 (de) * 1990-12-19 1999-11-11 Gao Ges Automation Org Datenträger mit integriertem Schaltkreis
FR2701139B1 (fr) * 1993-02-01 1995-04-21 Solaic Sa Procédé pour l'implantation d'un micro-circuit sur un corps de carte intelligente et/ou à mémoire, et carte comportant un micro-circuit ainsi implanté.
FR2703806B1 (fr) * 1993-04-06 1995-07-13 Leroux Gilles Sa Objet portatif et procede de fabrication.

Also Published As

Publication number Publication date
ES2192210T3 (es) 2003-10-01
EP0724228A3 (de) 1998-01-07
DE59610318D1 (de) 2003-05-15
DE19502398A1 (de) 1996-08-01
JPH08258471A (ja) 1996-10-08
ES2192210T5 (es) 2006-07-16
EP0724228A2 (de) 1996-07-31
ZA96543B (en) 1996-08-15
ATE237168T1 (de) 2003-04-15
EP0724228B1 (de) 2003-04-09
DK0724228T3 (da) 2003-09-01
EP0724228B2 (de) 2006-04-05
US5951810A (en) 1999-09-14

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