PL398149A1 - Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT - Google Patents

Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT

Info

Publication number
PL398149A1
PL398149A1 PL398149A PL39814912A PL398149A1 PL 398149 A1 PL398149 A1 PL 398149A1 PL 398149 A PL398149 A PL 398149A PL 39814912 A PL39814912 A PL 39814912A PL 398149 A1 PL398149 A1 PL 398149A1
Authority
PL
Poland
Prior art keywords
heterostructure
thickness
layer
hemt
manufacture
Prior art date
Application number
PL398149A
Other languages
English (en)
Inventor
Piotr Caban
Włodzimierz Strupiński
Original Assignee
Isos Technologies Sarl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Isos Technologies Sarl filed Critical Isos Technologies Sarl
Priority to PL398149A priority Critical patent/PL398149A1/pl
Priority to PCT/EP2013/053067 priority patent/WO2013120990A1/en
Publication of PL398149A1 publication Critical patent/PL398149A1/pl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432—Heterojunction gate for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Przedmiotem wynalazku jest heterostruktura tranzystora HEMT, obejmujaca podloze i warstwe buforowa, charakteryzuje sie tym, ze obejmuje kolejno nastepujace warstwy: (1) warstwa pasywujaca/podkontaktowa GaN o grubosci 3 nm, (2) warstwa bariery c): AlxGa1-xN 0.15 < x < 0.5, grubosc 3-5 nm, (3) warstwa bariery b): InxAl1-xN 0.05 < x < 0.3, grubosc 2-15 nm, (4) warstwa bariery a): AlxGa1-xN 0.15 <x < 0.4, grubosc 3-15 nm, (5) korzystnie warstwa AIN, grubosc 0-2 nm, (6) warstwa GaN, grubosc 1000-3000 nm, (7) warstwa buforowa, (8) podloze, korzystnie z SiC, Al2O3, Si lub 3C-SiC. Wynalazek obejmuje takze sposób wytwarzania takiej heterostruktury tranzystora HEMT przez epitaksje na podlozu.
PL398149A 2012-02-17 2012-02-17 Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT PL398149A1 (pl)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PL398149A PL398149A1 (pl) 2012-02-17 2012-02-17 Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT
PCT/EP2013/053067 WO2013120990A1 (en) 2012-02-17 2013-02-15 Hemt heterostructure and a method of hemt manufacturing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL398149A PL398149A1 (pl) 2012-02-17 2012-02-17 Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT

Publications (1)

Publication Number Publication Date
PL398149A1 true PL398149A1 (pl) 2013-08-19

Family

ID=47901946

Family Applications (1)

Application Number Title Priority Date Filing Date
PL398149A PL398149A1 (pl) 2012-02-17 2012-02-17 Heterostruktura tranzystora HEMT i sposób wytwarzania heterostruktury tranzystora HEMT

Country Status (2)

Country Link
PL (1) PL398149A1 (pl)
WO (1) WO2013120990A1 (pl)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018196948A1 (en) * 2017-04-24 2018-11-01 Swegan Ab Interlayer barrier

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5135686B2 (ja) * 2005-03-23 2013-02-06 住友電気工業株式会社 Ｉｉｉ族窒化物半導体素子
US20080067549A1 (en) * 2006-06-26 2008-03-20 Armin Dadgar Semiconductor component
WO2009066434A1 (ja) * 2007-11-19 2009-05-28 Nec Corporation 電界効果トランジスタおよびその製造方法

Also Published As

Publication number Publication date
WO2013120990A1 (en) 2013-08-22

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