PL3092575T3 - Sposoby i aparat do ustawiania adresu modułu przy użyciu zegara - Google Patents

Sposoby i aparat do ustawiania adresu modułu przy użyciu zegara

Info

Publication number
PL3092575T3
PL3092575T3 PL15788281T PL15788281T PL3092575T3 PL 3092575 T3 PL3092575 T3 PL 3092575T3 PL 15788281 T PL15788281 T PL 15788281T PL 15788281 T PL15788281 T PL 15788281T PL 3092575 T3 PL3092575 T3 PL 3092575T3
Authority
PL
Poland
Prior art keywords
clock
address
module
setting
methods
Prior art date
Application number
PL15788281T
Other languages
English (en)
Inventor
James Ronald Booth
Adam J. Ahne
Original Assignee
Lexmark International, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/517,394 external-priority patent/US9223741B1/en
Application filed by Lexmark International, Inc. filed Critical Lexmark International, Inc.
Publication of PL3092575T3 publication Critical patent/PL3092575T3/pl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
PL15788281T 2014-10-17 2015-10-16 Sposoby i aparat do ustawiania adresu modułu przy użyciu zegara PL3092575T3 (pl)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US14/517,394 US9223741B1 (en) 2014-10-17 2014-10-17 Systems for setting the address of a module
US14/703,376 US9213396B1 (en) 2014-10-17 2015-05-04 Methods and apparatus for setting the address of a module using a clock
EP15788281.2A EP3092575B1 (en) 2014-10-17 2015-10-16 Methods and apparatus for setting the address of a module using a clock
PCT/US2015/055979 WO2016061480A2 (en) 2014-10-17 2015-10-16 Methods and apparatus for setting the address of a module using a clock

Publications (1)

Publication Number Publication Date
PL3092575T3 true PL3092575T3 (pl) 2020-12-28

Family

ID=55747559

Family Applications (1)

Application Number Title Priority Date Filing Date
PL15788281T PL3092575T3 (pl) 2014-10-17 2015-10-16 Sposoby i aparat do ustawiania adresu modułu przy użyciu zegara

Country Status (7)

Country Link
US (1) US9213396B1 (pl)
EP (1) EP3092575B1 (pl)
CN (1) CN106104508B (pl)
AU (1) AU2015331864A1 (pl)
CA (1) CA2938892A1 (pl)
PL (1) PL3092575T3 (pl)
WO (1) WO2016061480A2 (pl)

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US9970986B2 (en) * 2014-03-11 2018-05-15 Cryptography Research, Inc. Integrated circuit authentication
US10067895B2 (en) * 2015-06-03 2018-09-04 Lexmark International, Inc. Systems and methods for asynchronous toggling of I2C data line
US9805257B1 (en) * 2016-09-07 2017-10-31 Datamax-O'neil Corporation Printer method and apparatus
CN108243622B (zh) * 2016-10-27 2021-01-22 惠普发展公司，有限责任合伙企业 可替换物件认证
CN106657908B (zh) * 2016-12-16 2019-07-16 浙江大华技术股份有限公司 一种数字总线异常的视频信号处理方法及装置
CN113168457A (zh) * 2018-12-03 2021-07-23 惠普发展公司，有限责任合伙企业 逻辑电路系统封装
US10894423B2 (en) * 2018-12-03 2021-01-19 Hewlett-Packard Development Company, L.P. Logic circuitry
WO2020113389A1 (en) * 2018-12-03 2020-06-11 Astec International Limited Switched mode power supplies with configurable communication addresses
KR20210087978A (ko) 2018-12-03 2021-07-13 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 로직 회로
MX2021005993A (es) 2018-12-03 2021-07-06 Hewlett Packard Development Co Conjunto de circuitos logicos.
BR112021010044A2 (pt) 2018-12-03 2021-08-17 Hewlett-Packard Development Company, L.P. circuitos lógicos
WO2021080606A1 (en) * 2019-10-25 2021-04-29 Hewlett-Packard Development Company, L.P. Logic circuitry package
BR112021010658A2 (pt) 2018-12-03 2021-08-24 Hewlett-Packard Development Company, L.P. Circuitos lógicos
CN113165390A (zh) 2018-12-03 2021-07-23 惠普发展公司，有限责任合伙企业 逻辑电路系统封装
KR20210087502A (ko) * 2018-12-03 2021-07-12 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 로직 회로
WO2020117195A1 (en) 2018-12-03 2020-06-11 Hewlett-Packard Development Company, L.P. Logic circuitry
JP7200370B2 (ja) 2018-12-03 2023-01-06 ヒューレット－パッカード デベロップメント カンパニー エル．ピー． 論理回路
WO2020117392A1 (en) * 2018-12-03 2020-06-11 Hewlett-Packard Development Company, L.P. Logic circuitry package
US11338586B2 (en) 2018-12-03 2022-05-24 Hewlett-Packard Development Company, L.P. Logic circuitry
CN110297792B (zh) * 2019-08-02 2024-05-17 富满微电子集团股份有限公司 数据高电平宽度稳定转发芯片及级联方法
US11409487B2 (en) 2019-10-25 2022-08-09 Hewlett-Packard Development Company, L.P. Power management in a logic circuitry package
WO2021080604A1 (en) * 2019-10-25 2021-04-29 Hewlett-Packard Development Company, L.P. Logic circuitry package
US11407229B2 (en) 2019-10-25 2022-08-09 Hewlett-Packard Development Company, L.P. Logic circuitry package
US12406077B2 (en) 2020-04-30 2025-09-02 Hewlett-Packard Development Company, L.P. Logic circuitry package for print apparatus
US11977506B2 (en) 2020-12-11 2024-05-07 Skyworks Solutions, Inc. Enumeration of peripheral devices on a serial communication bus

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DE58908747D1 (de) 1988-07-27 1995-01-19 Peter Vockenhuber Adressieranordnung.
US5210846B1 (en) 1989-05-15 1999-06-29 Dallas Semiconductor One-wire bus architecture
US5270972A (en) 1992-04-14 1993-12-14 Xicor, Inc. Three terminal serial-communicating peripheral device
US5831546A (en) 1996-05-10 1998-11-03 General Signal Corporation Automatic addressing in life safety system
US6255973B1 (en) 1999-08-26 2001-07-03 Analog Devices, Inc. Address selection circuitry and method using single analog input line
TWI255404B (en) * 2004-12-03 2006-05-21 Hon Hai Prec Ind Co Ltd System and method for dynamically allocating addresses to devices connected to an integrated circuit bus
TWI268423B (en) * 2004-12-03 2006-12-11 Hon Hai Prec Ind Co Ltd System and method for configuring I2C address dynamically
FR2885710B1 (fr) 2005-05-11 2007-08-03 Stmicroelectronics Maroc Selection d'adresse pour bus i2c
US8521970B2 (en) * 2006-04-19 2013-08-27 Lexmark International, Inc. Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts
US20060291406A1 (en) * 2005-06-23 2006-12-28 Lexmark International, Inc. Device authentication method and system
US20070079125A1 (en) * 2005-09-27 2007-04-05 Lexmark International, Inc. Interface protocol method and system
JP3128349U (ja) * 2006-10-23 2007-01-11 船井電機株式会社 テレビジョン受信機
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US7536492B2 (en) * 2007-01-23 2009-05-19 International Business Machines Corporation Apparatus, system, and method for automatically resetting an inter-integrated circuit bus
US7827330B2 (en) * 2007-07-27 2010-11-02 Microchip Technology Incorporated Configuring multi-bit slave addressing on a serial bus using a single external connection
ES2635339T3 (es) 2008-05-21 2017-10-03 Hewlett-Packard Development Company, L.P. Bus serie de múltiples salidas con detección de ubicación y procedimiento
JP2010212989A (ja) * 2009-03-10 2010-09-24 Freescale Semiconductor Inc アドレスデコーダ及びアドレス設定方法
CN102200953A (zh) * 2010-03-24 2011-09-28 鸿富锦精密工业（深圳）有限公司 电子系统
US9477634B2 (en) * 2010-06-04 2016-10-25 Intersil Americas LLC I2C address translation
US8667204B2 (en) * 2011-01-24 2014-03-04 Rpx Corporation Method to differentiate identical devices on a two-wire interface
JP5928107B2 (ja) * 2012-04-06 2016-06-01 セイコーエプソン株式会社 センサーシステム、センサーモジュール

Also Published As

Publication number Publication date
US9213396B1 (en) 2015-12-15
CN106104508A (zh) 2016-11-09
AU2015331864A1 (en) 2016-08-25
WO2016061480A2 (en) 2016-04-21
CN106104508B (zh) 2019-07-09
EP3092575B1 (en) 2020-06-17
EP3092575A2 (en) 2016-11-16
CA2938892A1 (en) 2016-04-21
WO2016061480A3 (en) 2016-06-09

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