PH30201A - Tightly coupled multi-processor instruction synchronization - Google Patents
Tightly coupled multi-processor instruction synchronizationInfo
- Publication number
- PH30201A PH30201A PH39687A PH39687A PH30201A PH 30201 A PH30201 A PH 30201A PH 39687 A PH39687 A PH 39687A PH 39687 A PH39687 A PH 39687A PH 30201 A PH30201 A PH 30201A
- Authority
- PH
- Philippines
- Prior art keywords
- tightly coupled
- processor instruction
- coupled multi
- instruction synchronization
- synchronization
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/297,783 US5075840A (en) | 1989-01-13 | 1989-01-13 | Tightly coupled multiprocessor instruction synchronization |
Publications (1)
Publication Number | Publication Date |
---|---|
PH30201A true PH30201A (en) | 1997-02-05 |
Family
ID=23147726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PH39687A PH30201A (en) | 1989-01-13 | 1989-12-13 | Tightly coupled multi-processor instruction synchronization |
Country Status (13)
Country | Link |
---|---|
US (1) | US5075840A (zh) |
EP (1) | EP0377991B1 (zh) |
JP (1) | JP2645669B2 (zh) |
KR (1) | KR930004214B1 (zh) |
CN (1) | CN1013067B (zh) |
AU (1) | AU618142B2 (zh) |
BR (1) | BR9000112A (zh) |
CA (1) | CA1321655C (zh) |
DE (1) | DE68927911T2 (zh) |
GB (1) | GB2227108A (zh) |
HK (1) | HK1000050A1 (zh) |
MY (1) | MY105754A (zh) |
PH (1) | PH30201A (zh) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5293500A (en) * | 1989-02-10 | 1994-03-08 | Mitsubishi Denki K.K. | Parallel processing method and apparatus |
US5781753A (en) | 1989-02-24 | 1998-07-14 | Advanced Micro Devices, Inc. | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions |
US5768575A (en) * | 1989-02-24 | 1998-06-16 | Advanced Micro Devices, Inc. | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions |
US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
US5185871A (en) * | 1989-12-26 | 1993-02-09 | International Business Machines Corporation | Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions |
EP0945787A3 (en) * | 1991-07-08 | 2008-12-31 | Seiko Epson Corporation | Risc microprocessor architecture implementing fast trap and exception state |
US5539911A (en) | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
EP0886209B1 (en) * | 1991-07-08 | 2005-03-23 | Seiko Epson Corporation | Extensible risc microprocessor architecture |
US5961629A (en) * | 1991-07-08 | 1999-10-05 | Seiko Epson Corporation | High performance, superscalar-based computer system with out-of-order instruction execution |
US5363495A (en) * | 1991-08-26 | 1994-11-08 | International Business Machines Corporation | Data processing system with multiple execution units capable of executing instructions out of sequence |
GB2263565B (en) * | 1992-01-23 | 1995-08-30 | Intel Corp | Microprocessor with apparatus for parallel execution of instructions |
US5438668A (en) | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
WO1994008287A1 (en) | 1992-09-29 | 1994-04-14 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
US6735685B1 (en) | 1992-09-29 | 2004-05-11 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
US5410657A (en) * | 1992-10-09 | 1995-04-25 | International Business Machines Corporation | Method and system for high speed floating point exception enabled operation in a multiscalar processor system |
DE69325769T2 (de) * | 1992-11-04 | 2000-03-23 | Digital Equipment Corp., Maynard | Erkennung von Befehlssynchronisationsfehlern |
JP2549256B2 (ja) * | 1992-12-01 | 1996-10-30 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 浮動小数点プロセッサへデータを転送する方法及び装置 |
JP3182591B2 (ja) * | 1993-01-20 | 2001-07-03 | 株式会社日立製作所 | マイクロプロセッサ |
GB9305263D0 (en) * | 1993-03-15 | 1993-05-05 | Univ Westminster | Parrallel computation |
JP2596712B2 (ja) * | 1993-07-01 | 1997-04-02 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 近接した分岐命令を含む命令の実行を管理するシステム及び方法 |
CA2123442A1 (en) * | 1993-09-20 | 1995-03-21 | David S. Ray | Multiple execution unit dispatch with instruction dependency |
US5471598A (en) * | 1993-10-18 | 1995-11-28 | Cyrix Corporation | Data dependency detection and handling in a microprocessor with write buffer |
US6219773B1 (en) | 1993-10-18 | 2001-04-17 | Via-Cyrix, Inc. | System and method of retiring misaligned write operands from a write buffer |
US5584009A (en) * | 1993-10-18 | 1996-12-10 | Cyrix Corporation | System and method of retiring store data from a write buffer |
US5740398A (en) * | 1993-10-18 | 1998-04-14 | Cyrix Corporation | Program order sequencing of data in a microprocessor with write buffer |
US5615402A (en) * | 1993-10-18 | 1997-03-25 | Cyrix Corporation | Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch |
TW353732B (en) * | 1994-03-31 | 1999-03-01 | Ibm | Processing system and method of operation |
CN1048344C (zh) * | 1994-05-24 | 2000-01-12 | 禹成海 | 一种适度耦合多处理机系统的体系结构 |
US5465336A (en) * | 1994-06-30 | 1995-11-07 | International Business Machines Corporation | Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system |
US5666506A (en) * | 1994-10-24 | 1997-09-09 | International Business Machines Corporation | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle |
US5870612A (en) * | 1996-10-15 | 1999-02-09 | International Business Machines Corporation | Method and apparatus for condensed history buffer |
US5805906A (en) * | 1996-10-15 | 1998-09-08 | International Business Machines Corporation | Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions |
US5860014A (en) * | 1996-10-15 | 1999-01-12 | International Business Machines Corporation | Method and apparatus for improved recovery of processor state using history buffer |
US6070235A (en) * | 1997-07-14 | 2000-05-30 | International Business Machines Corporation | Data processing system and method for capturing history buffer data |
US6065086A (en) * | 1998-02-17 | 2000-05-16 | International Business Machines Corporation | Demand based sync bus operation |
US6564298B2 (en) | 2000-12-22 | 2003-05-13 | Intel Corporation | Front end system having multiple decoding modes |
US20070083192A1 (en) * | 2005-10-07 | 2007-04-12 | Eric Welch | Apparatus and method for ablation of targeted tissue |
TWI348652B (en) * | 2005-10-17 | 2011-09-11 | Via Tech Inc | Driver assisted asynchronous command processing |
US20070157030A1 (en) * | 2005-12-30 | 2007-07-05 | Feghali Wajdi K | Cryptographic system component |
US20070192571A1 (en) * | 2006-02-14 | 2007-08-16 | Feghali Wajdi K | Programmable processing unit providing concurrent datapath operation of multiple instructions |
CN102617431B (zh) * | 2011-01-28 | 2013-09-25 | 天津滨海索尔特生物技术中心有限公司 | 用无机碱提取盐藻中的β-胡萝卜素的方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3229260A (en) * | 1962-03-02 | 1966-01-11 | Ibm | Multiprocessing computer system |
US3896418A (en) * | 1971-08-31 | 1975-07-22 | Texas Instruments Inc | Synchronous multi-processor system utilizing a single external memory unit |
GB1441458A (en) * | 1972-06-28 | 1976-06-30 | Texas Instruments Inc | Stored programme data processing for parallel processing of programme segment |
US3793631A (en) * | 1972-09-22 | 1974-02-19 | Westinghouse Electric Corp | Digital computer apparatus operative with jump instructions |
CH556576A (de) * | 1973-03-28 | 1974-11-29 | Hasler Ag | Einrichtung zur synchronisierung dreier rechner. |
FR2471631B1 (fr) * | 1979-12-11 | 1986-02-21 | Cii Honeywell Bull | Dispositif de synchronisation et d'affectation de processus entre plusieurs processeurs dans un systeme de traitement de l'information |
JPS6043535B2 (ja) * | 1979-12-29 | 1985-09-28 | 富士通株式会社 | 情報処理装置 |
JPS58114274A (ja) * | 1981-12-28 | 1983-07-07 | Hitachi Ltd | デ−タ処理装置 |
US4498136A (en) * | 1982-12-15 | 1985-02-05 | Ibm Corporation | Interrupt processor |
US4564901A (en) * | 1983-07-21 | 1986-01-14 | Burroughs Corporation | Method of performing a sequence of related activities via multiple asynchronously intercoupled digital processors |
JPH0744849B2 (ja) * | 1985-07-31 | 1995-05-15 | 株式会社ニコン | 超音波モータ |
JPS6246341A (ja) * | 1985-08-23 | 1987-02-28 | Hitachi Ltd | 付加プロセツサの入出力制御方法 |
US4763294A (en) * | 1985-12-19 | 1988-08-09 | Wang Laboratories, Inc. | Method and apparatus for floating point operations |
JP2610821B2 (ja) * | 1986-01-08 | 1997-05-14 | 株式会社日立製作所 | マルチプロセツサシステム |
JPS6365528A (ja) * | 1986-09-06 | 1988-03-24 | Nec Corp | コ・プロセツサ |
JPS63282528A (ja) * | 1987-02-04 | 1988-11-18 | Sharp Corp | 中央処理装置実行命令の検出方式 |
ATE85853T1 (de) * | 1987-03-20 | 1993-03-15 | Digital Equipment Corp | Vorrichtung und verfahren zur synchronisation von arithmetischen exceptionen in parallelen pipeline-ausfuehrungseinheiten. |
EP0312764A3 (en) * | 1987-10-19 | 1991-04-10 | International Business Machines Corporation | A data processor having multiple execution units for processing plural classes of instructions in parallel |
US4937741A (en) * | 1988-04-28 | 1990-06-26 | The Charles Stark Draper Laboratory, Inc. | Synchronization of fault-tolerant parallel processing systems |
-
1989
- 1989-01-13 US US07/297,783 patent/US5075840A/en not_active Expired - Fee Related
- 1989-08-18 CA CA000608713A patent/CA1321655C/en not_active Expired - Fee Related
- 1989-11-02 AU AU44337/89A patent/AU618142B2/en not_active Ceased
- 1989-12-09 CN CN89109161A patent/CN1013067B/zh not_active Expired
- 1989-12-13 KR KR1019890018447A patent/KR930004214B1/ko not_active IP Right Cessation
- 1989-12-13 PH PH39687A patent/PH30201A/en unknown
- 1989-12-13 MY MYPI89001751A patent/MY105754A/en unknown
- 1989-12-20 EP EP89313401A patent/EP0377991B1/en not_active Expired - Lifetime
- 1989-12-20 GB GB8928776A patent/GB2227108A/en not_active Withdrawn
- 1989-12-20 DE DE68927911T patent/DE68927911T2/de not_active Expired - Fee Related
-
1990
- 1990-01-12 JP JP2003662A patent/JP2645669B2/ja not_active Expired - Lifetime
- 1990-01-12 BR BR909000112A patent/BR9000112A/pt not_active Application Discontinuation
-
1997
- 1997-07-23 HK HK97101597A patent/HK1000050A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0377991B1 (en) | 1997-03-26 |
CN1013067B (zh) | 1991-07-03 |
AU4433789A (en) | 1990-07-19 |
DE68927911T2 (de) | 1997-09-18 |
AU618142B2 (en) | 1991-12-12 |
KR930004214B1 (ko) | 1993-05-21 |
CN1044177A (zh) | 1990-07-25 |
JP2645669B2 (ja) | 1997-08-25 |
BR9000112A (pt) | 1990-10-23 |
JPH02227769A (ja) | 1990-09-10 |
KR900012155A (ko) | 1990-08-03 |
EP0377991A2 (en) | 1990-07-18 |
HK1000050A1 (en) | 1997-10-24 |
CA1321655C (en) | 1993-08-24 |
EP0377991A3 (en) | 1991-07-31 |
MY105754A (en) | 1995-01-30 |
GB8928776D0 (en) | 1990-02-28 |
US5075840A (en) | 1991-12-24 |
GB2227108A (en) | 1990-07-18 |
DE68927911D1 (de) | 1997-04-30 |
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