NO975865L - Anordning for tilveiebringelse av en felles bearbeidelsestakt for flere datasignaler - Google Patents

Anordning for tilveiebringelse av en felles bearbeidelsestakt for flere datasignaler

Info

Publication number
NO975865L
NO975865L NO975865A NO975865A NO975865L NO 975865 L NO975865 L NO 975865L NO 975865 A NO975865 A NO 975865A NO 975865 A NO975865 A NO 975865A NO 975865 L NO975865 L NO 975865L
Authority
NO
Norway
Prior art keywords
common processing
processing rate
pulse width
rate
data signals
Prior art date
Application number
NO975865A
Other languages
English (en)
Other versions
NO975865D0 (no
Inventor
Klaus Ruthemann
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of NO975865D0 publication Critical patent/NO975865D0/no
Publication of NO975865L publication Critical patent/NO975865L/no

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Anordning for utlesing av en felles bearbeidelsestakt for flere datasignaler, hvis takt er frekvenslik, men faseforskjøvet i forhold til hverandre. Det er anordnet for hvert datasignal (Dl) en fasediskriminator (PD1), som gjengir faseawiket til de individuelle taktene (TS1) i forhold til den felles bearbeidelsestakten (TL) i form av et pulsbredde- modulert signal (Pl). Dessuten er det anordnet en multiplekser (MUX), som gjennomkobler alle inngangssidige parallelle anliggende pulsbreddemodulerte fase- awiksignal (Pl,.....Pn) cyklisk etter hverandre på en seriell utgang. Av det serielle pulsbreddemodulerte utgangssignalet (PS) til multiplekseren (MUX) utledes et reguleringskriterium (PSM) for bearbeidelsestakten (TL).
NO975865A 1996-12-13 1997-12-12 Anordning for tilveiebringelse av en felles bearbeidelsestakt for flere datasignaler NO975865L (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19651834A DE19651834C1 (de) 1996-12-13 1996-12-13 Anordnung zum Gewinnen eines gemeinsamen Verarbeitungstaktes für mehrere Datensignale

Publications (2)

Publication Number Publication Date
NO975865D0 NO975865D0 (no) 1997-12-12
NO975865L true NO975865L (no) 1998-06-15

Family

ID=7814563

Family Applications (1)

Application Number Title Priority Date Filing Date
NO975865A NO975865L (no) 1996-12-13 1997-12-12 Anordning for tilveiebringelse av en felles bearbeidelsestakt for flere datasignaler

Country Status (3)

Country Link
EP (1) EP0848513A3 (no)
DE (1) DE19651834C1 (no)
NO (1) NO975865L (no)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4327411A (en) * 1980-03-04 1982-04-27 Bell Telephone Laboratories, Incorporated High capacity elastic store having continuously variable delay
US4718074A (en) * 1986-03-25 1988-01-05 Sotas, Inc. Dejitterizer method and apparatus
DE4025831A1 (de) * 1990-08-16 1992-02-20 Philips Patentverwaltung Pufferspeicher
US5502750A (en) * 1994-06-15 1996-03-26 Pericom Semiconductor Corp. Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network
JP3403849B2 (ja) * 1995-03-17 2003-05-06 富士通株式会社 多重無線装置の受信部に設けられるクロック位相検出回路及びクロック再生回路

Also Published As

Publication number Publication date
NO975865D0 (no) 1997-12-12
EP0848513A3 (de) 2000-09-20
EP0848513A2 (de) 1998-06-17
DE19651834C1 (de) 1998-08-20

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Legal Events

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FC2A Withdrawal, rejection or dismissal of laid open patent application