FR2714240B1 - Dispositif de compensation de phase de trame - Google Patents

Dispositif de compensation de phase de trame

Info

Publication number
FR2714240B1
FR2714240B1 FR9415427A FR9415427A FR2714240B1 FR 2714240 B1 FR2714240 B1 FR 2714240B1 FR 9415427 A FR9415427 A FR 9415427A FR 9415427 A FR9415427 A FR 9415427A FR 2714240 B1 FR2714240 B1 FR 2714240B1
Authority
FR
France
Prior art keywords
demultiplexing
data
compensation device
phase compensation
multiplexing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9415427A
Other languages
English (en)
Other versions
FR2714240A1 (fr
Inventor
Sang Hoon Lee
Jung Hoon Ko
Tae Hee Lee
Chang Sup Shim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electronics and Telecommunications Research Institute ETRI
KT Corp
Original Assignee
Electronics and Telecommunications Research Institute ETRI
KT Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electronics and Telecommunications Research Institute ETRI, KT Corp filed Critical Electronics and Telecommunications Research Institute ETRI
Publication of FR2714240A1 publication Critical patent/FR2714240A1/fr
Application granted granted Critical
Publication of FR2714240B1 publication Critical patent/FR2714240B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Ce dispositif comprend des moyens de sélection 2:1 (8) pour sélectionner l'un de deux signaux d'entrée présentant des écarts temporels, des moyens (28) de production de signaux de sélection, des moyens (9) de production de signaux de commande pour le démultiplexage des données qui ont été sélectionnées, des moyens (10) de démultiplexage pour démultiplexer sous la forme de données à faible vitesse, les données qui ont été sélectionnées, des moyens (12) de multiplexage pour réaliser la synchronisation sur un signal synchrone de trame de référence et un signal d'horloge de référence et multiplexer les données délivrées par les moyens (10) de démultiplexage, et des moyens (11) de production de signaux de référence. Application notamment aux systèmes de transfert numérique de données.
FR9415427A 1993-12-21 1994-12-21 Dispositif de compensation de phase de trame Expired - Fee Related FR2714240B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93028932A KR960009536B1 (en) 1993-12-21 1993-12-21 Apparatus for arranging frame phase

Publications (2)

Publication Number Publication Date
FR2714240A1 FR2714240A1 (fr) 1995-06-23
FR2714240B1 true FR2714240B1 (fr) 1998-09-04

Family

ID=19372022

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9415427A Expired - Fee Related FR2714240B1 (fr) 1993-12-21 1994-12-21 Dispositif de compensation de phase de trame

Country Status (3)

Country Link
US (1) US5546401A (fr)
KR (1) KR960009536B1 (fr)
FR (1) FR2714240B1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE515563C2 (sv) * 1995-01-11 2001-08-27 Ericsson Telefon Ab L M Dataöverföringssystem
US5751724A (en) * 1996-02-23 1998-05-12 Dsc Communications Corporation Demultiplexer for a multi-bitline bus
US20020044548A1 (en) 1996-07-15 2002-04-18 Mark J. Foladare Coupling multiple low data rate lines to effect high data rate communication
US5923671A (en) * 1996-07-22 1999-07-13 At&T Corp Coupling multiple low data rate lines to effect high data rate communication
US5940403A (en) 1996-11-07 1999-08-17 Adtran, Inc. Quarter-rate 2B1Q ISDN architecture with embedded differential delay compensation for extending range of DDS communications
US6201843B1 (en) * 1999-02-25 2001-03-13 L-3 Communications, Inc. Rapid acquisition dispersive channel receiver integrated circuit
US6721896B1 (en) * 2000-03-31 2004-04-13 Alcatel System and method for converting a selected signal into a timing signal and inserting the phase of the timing signal into a framed signal
US7239254B1 (en) * 2006-03-31 2007-07-03 Intel Corporation Programmable multi-cycle signaling in integrated circuits
US9270397B2 (en) * 2012-10-24 2016-02-23 Cisco Technology, Inc. Cascaded communication of serialized data streams through devices and their resulting operation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4434485A (en) * 1980-11-13 1984-02-28 Rockwell International Corporation Drop and insert channel bank with reduced channel units
US5331641A (en) * 1990-07-27 1994-07-19 Transwitch Corp. Methods and apparatus for retiming and realignment of STS-1 signals into STS-3 type signal
KR930002134B1 (ko) * 1990-10-24 1993-03-26 삼성전자 주식회사 병렬 데이타 전송 처리회로
DE69218999T2 (de) * 1991-05-01 1997-10-23 Motorola Inc Breitbandiger digitaler Phasenausrichter
CA2105268C (fr) * 1992-12-28 1999-07-13 Shahrukh S. Merchant Resynchronisation du mode de transfert asynchrone dans une memoire active

Also Published As

Publication number Publication date
KR950019570A (ko) 1995-07-24
US5546401A (en) 1996-08-13
KR960009536B1 (en) 1996-07-20
FR2714240A1 (fr) 1995-06-23

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20110831