NO834009L - PROCEDURE AND APPARATUS FOR MANUFACTURING MULTI-LAYER CIRCUITS - Google Patents

Description

The present invention relates to a method for the production of finely lined, high-density printed circuit boards and packages of multi-layer printed circuit boards.

There are many methods of manufacturing printed circuit boards that are used extensively in the electronics industry. The phenomenon of very large scale integrated circuits ("VLSI", very large scale integrated circuits) has created an ever-increasing need for higher component density per printed circuit board unit area. To meet this growing need, printed circuit boards must be manufactured with extremely narrower conductor line widths and spacings. Due to limitations inherent in the previously known methods, these cannot successfully meet the industry's need for multilayer printed circuit boards with good dimensional stability and increasingly narrow line widths and distances.

Although many methods are known that are used in the production of printed circuit boards, most use accepted methods with etching techniques. Typically, these methods include the steps of applying a base of an electrically insulating material with a conductive copper foil, placing a photoresist material in intimate contact therewith, developing the photoresist material to define a conductive circuit pattern, and etching away the exposed foil which is not covered with the photoresist material to provide a highlighted conductive circuit pattern.

This known method presents various problems. Because the conductive pattern is not flush with the surface of the circuit board, a conductive line can easily be scraped away during processing, resulting in an open circuit. Furthermore, the copper conductor can slip and come into contact with adjacent conductors, causing short circuits.

Furthermore, the etching step> in the known technique can also create various irregularities and defects in the printed circuit. The etching can cause a conductor to be over-etched near the base, which undercuts the conductor and gives a non-uniform mushroom-shaped cross-section. Furthermore, the photoresist can be captured at the side, by the mushroom edges, which prevents the foil hidden under the captured photoresist from being etched away. Over-etching therefore makes it extremely difficult to achieve control of the stability of fine lines and line width, when line and distance widths and tolerances become smaller. Etching fabrication can therefore result in various defects on conductive lines, can cause reductions in the yield of cards with a consequent discarding of the printed circuits, which in turn increases the final production costs.

Card flatness and dimensional stability are important characteristics to ensure that printed circuits maintain a continuous conductive connection with component conductors and adjacent cards. However, temperature and pressure fluctuations that occur during lamination cause warping to occur, which causes significant stresses in the circuit that is mounted in equipment rails. These stresses can cause conductors to break and/or float off the substrate produced by the prior art techniques, because they have poor ductility and are not flush with the circuit board.

The quality and stability of multilayer circuit board packages

is also limited by the known production methods. To produce such packages, the lamination bond between insulation layers must lie between circuit board layers to fill voids between the raised conductor lines and the circuit board substrate. Filling the voids requires high pressures during lamination, which can destructively destroy the conductor lines. Furthermore'can even. very high pressures do not ensure that the laminates fill all cavities. Finally, many voids may remain in the finished multi-layer package, which then become storage sites for impurities. Such impurities can cause electrical short circuits. Furthermore, the laminating bond layer and short-

the surfaces may be of different material compositions because they are often obtained from different manufacturers, may be made of different resins or come from different production batches.

As a result, the finished multilayer package is not homogeneous. The lack of homogeneity makes it difficult to provide correct drilling speeds and drilling angles when creating holes through the multilayers. In some cases, the drilling speed will be too great to cut through cups, which causes tearing, but will be a suitable speed for cutting through the insulation. Thus, some of the layers will have tearing and others will be smooth and some will be extremely uneven, which contributes to reduced card quality with increasing unit costs.

Achieving high density in printed circuits also requires that a uniform, continuous conductive coating be applied to small diameter holes drilled through multilayer packages for component connections and connectors. A technique that has found widespread use for the production of conductive hole walls is electroless coating, whereby an electroless metal deposit, usually of copper, is uniformly coated on the dielectric card substrate. This technique has the disadvantage that a coating is deposited which has poor adhesion qualities so that additional steps are required to ensure adequate adhesion. Other techniques are the application of a

thin electroless coating on the entire wall and then electro-coating to further build up the conductive surfaces. However, conventional electroplating techniques cannot be used for holes with small diameters and large depths, as is required for the printed circuits with high density and fine lines. Therefore, the prior art teaches plating of holes with very small diameters such as 0.0115" or less entirely by electroless operation, which usually requires considerably more machining time, 24 hours or more.

The present invention includes a method for producing high-density printed circuit boards with fine lines and printed circuit board packages and circuit boards and packages made according to the invention.

A flash layer of conductive material, preferably copper, is electrodeposited on a rigid metal or metallized substrate having a low coefficient of thermal expansion. A thickness of photosensitive resist is deposited on the first layer by screen printing or other known methods. A stencil is placed over the resist to define a conductive circuit pattern on the surface of the resist. The template is expanded to light and the resist developed. Channels with straight and parallel walls in the resist will form and define the conductive circuit pattern by duplicating the photo stencil pattern upon exposure of the flash layer.

Another layer of conductive material builds up the physically exposed parts of the flash layer of the conductive material in the channels and forms a raised conductive circuit pattern with a thickness that does not exceed the depth of the channels. The . the remaining photosensitive resist is then removed from the flash layer.

The flash layer and the second layer defining a prominent conductive circuit pattern are completely covered with a uniform layer of an insulating laminate material. Pressure is applied to completely envelop the highlighted conductive layers in the insulating material, so that the flash layer of conductive material remains in intimate and continuous contact with the insulating material.

The flash layer, integrated with the highlighted conductive circuit pattern and the insulator material is separated from the rigid substrate. The conductive flash layer is then etched away so that the conductive circuit pattern is embedded in the insulator material exposed as lying flush and level with the surface of the insulator material.

Printed circuit boards can be manufactured with sheathed conductors exposed on a single side. However, a double-sided board can be produced if this is desired by heat-pressing two such printed circuit boards against each other,

back to back, or by embedding the leaders on both sides of a single card.

The finished circuit boards are stacked with a layer of insulating laminate bonding material placed between each printed circuit board layer. The layers of printed circuits and intermediate insulating material are hot-pressed together to form a homogeneous package of the insulating material with conductive circuit board patterns embedded.

To prepare the cards for the components and connectors, holes are drilled through the homogeneous package. The holes are coated with a thin layer of conductive material, preferably copper, using an electroless coating method to provide a conductive substrate for electrodeposition of additional conductive material. Using an electrodeposition apparatus with a high strike rate, a continuous layer of conductive material of uniform thickness is coated on the hole walls.

A main object of the invention is to provide a method for producing printed circuits with

high density and fine lines, whereby the conductive circuit pattern. lies flush and level with the insulating substrate.

A further object of the invention is to provide a method for the production of fine-line, high-density printed circuits, whereby the conductor lines have improved ductility properties.

A further object of the invention is to provide a method for the production of fine-line, high-density printed circuits with improved dimensional stability.

A further object of the invention is to provide a method for producing finely lined and high-density printed circuits, whereby the conductive circuits have a uniform width along the entire cross-section.

A further object of the invention is to provide a method for the production of fine-line and high-density printed circuit board packages with multiple layers and with uniform insulation material? with flat, stable, throw-free and cavity-free properties.

A further object of the invention is to provide a method for the production of finely lined, high-density printed circuit board packages with a small diameter in the through-holes and with uniform and continuous conductor thickness on the walls.

Further objects of the invention will appear at

a reading of the following description together with the accompanying drawings, where the same reference numbers refer to the same parts.

Figure 1 shows a side view of a substrate with a flash layer

applied.

Figure 2 is a side view of the substrate in Figure 1 with a layer

of photoresist applied.

Figure 3 is a perspective sketch of the object in Figure 2

with a photo template arranged.

Figure 4 is a perspective sketch along the line 4-4 in the figure

3 and shows rectangular channels defining a conductive circuit pattern developed in the photoresist layer after the phototemplate is removed. Figure 5 is a side view of highlighted conductive lines placed in the photoresist channels on the flash layer along the line 4-4 in Figure 3. Figure 6 is a perspective sketch of the highlighted conductive circuit pattern in Figure 5 after the remaining photoresist has been removed.

Figure 7 is a view along the line 4-4 in Figure 3 and shows

an insulator laminate layer covering the conductive circuit pattern and flash layer in Figure 6.

Figure 8 is a view along the line 4-4 in Figure 3 and shows the objects according to Figure 7 removed from the rigid substrate. Figure 9 is the object in figure 8 seen from above with the flash layer etched away to thereby expose the conductive circuit pattern embedded in and flush with the insulator laminate. Figure 10 is a cross-section of the printed circuit board along

the line 9—9 in figure 9.

Figure 11 is a side view of a printed circuit board with drilled registration holes. Figure 12 is a perspective cross-section of a number of printed circuit boards and insulator laminate layers placed between them and stacked up in a conventional press. Figure 13 is a perspective view showing a homogeneous multilayer

printed circuit board package according to the invention, and

Figure 14 is a partial perspective view showing electro-deposited and electroless-deposited coating layers, built up with conductor holes or contact holes according to the invention.

Referring to Figure 1, a substrate 10 consists of a material such as stainless steel with a metallized surface to receive a flash layer of electrodeposited material.

In the preferred embodiment, the substrate is a rigid metal or metallized plate. However, other rigid material compositions with suitable properties can be used, such as a metallized glass material, e.g. metallized pyrex, with a very low coefficient of thermal expansion. The substrate must have a low coefficient of thermal expansion to ensure that when a conductor is placed thereon, it will not shift or flow from the design positions due to the thermal expansion in the substrate that occurs during a subsequent compression step.

A flash layer of electrically conductive material 12, preferably copper, is electro-deposited on the substrate 10. The copper flash layer 12 serves as a base layer on which further electro-coating of conductor lines can be applied. It also serves as a release material to separate the one printed circuit from the stainless steel substrate 10 after the printed circuit board is finished, as will be described below.

The flash layer is as thin as it can be, because the heat transfer properties of a very thin layer tend to speed up heat transfer when heated, causing improved stability in the conductive lines. As a result, a flash layer with a thickness of only 0.0001" to 0.0002" is deposited on the substrate in the preferred embodiment. Furthermore, a very thin layer is less wasteful. The thin electroplated coating is obtained by using an electroplating apparatus commonly known as a high impact rate coating apparatus such as that described

in US-PS 4,174,261, known as "RISP" and commercially available from Economics Laboratory, Inc. Osborn Building, St.

Paul, Minnesota, 55102. Alternatively, any conventional electroplating apparatus may be used to apply the copper flash layer to the substrate. However, the known conventional electrocoating apparatus generally cannot apply such an extremely thin layer as desired according to the invention without causing holes or other defects and they are therefore not preferred.

A low contact pressure is desired at the interface between the flash layer and the substrate to facilitate separation of the flash layer from the substrate. Low contact pressure can be achieved by using different materials for flash layer and substrate such as, but not limited to, the use of a copper flash layer with a stainless steel substrate as occurs in the preferred embodiment. Alternatively, materials with similar surfaces can be used, if one of them is coated with an impurity to reduce adhesion at the interface.

In the preferred embodiment, the printed circuit can be fabricated on one side of the stainless steel substrate, but for multi-layer applications they can be fabricated on both sides of the substrate. This enables maximum production performance and allows optimal use of electroplating and other equipment used.

With general reference to Figures 2-5, a layer of photosensitive resist material 4 such as "Dryfilm" from Dupont is placed on the copper flash surface 12 of the substrate 10 using techniques well known. The photoresist will be either positive so that it dissolves on exposure to light, or negative, i.e. it does not dissolve on exposure to light. A photo stencil 16 defining a conductive circuit pattern 18 is placed on top of the photoresist layer 14 using well-known techniques. The photo template 16 is aligned on and brought into continuous contact with the surface of the photoresist 14 to ensure high resolution of the conductive circuit pattern on the surface of the photoresist 14. The phototemplate masks the surface of the photoresist so that when it is exposed to light only the areas that define the manager, exposed.

After the photo template 16 has been exposed to light, it is removed

it and the photoresist 14 are developed using a commercially available developer such as "Resist Stripper"

from DuPont. As a result, cavities 20 are formed in the areas where the photoresist 14 dissolves and exposes the copper flash layer 12 that was previously covered by the photoresist 14, in a defined circuit pattern 18. The walls of the cavities 20 are parallel to each other and perpendicular to the substrate

10 and act as essentially rectangular channels

which runs in the remaining undissolved photoresist 14 according to the original circuit pattern 18 which was defined by the template 16.

The whole is placed in an electroplating apparatus with a high impingement rate and where the preferred apparatus is the above-mentioned "RISP" apparatus. A conductive material 26 such as copper is electrodeposited on the exposed copper flash layer 12 at the bottom of the rectangular channels 20 instead of using the subtractive etching method taught in the prior art. The electrodeposited material 26 accumulates in the channels to a desired thickness of approx. 1.2 to approx. 15 mils (1.2 mil thickness of cups per ft<2> to 1.5 mil thickness of cups per ft2 ), and the thickness is chosen to prevent "mushrooming" in the electrodeposited material as previously occurred. However, at no time should the thickness exceed the depth of the channels.

The additive electrodeposition procedure provides the lines 26 with smooth and vertical walls of uniform cross-sectional width, which facilitates fine line resolution and enables easy control of line width and densities with extremely narrow dimensions. The use of the "RISP" equipment enables conductor lines to be coated at a speed and uniformity that is considerably better than could be achieved by the known electroplating techniques. In addition, processes with rapid shocks produce very ductile conductors, which is essential to prevent defects and errors in conductor lines with very small cross-sections.

Referring generally to Figures 5-8, the photoresist layer 14 is chemically stripped from the copper flash surface 12 exposing the highlighted electroplated conductive circuit lines 26 arranged in the pattern 18. A layer of insulating material 32 such as an epoxy coated fiberglass is laminated to the copper flash layer 12 to completely cover this and the excellent conductive circuit pattern 18. Thermosetting of insulating material such as epoxy-coated fiberglass is used because of low costs and good temperature properties. If epoxy-coated fiberglass is not used, alternative materials such as polypropylene, phenol compounds or Teflon can be used.

The insulating layer 32 is laminated over the conductive circuit pattern and the copper flash layer 12 using heat and pressure according to the selected laminate material, carried out with a rigid laminating press. When epoxy-coated fiberglass is used, this lamination step can be carried out at a pressure of approx. 50-200 lb/inch2 , depending on the weave in the glass fabric (thicker glass requires more pressure to harden the epoxy inside the weave) and at a temperature of approx. 425°F. The insulating material 32 will thereby flow and completely fill all cavities between the protruding conductor lines 26 and will also provide a strong bond with the conductors. The insulator material 32 should be of uniform thickness, so that the conductor lines 26 in the printed circuits 18 are completely covered by the insulator material.

The insulator material 32 in which the pattern 18 is formed and enveloped and which is bonded to the copper flash layer 12 is manually separated from the surface of the substrate 10. The copper flash layer 12 is then removed from the insulator material 32 using conventional etching techniques or a high-speed etching apparatus to thereby expose the conductors 26 in the circuit pattern 18, embedded in the insulating material. Figures 9 and 10 show the resulting printed circuit boards, generally indicated as 36. As illustrated in Figure 10, the conductors 26 of the circuit pattern 18 are flush with the surface 34

of the insulating material 32 and has no abutting edges or protruding surfaces. Thus, the conductive circuit pattern is completely bounded and cannot move. This is in contrast to the floating or shifting that has been a general problem with printed circuit boards that have been produced using previously known methods and where the conductive circuit patterns were located over an insulating material base. The sheathed conductor configuration which arises according to the invention provides a durable and very stable composition which enables large continuous sheets of printed circuits to be produced with extremely small tolerances.

The oxide that forms on the copper conductors does not bond well to the insulation material. Therefore, the entire card 36 with the conductive circuit pattern 18 is immersed in a chemical bath such as these are available under the designation "Macublack" from McDermott. The chemical coating improves the adhesion quality of the laminate and further ensures that if the card is stacked, the copper surface of one card will adhere to the laminate surface of the adjacent one. This is particularly important for cards with surfaces that expose most cups and thus very little laminate.

At this stage in the present process, a layer 36 is off

a printed circuit complete. Thus, after a printed circuit with the desired conductor patterns has been produced, multi-layer packages of printed circuits can be produced. A layer of insulating material 44 is placed between each layer of the printed circuits 36. This insulating material 44 is of the same composition as was used in the laminate structure in the printed circuit. Thus, a number of printed circuit board layers 36 were laid on top of each other with layers of insulating material 44 arranged between them.

With general reference to Figures 9-13, registration holes 38 are drilled through each printed circuit board 36 and the insulating layer 44 to be included in the multilayer package. An optically guided reading system such as that manufactured by Sportonics in Rockford, Illinois, seeks the target where the hole is to be made and this is then drilled through so that there is a hole per goal. The registration holes 38 provide mounting devices for stacking the printed circuit boards 36 and the insulating layers 44 on mounting rods 46 so that the multiple layers of printed circuits will lie well aligned between a pair of printing surfaces 48 of which only one is shown.

The printed circuit boards 36 with intervening insulating material layers 44 are pressed together between a pair of pressure surfaces 48 in a conventional press at a temperature of 375-425°F to provide a pressure of approximately 250 lb|inch<2>to form a multi-layer package. 54. However, when in the preferred embodiment 50 psi is used to press a single layer, the same pressure will be used throughout the process.

Previously known such circuit board packages often had layers

which used insulation materials of different compositions or produced in different batches. Produce- . However, the use of multi-layer printed circuit board packages according to the invention makes it possible for the intermediate insulating material layer as well as the laminate base in the printed circuit board layer to be of the same material. This results in a homogeneous and continuous material structure when the layers are hot-pressed together to form a package 54. Furthermore, because the printed circuit board layers according to the invention are flush and have no outstanding elements, the production of the multi-layer package is carried out without voids or other irregularities in the package structure. Also, because the surface of each circuit board layer is flush, lower pressures can be used to form the multi-layer package. The advantage of such low pressures is that throw or distortions in the package are avoided during the compression step.

In the prior art, internal shifting and flow resulted

of the application of high pressures during the multilayer package's manufacture significant limitations on the number of circuit board layers that could be contained in a single multilayer package. According to the invention, the combination of developing a homogeneous insulating material in the package together with the elimination of voids by the use of circuits in flight enables a substantial increase in the number of printed circuit board layers that can be pressed into a single package. The present method has been regularly practiced on a maximum of 22 short layers and on a maximum of 40 layers on a more limited basis. However, the invention is not limited thereby and it is possible that packs with an even greater number of cards can be produced using the method of the invention.

Referring to Figure 14, connection and component holes 58 are drilled through the multilayer package 44 using conventional drilling devices. The holes generally have a diameter of between 0.0115 and 0.093". The holes are then cleaned to remove drill debris using cleaning devices as are well known in the art or by a high impact rate coating apparatus.

As generally shown in Figure 14, a copper layer 56 having a thickness of 0.000050" is deposited on the hole walls 58 using a conventional electroless plating process. The copper deposit serves as a base to provide sufficient conductivity to conduct current for electrolysis. It should be pointed out that if the copper layer is too thin, it will simply burn away due to the heat generated

nes during the electrolysis.

Once more, the holes are cleaned and rinsed to remove impurities and surface dirt. A second copper layer 60 is then electrolytically applied using a coating apparatus with a high impact velocity, to build up the desired thickness of conductive coating along the walls of the hole 58. It is essential that the described apparatus is used, because conventional electroplating devices do not the long and narrow holes to provide good and conductive coatings. Furthermore, the use of the described electroplating apparatus provides a copper coating with improved ductility properties. Thus, a thermal or other expansion along the vertical axis of the hole will not cause a break in the conductive surface, which could cause a power failure.

The invention is capable of providing conductive lines with widths 'and distances between such down to 2 miles, packages of

layers with up to 40 layers or more through holes down to 5 mil diameter.

While certain embodiments of the invention have been shown and described above, it should be clear that the invention is not limited thereto. According to this, it should be clear to the person skilled in the art that various changes in form and detail can take place without departing from the scope of the invention.

Claims (31)

1. Procedure for the production of printed circuit cards, characterized in that it includes: encasing an outstanding conductive circuit pattern in a uniform layer of insulating material such that a surface of the conductive circuit pattern is exposed flush and flush with the surface of insulating material. 2. Method according to claim 1, characterized in that it comprises: to form an excellent conductive circuit pattern on a rigid substrate, encasing the pattern with a uniform thickness of insulating material, and separation of the encapsulated conductive circuit from the rigid substrate. 3. Method according to claim 1. characterized by the fact that it further includes: creating conductive holes through the circuit board for attaching circuit components. 4. Method for producing a printed circuit board, characterized in that it includes: ■ forming a first layer of a conductive material on a rigid substrate, deposition of photosensitive resist on the first layer of conductive material, masking the photosensitive resist to define a conductive circuit pattern on the surface of the resist, exposing the masked photosensitive resist to light to dissolve portions of the resist according to the conductive circuit pattern where certain portions of the first layer of conductive material are exposed; formation of a second layer of conductive material, on the exposed parts of the first layer of conductive t material in which an excellent conductive circuit pattern is formed over the general plane of the first conductive layer, removing undissolved photosensitive resist from the first layer of conductive material, embedding the conductive circuit pattern on the first conductive layer with a uniform thickness of insulating material, separation of the first conductive layer from the rigid substrate, removal of the first conductive layer from the insulating material, whereby the conductive circuit pattern embedded in the insulating material is exposed flush and level with the surface of the insulating material. 5. Method according to claim 4, characterized in that the second layer of conductive material is electrodeposited on the first layer of conductive material. 6. Method according to claim 4, characterized in that the excellent conductive pattern is embedded in the insulating material by lamination. 7. Method according to claim 4, characterized in that the first layer of conductive material is electrodeposited on the rigid substrate. 8. Method according to claim 4, characterized in that the rigid substrate has a metallized surface and a low coefficient of thermal expansion. 9. Method according to claim 7, characterized in that the first layer of conductive material is electrodeposited on the rigid substrate using an electrocoating apparatus with a high impact speed. 10. Method according to claim 4, characterized in that it further comprises creating conductive holes through said printed circuit board for circuit components and connection between the boards. 11. Method according to claim 4, characterized in that it further comprises to coat the holes with a thin. layer of conductive material, and forming a continuous conductive surface along the walls of the coated holes. 12. Method according to claim 10, characterized in that the holes are obtained by drilling. 13. Method according to claim 11, characterized in that the holes are coated using a thin electroless coating to provide a conductive substrate and electrodeposition of conductive material on the conductive substrate to form the continuous conductive surfaces along the walls of the coated holes. 14. Method according to claim 10, characterized in that it further comprises cleaning impurities from the conductive holes. 15. Method for the production of multi-layer printed circuit board packages, characterized in that it includes: manufacturing a number of printed circuit board layers where each layer is formed by embedding a conductive circuit pattern in an insulating material base, so that the exposed surface of the pattern is flush and level with the surface of the base, stacking a number of circuit board layers on top of each other, placing an insulating layer between each printed circuit board layer, bonding the stack of circuit boards and intermediate layers of insulating material together to form a multi-layer printed circuit board package. 16. Method according to claim 15, characterized in that the production of each printed circuit board layer comprises: forming a first layer of conductive material on a rigid substrate, depositing a thickness of photosensitive resist material on the first layer of conductive material, masking the photosensitive resist to define a conductive circuit pattern on the surface of the photosensitive resist, exposing the masked photosensitive resist to light to dissolve portions of the resist according to the conductive circuit pattern where the portion of the first layer of conductive material is exposed; forming a second layer of conductive material on the exposed portions of said first layer of conductive material to form an excellent conductive circuit pattern, removing undissolved photosensitive resist from the first layer of conductive material, embedding of. the excellent conductive circuit pattern on the first conductive layer with a uniform thickness of insulating material, separation of the first conductive layer from the rigid substrate, removing said first conductive layer to expose the conductive circuit pattern embedded in the insulating layer, and whereby said exposed circuit pattern lies flush and level with the insulation material. 17. Method according to claim 15, characterized in that the formation of the first layer of conductive material on the rigid substrate comprises electrodeposition of a thin coating of conductive material on a rigid substrate with a metallized surface and low coefficient of thermal expansion. 18. Method according to claim 14, characterized in that the formation of the second layer of conductive material comprises electrodeposition of this to a thickness of 1.2 to 15 mil. 19. Method according to claim 16, characterized in that an electrocoating apparatus is used with a high impact speed for electrodeposition of the second layer. 20.. Method according to claim 16, characterized in that the embedding step comprises lamination of the insulating material over said first and second conductive layers and application of continuous uniform pressure and heat to thereby envelop said second conductive layer with insulating material. 21. Method according to claim 16, characterized in that the circuit boards and the intermediate layer of insulating material are bonded together by applying continuous uniform heat and pressure to form a uniform homogeneous package of insulating material with said conductive circuit pattern embedded. 22. Method according to claim 15, characterized by creating conductive holes through the package for circuit components and connecting the cards to each other. 23. Method according to claim 15, characterized by formation of holes through the package, coating the holes with a thin layer of conductive material, and forming a continuous conductive surface along the walls of the coated holes. 24. Method according to claim 15, characterized in that it comprises: formation of holes through the package, drilling holes for electrical conductors for circuit components and board connection through said stack of printed circuit board layers and intermediate layers of insulating material, and using an electroless coating method to provide a conductive substrate for electrodeposition of conductive material thereon and electrodeposition of conductive material on the conductive substrate. 25. Method according to claim 23, characterized in that, as a further feature, the holes are cleaned immediately before coating. 26. Method according to claim 22, characterized in that the holes are obtained by drilling. 27. Multi-layer package of printed circuit boards, characterized in that it includes: a number of printed circuit board layers, each printed circuit board layer comprising a conductive circuit pattern embedded in and integral with an insulating material substrate, where the surface of the conductive circuit pattern is exposed along a surface of the substrate and lies flush and level with the substrate surface, a layer of insulating material arranged between each printed circuit board layer, wherein the insulating material layer is integrally formed and bonded to adjacent surfaces of said printed circuit board layer, whereby the bonded layers form a uniform homogeneous structure with a number of conductive circuit patterns embedded in and integrally formed in the package. 28. Multi-layer package according to claim 27, characterized in that the insulation material and the substrate in the printed circuit boards comprise the same insulation material 29. Fine-line high-density printed circuit board, characterized in that it comprises: an insulating material substrate, and a conductive circuit pattern embedded in and integral with the insulating material substrate whereby the surface of the conductive circuit pattern is exposed along a surface of the substrate whereby the conductive circuit pattern is flush and planar with the substrate surface. 30. Printed circuit board according to claim 29, characterized in that said embedded conductive circuit pattern comprises conductive lines of essentially rectangular cross-section, the parallel side walls of the conductors being perpendicular to the substrate surface. 31. The printed circuit board according to claim 29, characterized in that the insulator material substrate comprises a dielectric laminate material. 1. Method for producing a printed circuit board, characterized in that it comprises: forming a first layer of a conductive material on a rigid substrate, deposition of photosensitive resist on the first layer of conductive material, masking the photosensitive resist to define a conductive circuit pattern on the surface of the resist, exposure of the masked photosensitive resist to light to dissolve parts of the resist according to the conductive circuit pattern where certain parts of the first layer of conductive material are exposed, forming a second layer of conductive material on the exposed portions of the first layer of conductive material in which an outstanding conductive circuit pattern is formed over the general plane of the first conductive layer, removing undissolved photosensitive resist from the first layer of conductive material, embedding the conductive circuit pattern on the first conductive layer with a uniform thickness of insulating material, separation of the first conductive layer from the rigid substrate, removing the first conductive layer from the insulating material, . whereby the conductive circuit pattern that is embedded . in the insulation material is exposed flush and level with the surface of the insulation material. 2. Method according to claim 1. characterized in that the second layer of conductive material is electrodeposited on the first layer of conductive material. 3. Method according to claim 1. characterized in that the excellent conductive pattern is embedded in the insulating material by lamination. 4. Method according to claim 1, characterized in that the first layer of conductive material is electrodeposited on the rigid substrate. 5. Method according to claim 1, characterized in that the rigid substrate has a metallized surface and a low coefficient of thermal expansion. 6. Method according to claim 4, characterized in that the first layer of conductive material is electrodeposited on the rigid substrate using an electrocoating apparatus with a high impact speed. 7. Method according to claim 1, characterized in that it further comprises the creation of conductive holes through said printed circuit board for circuit components and connection between the boards. 8. Method according to claim 1. characterized in that it further comprises to coat the holes with a thin layer of conductive material, and forming a continuous conductive surface along the walls of the coated holes. 9. Method according to claim <7>, characterized in that the holes are obtained by drilling. 10. Method according to claim 8, characterized in that the holes are coated using a thin electroless coating to provide a conductive substrate and electrodeposition of conductive material on the conductive substrate to form the continuous conductive surfaces along the walls of the coated holes. 11. Method according to claim 7, characterized in that it further comprises cleaning impurities from the conductive holes. 12. Method for the production of multi-layer printed circuit board packages, characterized in that it comprises: manufacturing a number of printed circuit board layers where each layer is formed by embedding a conductive circuit pattern in an insulating material base, so that the exposed surface of the pattern lies flush and level with the surface of the base, stacking a number of circuit board layers on top of each other, placing an insulating layer between each printed circuit board layer, bonding the stack of circuit boards and intermediate layers of insulating material together to form a multi-layer printed circuit board package. _13. Method according to claim 12, characterized in that the production of each printed circuit board layer includes: forming a first layer of conductive material on a rigid substrate, depositing a thickness of photosensitive resist material on the first layer of conductive material, masking the photosensitive resist to define a conductive circuit pattern on the surface of the photosensitive resist, exposing the masked photosensitive resist to light to dissolve portions of the resist according to the conductive circuit pattern where the portion of the first layer of conductive material is exposed; .forming a second layer of conductive material on the exposed portions of said first layer of conductive material to form an excellent conductive circuit pattern, ■ removal of undissolved photosensitive resist from the first layer of conductive material, embedding the outstanding conductive circuit pattern on the first conductive layer with a uniform thickness of insulating material, separation of the first conductive layer from the rigid substrate, removing said first conductive layer to expose the conductive circuit pattern embedded in the insulating layer, and whereby said exposed circuit pattern is flush and level with the insulation material. 14. Method according to claim 12, characterized in that the formation of the first layer of conductive material on the rigid substrate comprises electrodeposition of a thin coating of conductive material on a rigid substrate with a metallized surface and low coefficient of thermal expansion. 15. Method according to claim 11, characterized in that the formation of the second layer of conductive material comprises electrodeposition of this to a thickness of 1.2 to 15 mil. 16. Method according to claim 13, characterized in that an electrocoating apparatus is used with a high impact speed for electrodeposition of the second layer. 17. Method according to claim 13,. characterized in that the embedding step comprises lamination of the insulating material over said first and second conductive layers and application of continuous uniform pressure and heat to thereby envelop said second conductive layer with insulating material. 18. Method according to claim 13, characterized in that the circuit boards and the intermediate layer of insulating material are bonded together by applying continuous uniform heat and pressure to form a uniform homogeneous package of insulating material with said conductive circuit pattern embedded. 19. Method according to claim 12/characterized by creating conductive holes through the package for circuit components and connecting the cards to each other. 20 . Method according to claim 12, characterized by formation of holes through the package, coating the holes with a thin layer of conductive material, and forming a continuous conductive surface along the walls of the coated holes. 21. Method according to claim 12, characterized in that it comprises: formation of holes through the package, drilling holes for electrical conductors for circuit components and board connection through said stack of printed circuit board layers and intermediate layers of insulating material, and use an electroless coating method to provide a conductive substrate for electrodeposition of. leading material on this and electrodeposition of conductive material on the conductive substrate. 22 . Method according to claim 20, grade i-, characterized in that, as a further feature, the holes are cleaned immediately before coating. 23. Method according to claim 19, characterized in that the holes are obtained by drilling. 24 . Multi-layer package of printed circuit boards, characterized in that it includes: a number of printed circuit board layers, each printed circuit board layer comprising a conductive circuit pattern embedded in and integral with an insulating material substrate, where the surface of the conductive circuit pattern is exposed along a surface of the substrate and lies flush and level with the substrate surface, a layer of insulating material arranged between each printed circuit board layer, wherein the insulating material layer is integrally formed and bonded to adjacent surfaces of said printed circuit board layer, whereby the bonded layers form a uniform homo gene structure with a number of conductive circuit patterns embedded in and integrally formed in the package. 25 . Multi-layer package according to claim 24r characterized in that the insulation material and the substrate in the printed circuit boards comprise the same insulation material. 26. Fine-line high-density printed circuit board, characterized in that it comprises: an insulating material substrate, and a conductive circuit pattern embedded in and integral with the insulating material substrate whereby the surface of the conductive circuit pattern is exposed along a surface of the substrate whereby the conductive circuit pattern is flush and planar with the substrate surface. 27. Printed circuit board according to claim 26, characterized in that said embedded conductive circuit pattern comprises conductive lines of essentially rectangular cross-section, the parallel sidewalls of the conductors being perpendicular to the substrate surface. 28. The printed circuit board according to claim 26', characterized in that the insulator material substrate comprises a dielectric laminate material.