EP0103627A4

EP0103627A4 - A method and apparatus for manufacturing multi-layer circuit boards.

Info

Publication number: EP0103627A4
Application number: EP19830901286
Authority: EP
Inventors: Peter P Pelligrino
Original assignee: Economics Laboratory Inc
Current assignee: Ecolab Inc
Priority date: 1982-03-04
Filing date: 1983-03-04
Publication date: 1985-09-18
Also published as: CA1222574A; IT8319877A1; IN158376B; EP0103627A1; WO1983003065A1; IT1163136B; JPS59500341A; DK502783D0; DK502783A; NO834009L; IT8319877A0

Abstract

Methods and apparatus (48) for providing fine line, high density multiple layer printed circuit board packages (44). In the method for fabricating multiple layer printed circuit board package (44), a printed circuit board (42) is formed having a conductive circuit pattern (18) embedded in and integral with an insulator material substrate (32), such that the surface of the conductive circuit pattern is exposed along one surface (34) of the substrate, and lays flush and coplanar therewith. At least two of said boards (42) are stacked with a layer of insulator material (44) interposed between each pair of adjacent boards (42). The entire assembly is heat-pressed together to form a homogeneous block of insulator material having conductive circuit patterns embedded and integrally molded therein.

Description

I

A METHOD AND APPARATUS FOR MANUFACTURING MULTI-LAYER CIRCUIT BOARDS

Background of the Invention This invention relates to a method for manufac- turing dense, fine line printed circuit boards and multiple layer printed circuit board packages.

There are many methods of manufacturing printed circuit boards used extensively throughout the elec¬ tronics industry. The advent of very large scale integrated circuits ("VLSI") has created an ever in¬ creasing demand for higher component density per unit of printed circuit board area. To meet this growing demand, printed circuit boards must be fabricated having extremely narrow conductor line widths and spacings. Becuase of the limitations inherent in the prior art methods, they cannot successfully meet the industry demands for high yield, multilayer printed circuit boards possessing good dimensional stability and ever-smaller line widths and spacings. Although there are many methods known and used in the fabrication of printed circuit boards, the most widely accepted methods employ an etching technique. Typically, these methods include the steps of cladding a base of an electrically insulating material with a conductive copper foil, placing a photoresist material in intimate contact therewith, developing the photo¬ resist material to define a conductive circuit pattern thereon, and etching away any_. exposed foil which is not covered with photoresist to provide a raised conductive circuit pattern.

This prior art method creates several problems.

Since the conductor patterns are not flush with the surface of the circuit board, a conductor line can be easily scratched during handling, resulting in an open circuit. Also, the copper conductor may sliver and bridge across adjacent conductors, causing short circuits.

Furthermore, the etching step in the prior art method may also create a variety of irregularities and defects in the printed circuitry. Etching may result in a conductor being over-etched near its base, thereby undercutting the conductor causing a nonuniform, mush¬ room-shaped cross-section. Also, photoresist may become trapped beneath the mushroom ledges, preventing foil hidden beneath the trapped photoresist from being etched away. Over-etching, therefore, makes fine line stability and line width control extremely difficult to achieve as line and spacing widths and tolerances grow smaller. Thus, etching fabrication methods can result in multiple conductor line defects, significantly reducing board yields, with a consequent upsurge in rejected printed circuitry which increases final pro¬ duction costs.

Board flatness and dimensional stability are important characteristics for insuring that printed circuitry maintains continuous conductive intercon¬ nection with component leads and adjacent boards. However, temperature and pressure fluctuations that occur during lamination cause the board to warp, causing considerable stresses to develop in circuitry mounted on equipment rails. These stresses cause conductors to break and/or to "swim" off the substrate fabricated by prior art methods because they have poor ductility and do not lay flush with the circuit board.

Quality and stability of multiple layer circuit board packages is also limited by prior. art fabrication methods. To make such packages, lamination bonding between layers of insulation must be sandwiched between circuit board layers to fill voids between the raised conductor lines and the circuit board substrate. Filling the voids requires high pressures during the lamination process which can destructively distort the conductor lines. Also, even very high pressures cannot insure that the laminate will fill all of the voids, ultimately, many voids may remain within the finished multilayered package which become depositories of impurities. Such impurities can cause electrical _c shorts. Further, the lamination bonding layers and board substrates may be of different material composi¬ tion since they are often supplied by different manu¬ facturers, may be made of different resins, or come from differnt manufacturing runs. Consequently, the finished -._Q multilayer package is not homogeneous. Lack of homoge¬ neity makes it difficult to set proper drill speeds, and drill angles in the fabrication of holes through the multilayers. In some cases the drill speed will be too fast to cut through the copper, causing it to tear, but •_j_5 will be the proper speed to cut through the insulation. Thus, some of the layers will have tears and others will be smooth, and some will be extremely uneven, contributing to degraded board quality while increasing unit cost. _Q Achieving high density in printed circuitry also requires that a uniform, continuous conductive coating be placed on small diameter holes that are drilled through multilayer packages for component leads and interconnects. One technique widely known in the art 5 for making hole walls conductive is electroless plating, whereby an electroless metal deposit, usually of copper, is uniformly coated on the dielectric board substrate. This technique has the disadvantage of depositing a coating that has poor adhesion qualities so that addi- _Q tional steps to insure adequate adhesion are required. Another technique is the application of a thin electro¬ less coating to the hole wall, then electroplating to further build up the conductive surface. Conventional electroplating techniques, however, cannot access holes 5 having small diameters and large depths demanded by fine line, high density printed circuitry. Therefore the - 4 - prior art teaches coating very small diameter holes, such as .0115 or less totally by electroless processing, which takes a substantial amount of processing time - 24 hours or more.

Summary of the Invention The present invention is a method of manufacturing fine line, high density printed circuit boards and printed circuit board pcakages. A flash layer of conductive material, preferably copper, is electrode- posited onto a rigid metal or metallized substrate that has a low coefficient of thermal expansion. A thick¬ ness of photosensitive resist is deposited onto the first layer by silkscreening or other methods known in the art. A mask is placed over the resist to define a conductive circuit pattern on the surface of the resist. The mask is exposed to light, and the resist is devel¬ oped. Channels having straight and parallel walls of resist will be formed defining the conductive circuit pattern duplicating the photomask thereby exposing the flash layer. A second layer of conductive material is built up on the physically exposed portions of the flash layer of conductive material within the channels, forming a raised conductive circuit pattern having a thickness not exceeding the depth of the channels. The remaining photosensitive resist is then removed from the flash layer.

The flash layer and the second layer defining a raised conductive circuit pattern are completely covered with a uniform layer of insulator laminate material. Pressure is applied to fully embed the raised conduc¬ tors in the insular material, such that the flash layer of conductive material remains in intimate and contin¬ uous contact with the insulator material.

The flash layer, integrated with the raised conduc- tive circuit pattern and the insulator material, is separated from the rigid substrate. The flash conduc-

OMP tive layer is then etched away, so that the conductive circuit pattern embedded in the insulator material is exposed as laying flush and coplanar with^* the surface of the insulator material. Printed circuit boards may be formed having embed¬ ded conductors exposed on a single side. However, a double sided board may be fabricated if desired, by heat pressing two such printed circuit boards together, back to back or by embedding the conductors on both sides of a single board.

The completed circuit boards are stacked with a layer of insulator laminate bonding material interposed between each printed circuit board layer. The multiple layers of printed circuitry and interposed insulator material are heat-pressed together to form a homogeneous package of insulator material with conductive circuit patterns embedded therein.

To prepare the boards for components and inter¬ connects, holes'^" are drilled through the homogeneous package. The holes are coated with a thin layer of conductive material, preferably copper, using an elec¬ troless coating method so as to provide a conductive substrate for electrodepositing additional conductive material thereon. Using a high impingement speed electrodepositing apparatus, a continuous and uniform thickness of conductive maerial is plated onto the walls of the holes.

A primary object of this invention is to provide a method for manufacturing fine line, high density printed circuitry whereby the conductive circuit pattern lays flush and aligned with its insulative substrate.

It is a further object of this invention to pro¬ vide a method for manufacturing fine line, high density printed circuitry whereby the conductor lines have improved ductility characteristics.

It is a further object of this invention to provide a method for manufacturing fine line, high density

OMPI - 6 - printed circuitry that has improved dimesional stability.

It is a further object of this invention to provide a method for manufacturing fine line, high density printed circuitry whereby the conductive circuits have a uniform width along its cross-section.

It is a further object of this invention to provide a method for manufacturing fine line, high density multiple later printed circuit board packages of uniform insulator material which have flat, stable, warp-free, and void-free characteristics.

It is still a further object of this invention to provide a method for fabricating fine line, high density printed circuit board packages having smal diameter through-holes of uniform and continuous conductive wall thickness.

Other objects of this invention will become more apparent upon a reading of the following description togther with the accompanying drawing, in which like reference numerals refer to like parts throughout and in which:

Brief Description of the Drawings Figure 1 is a side view of a substrate with a flash layer deposited thereon.

Figure 2 is a side view of the substrate in Figure 1, having a layer of photoresist deposited thereon. Figure 3 is a perspective view of the assembly in Figure 2 with a photomask aligned thereon.

Figure 4 is a perspective view taken along line 4-4 of Figure 3 illustrating rectangular channels defining a conductive circuit pattern developed in the photoresist layer after the photomask is removed.

Figure 5 is a side view of raised conductor lines deposited within the photoresist channels onto the flash layer taken along 4-4 of Figure 3. Figure 6 is a perspective view of the raised conductive circuit pattern pf Figure 5 after the remain¬ ing photoresist is removed. Figure 7 is a view taken along line 4-4 of Figure 3 showing an insulator laminate layer covering the raised conductive circuit pattern and flash layer of Figure 6. Figure 8 is a view taken along line 4-4 of Figure 3 showing the assembly of Figure 7 removed from the rigid substrate.

Figure 9 is a top plan view of the printed circuit board assembly of Figure 8 with the flash layer etched away thereby exposing the conductive circuit pattern embedded in and aligned flush with the insulator lami¬ nate.

Figure 10 is a cross-section of the printed circuit board assembly taken along lines 9-9 of Figure 9. Figure 11 is a side view of a printed circuit board assembly with registration holes drilled therethrough. Figure 12 is a perspective cross-sectional view illustrating multiple printed circuit boards and insula¬ tor laminate layers interposed therebetween stacked upon a conventional press.

Figure 13 is a perspective view illustrating a homogeneous multi-layer printed circuit board package of the present invention.

Figure 14 is a partial perspective v ew illustra- ting electrodeposited and electroless plating layers built up on an interconnect or lead hole of the present invention.

Description of the Preferred Embodiment

Referring first to Figure 1, a substrate 10 is comprised of a material such as stainless steel having a metallized surface for receiving a flash layer of electrodeposited material. The substrate is comprised of a rigid metal or a metallized plate. However, many other rigid material compositions having suitable characteristics may be used, such as a metallized glass material, for example, metallized Pyrex, having a very low coefficient of thermal expansion. The substrate - 8 - must have a low coefficient of thermal expansion to insure that when a conductor is placed thereon, it will not shift or float from its design positions due to the thermal expansion of the substrate caused during a subsequent pressing step.

A flash of electrically conducting material 12, preferably copper, is electroplated onto the substrate 10. The copper flash 12 serves as a base layer upon which further electroplating of conductor lines may be applied. It also serves as a releasing material for separating the printed circuitry from the stainless steel substrate 10 after formation of the printed circuit board is complete, as will be described in detail hereinbelow. The flash layer is as thin as can be since heat transfer characteristics of a very thin layer tend to rapid heat dissipation during heating, causing improved conductor line stability. Consequently, a flash layer of only .0001" to .0002" is deposited onto the substrate in the preferred embodiment. Furthermore, a very thin layer is less wasteful of copper. The thin electro¬ plated coating is achieved by utilizing an electropla¬ ting apparatus commpnly known as a high impingement speed plating apparatus, such as is taught in United States Patent Number 4,174,261 known as RISP, available from Economics Laboratory, Inc. Osborn Building, St. Paul, Minnesota, 55102. Alternatively, any conventional electroplating apparatus may be used for applying the copper flash to the substrate. However, a conventional electroplating apparatus cannot plate the extremely thin coating "contemplated in the present invention without causng pinholes and other imperfections, and therefore is not preferred.

A low contact pressure is desired at the interface between the flash layer and the substrate to facilitate separating the flash layer from the substrate. Low contact pressure may be accomplshed by using dissimilar materials for the flash and for the substrate, such as,^' but not limited to, using a copper flash with a stain¬ less steel substrate as in the preferred embodiment. Alternatively, materials having similar surfaces may be used if either material is coated with an impurity for reducing adhesion at their interface.

In the preferred method of the invention, the printed circuitry may be fabricated on one side of the stainless steel substrate, but for multilayer applica- tions may be fabricated on both sides of the substrate. This facilitates maximum production output, and allows optimal utilization of electroplating and other appara¬ tus used in the method.

Referring generally to Figures 2 through 5, a layer of photosensitive resist material 14, such as Dryfilm, manufactured by Dupont, is applied to the copper flash surface 12 of the substrate 10 using techniques well known in the art. The photoresist will be either positive, such that it. dissolves when exposed to light, or negative, i.e., it will not dissolve when exposed to light. A photomask 16 defining a conductive circuit pattern 18, is placed on top of the photoresist layer 14, by techniques widely known in the art. The photo¬ mask 16 is aligned and brought into continuous contact with the surface of the photoresist 14 to insure a high resolution of the conductive circuit pattern on the surface of the photoresist 14. The photomask masks the surface of the photoresist such that when it is exposed to light only the areas in which the conductors are to be defined are left exposed.

After the- photomask 16 is exposed to light, it is removed, and the photoresist 14 is developed using a commercially available developer such as Resist Stripper manufactured by Dupont. As a result, cavities 20 are formed in the areas where the photoresist 14 dissolved exposing the copper flash 12 previously covered by said photoresist 14 in a defined conductive circuit pattern - 10 - 18. The cavities' walls 18 are parallel to each other and perpendicular to the substrate 10, amounting to essentially rectangular channels running throughout the remaining undissolved photoresist 14 according to the original conductive circuit pattern 18 defined by the photomask 16.

The entire assembly is placed in a high impingement speed plating apparatus which in the preferred method is the RISP apparatus manufactured by Economics Laboratory, Inc., St. Paul, Minnesota. A conductive material 26, such as copper, is electrodeposited onto the exposed copper flash 19 at the bottom of the rectangular chan¬ nels 20, rather than utilizing the subtractive etching method as taught in the prior art. The electrodeposited material 26 is accumulated within the channels to a desired thickness of about 1.2 to about 15 mils (1.2 mils thickness of copper per sq. ft. to 15 mil thickness of copper per sq. ft.), the thickness being selected to prevent mushrooming of the electrodeposited material as happened in the prior art. At no time, however, should the thickness exceed the depth of the channels. The additive electroplating step produces conductor lines 28 having straight and perpendicular walls of uniform cross-sectional width, facilitating fine line resolu- tion, and making it possible to easily control line widths and densities of extremely narrow dimension. The use of the RISP apparatus enables the conductor lines to be plated with speed and uniformity that is considerably better than can be achieved with conventional electro- plating techniques. Additionally, rapid impingement speed electroplating produces, a very ductile conductor which is critical in preventing defects and failures in very narrow cross-sectioned conductor lines.

Referring generally to Figures 6 through 8, the photoresist layer 14 is chemically stripped away from the copper flash surface 12 exposing the raised electro¬ plated conductive circuit pattern 18. A layer of

O insulating material 30, such as epoxy coated fiberglass, is laminated to the copper flash^" layer 12 completely covering • the copper flash 12 and the raised conductive circuit pattern 18. Thermosetting insulator materials such as epoxy coated fiberglass are utilized because of their low cost and good temperature characteristics. If epoxy coated fiberglass is not used, alternative mate¬ rials, such as polypropylene, phenolics, or Teflon material manufactured by Dupont may be used. The insulating layer 32 is laminated over the conductive circuit pattern and the copper flash layer 12 by the application of heat and pressure as required for laminate material chosen, accomplished with a rigid pattern laminating press such as manufactured by Pasa- dena Hydraulic of El Monte, California. When epoxy coated fiberglass is used this lamination step can be performed at a pressure of approximately 50-250 pounds per square inch depending on the weave of the glass fabric (thicker -glass requires more pressure to set the epoxy into the weave) and at a temperature of approxi¬ mately 425 degrees Fahrenheit. The insulating material 32 will thereby flow and completely 'fill all the voids between the raised conductor lines and wil also achieve a strong bond with the conductors. The insulator material 32 should be of uniform thickness so that the conductor lines of the circuit pattern 38 will be completely covered by the insulator material.

The insulator material 32, in which the conductive circuit pattern 18 is molded and embedded and which is bonded to the copper flash layer 12, is manually separa¬ ted from the surface of the substrate 18.. The copper flash layer 12 is then removed from the insulator material 32 using conventional etching techniques or a rapid impingements speed etching apparatus, thereby exposing the conductive circuit pattern 18 embedded in the insulator material. Figures 9 and 10 show the resulting printed circuit board. As illustrated in

OMPI - 12 - Figure 10, the conductive circuit pattern 18 lays flush with the surface 34 of the insulator material 32, having no abutting, edges or protruding surfaces. Thus, the conductive circuit pattern is totally restricted and cannot move. This contrasts with the floating or shifting tendencies that commonly plague printed circui¬ try which have been fabricated using prior art methods, having the conductive circuit patterns raised above an insulator- material base. The embedded condutor config- uration that results from the present inventive method provides a durable and highly stable assembly, enabling large continuous sheets of printed circuitry to be manufactured at extremely close tolerances.

The oxide created on the copper conductors does not bond well to the insulation material. Therefore, the whole board 36 of the conductive circuit pattern 18 is immersed in a chemical bath, such as commercially available under the trademark Macublack from McDermott of Waterbury, Connecticut. * The chemical coating i - proves the adhesion qualities of the laminate, further insuring that, if the board is stacked, the copper surface of one board will adhere to the laminate surface of an adjacent board. This is particularly important for boards with surfaces exposing mostly copper and thus very little laminate, such as in ground and power boards.

At this stage of the invented process, a single layer of printed circuitry is complete. Having manu¬ factured printed circuitry with the desired conductor patterns, multiple layer printed circuit packages may be fabricted. A layer of insulator material 44 is sand¬ wiched between each layer of printed circuitry 42. This insulator material 44 is of the same composition as that used in the laminate structure of the printed circuitry. Thus, a multiplicity of printed circuit board layers are stacked atop one another, with interposed layers of insulator material 44 sandwiched therebetween. Referring generally to Figures 11 through 13, registration holes 38 are drilled through each printed circuit board 42 and insulation layer 44 that will be included in the multiple layer prnted circuit package. An optically guided sighting system, such as that made by Sportonics, of Rockford, Illinois sites the target at which the hole should be made and then drills through the targets such that there is one hole per target. The registration holes 38 provide mounting means for stack- ing the printed circuit boards and insulation layers 44 on mounting posts 46 so that the multiple layers of printed circuitry will align securely between a pair of pressure plates 48. •

The multiple printed circuit board layers 42, with insulator material 50 sandwiched therebetween, are pressed together between the pair of pressure plates 48 in a conventional press at a temperature of 375 to 425 degrees Fahrenheit at a pressure of approximately 250 pounds per square inch. However, in the "preferred embodiment, when 50 psi is used to press a single layer, the same pressure will be used throughout the process. Prior art multiple printed circuit packages often have layers that use insulator materials of different composition, or made in different manufacturing runs. Fabricating multiple-layer printed circuit board pack¬ ages in accordance with the present method, however, enables the sandwiched insulator material layers, as well as the laminate base of the printed circuit board layers, to be composed of the same meterial. This results in a homogeneous and continuous material struc¬ ture when the layers -are heat-pressed together to form a multilayer printed circuit board package. Also, since the printed circuit board layers of the present method are flush, having no protrusions or indentations, fabrication of the multilayer package is accomplished without voids or other irregularities occurring in the package structure. Further, because the surface of each circuit board layer is flush, lower pressure may be used to form the multilayer package. The advantage of such low pressure is that warpage or distortion of the package is avoided during the pressing step. In the prior art, internal shifting and floating that results from the use of high pressure during the multilayer package fabrication step places significant limitations on the number of circuit board layers that could comprise a single multilayer package. In the present invention, the combination of developing a homogeneous insulator material in the package, along with eliminating voids through the use of flush printed circuitry, substantially increases^' the number of printed circuit board layers that can be pressed into a single package. The present method has been regularly prac¬ ticed on a maximum of 22 board layers, and on a maximum of 40 layers on a more limited basis. However, the method is not thereby limited_/ and it is possible that packages with even a greater number of boards may be fabricated using the inventive method.

Interconnect and component lead holes 52 are then drilled through the multilayer package .44 using conven¬ tional drilling means. The holes are generally between .0115 and .093 inches in diameter. The holes are then cleaned to remove drill smear using cleaning means well known in the art or by the rapid impingement speed plating apparatus.

As generally illustrated in Figure 13, a .000050 inch thickness of copper 56 is deposited on the hole walls 58 using a conventional electroless plating process. The copper deposit serves as a base ^'for providing sufficient conductivity to carry substantial current for electrolysis. It should be noted that if this copper layer is too thin, it will simply burn away due to the heat generated during electrolysis.

Once again, the holes are cleaned and rinsed to remove impurities and surface dirt. A thickness of

0 copper 60 is then added electrolytically using the rapid impingement speed plating apparatus, to build up the desired conductive coating thickness along the walls of the hole 58. It is critical to this step that rapid impingement speed plating be used since conventional electroplating means cannot access the long and narrow diameter holes to provide a good conductive coating. Further, the use of the rapid impingement speed elec¬ troplating apparatus provides a copper coating having improved ductility characteristics. Thus, thermal or other expansion along the vertical axis of the hole will not cause a break in the conductor surface which could interrupt current flow.

The present invention is capable of fabricating line conductor widths and spaces as narrow as 2 mils, package layers numbering 40 or more having through holes as small as 5 mils in diameter.

While certain embodiments of the present invention have been shown -and described above, it will be appre¬ ciated that the invention is not limited thereto. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit of the invention.

OMPI ^NAT1

Claims

- 16 - I CLAIM:

1. A method for fabricating a printed circuit board comprising steps of: embedding a raised conductive circuit pattern within a uniform layer of insulator material such that one surface of the conductive circuit pattern is exposed as laying flush and coplanar with the surface of the insulator material.

2. The method of Claim 1, wherein the step of fabricating the printed circuit board comprises the steps of: forming a raised conductive circuit pattern on a rigid substrate, embedding the raised conductive circuit pattern with a uniform thickness of insulator material, and separating the embedded conductive circuit from the rigid substrate.

3. The method of Claim 1 further comprising the step of: forming conductive holes through said circuit board for affixing circuit components.

4. A method for fabricating a printed circuit board comprising steps of: forming a first layer of a conductive material on a rigid substrate, depositing photosensitive resist onto the first layer of conductive material, masking the photosensitive resist, defining a conductive circuit pattern on the surface of the resist, exposing the masked photosensitive resist to light to dissolve portions of the resist according to the conductive circuit pattern wherein certain portions of the first layer of conductive material are exposed, forming a second layer of conductive material upon the exposed portions of the first layer of conductive material wherein a raised conductive circuit pattern is formed above the general plane of said first conductive

O layer, removing undissolved photosensitive resist from the first layer of conductive material, embedding the raised conductive circuit pattern on the first conductive layer with a uniform thickness of insulator material, separating the first conductive layer from the rigid substrate, removing the first conductive layer from the insulator material, whereby the conductive circuit pattern embedded in the insulator material is exposed as laying flush and coplanar with the surface of the insulator material.

5. The method of Claim 4 wherein said second layer of conductive material is electroplated on the first layer of conductive material.

6. The method of Claim 4, wherein the raised conductive pattern is embedded in the insulator material by lamination. - 7. The method of Claim 4, wherein the first layer of conductive material is electrodeposited on the rigid substrate.

8. The method of Claim 4, wherein the rigid substrate has a metallized surface and a low coefficient of thermal expansion.

9. The method of Claim 7, wherein the first layer of conductive material is electrodeposited on the rigid substrate utilizing a rapid impingement speed electro¬ plating apparatus. 10. The method of Claim 4, further comprising the steps of forming conductive holes through said printed circuit board for circuit components and board inter¬ connects.

11. The method of Claim 4 , further comprising the steps of: coating said holes with a thin layer of conductive material, and - 18 - forming a continuous conductive surface along the walls of said coated holes.

12. The method of Claim 10 wherein, said holes are formed by drilling. 13. The method of Claim 11, wherein said holes are coated using a thin electroless coating for providing a conductive substrate, and electrodepositing conductive material on the conductive substrate to form the contin¬ uous conductive surface along the walls of the coated holes.

14. The method of Claim 10 further comprising the step of cleaning the impurities from the conductive holes.

15. A method for fabricating multiple layer printed circuit board packages, comprising the steps of: fabricating a plurality of printed circuit board layers, wherein each layer is formed by embedding a conductive circuit pattern in an insulator material base such that the exposed surface of the pattern lays flush and coplanar wth the surface of the base, stacking a plurality of circuit board layers on top of each other, placing a layer of insulator material between each printed circuit board layer, bonding the stack of circuit boards and interposed layers of insulator material together to form a multiple layer printed circuit board package.

16. The method of Claim 15, wlierein fabricating each printed circuit board layer comprises the steps of: forming a first layer of conductive material on a rigid substrate, depositing a thickness of photosensitive resist onto a first layer of conductive material, masking said photosensitive resist to define a conductive circuit pattern on the surface of said photosensitive resist, exposing said masked photosensitive resist to light to dissolve portions of the resist according to the conductive circuit pattern wherein portions of the first layer of conductive material are exposed, forming a second layer of conductive material upon the exposed portions of said first layer of conductive material to from a- raised conductive circuit pattern, removing the undissolved photosensitive resist from the first layer of conductive material, embedding the raised conductive circuit pattern on the first conductive layer with a uniform thickness of insulator material, separating a first conductive layer from the rigid substrate, removing said first conductive layer to expose said conductive circuit pattern embedded in said insulator material layer, whereby said exposed circuit pattern lays flush and coplanar with the surface of said insulator material. 17. The method to Claim 15, wherein the step of forming a first layer of conductive material on a rigid substrate comprises the steps of electrodepositing a thin coating of conductive metal onto a rigid substrate having a metallized surface and a low coefficient of thermal expansion.

18. The method according to Claim 14, wherein the step of forming a second layer of conductive material comprises the step of electrodepositing said material to a thickness of 1.2 to 15 mils. 19. The method according to Claim 16, wherein: a rapid impingement speed electroplating apparatus is used to electrodeposit said second layer.

20. The method according to Claim 16, wherein: the embedding step comprises laminating said insulator material over said first and second conductive layers, and applying continuous uniform pressure and heat, thereby embedding said second conductive layer - 20 - into said insulator material.

21. The method according to Claim 16, wherein: the circuit boards and the interposed layers of insulator material are bonded together by applying continuous uniform pressure and heat to form a unitary homogeneous package of insulator material with said conductive circuit patterns embedded therein.

22. The method according to Claim 15 further comprising the additional step of: forming conductive holes through said package for circuit components and board interconnects.

23. The method according to Claim 15 further comprising the steps of: forming holes through the package, coating said holes with a thin layer of conductive material, and forming a continuous conductive surface along the walls of said coated holes.

24. The method according ^"to Claim 15 further comprising the steps of: forming holes through the package, drilling holes for circuit component electrical leads and board interconnects through said stack of printed circuit board layers and interposed layers of insulator material, using an electroless coating method for providing a conductive substrate for electrodepositing conductive material thereupon, and electrodepositing . conductive material on said conductive substrate.

25. The method according to Claim 23, further comprising the additional step executed immediately prior to coating said holes of cleaning said holes.

26. The method of Claim 22, wherein said holes are formed by drilling.

27. A multiple layer printed circuit board package comprising: a plurality of printed circuit board layers each printed circuit board comprising a conductive circuit pattern embedded in and integral with an insulator material substrate, wherein the surface of said conduc¬ tive circuit pattern is exposed along one surface of said substrate, and lays flush and coplanar with said substrate surface, a layer of. insulator material interposed between each printed circuit board layer wherein said insulator material layer being integrally formed and bonded to adjacent surfaces of said printed circuit board layers, whereby said bonded layers form a unitary homoge¬ neous structure having a plurality of conductive circuit patterns embedded and integrally formed therein.

28. A multiple layer printed circuit board package according to Claim 27, wherein said insulator material and said substrate of said printed circuit boards comprise the same insulator material.

29. A fine line, high density printed circuit board comprising: an insulator material substrate, and a conductive circuit pattern embedded in, and integral with, said insulator material substrate, the surface of said conductive circuit pattern being exposed along one surface of said substrate, said conductive circuit pattern laying flush and coplanar with said substrate surface.

30. A printed circuit board according to Claim 29, wherein: said embedded conductive circuit pattern comprises conductor lines of substantially rectangular cross- section, the parallel side walls of said conductor lines being perpendicular to the substrate surface.

31. The printed circuit board according to Claim 29, wherein: said insulator material substrate comprises a dielectric laminate material.

OMPI