NL8600770A - Werkwijze voor het vervaardigen van een halfgeleiderinrichting. - Google Patents

Werkwijze voor het vervaardigen van een halfgeleiderinrichting. Download PDF

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Publication number
NL8600770A
NL8600770A NL8600770A NL8600770A NL8600770A NL 8600770 A NL8600770 A NL 8600770A NL 8600770 A NL8600770 A NL 8600770A NL 8600770 A NL8600770 A NL 8600770A NL 8600770 A NL8600770 A NL 8600770A
Authority
NL
Netherlands
Prior art keywords
opening
electrode
zone
layer
electrode zone
Prior art date
Application number
NL8600770A
Other languages
English (en)
Dutch (nl)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Priority to NL8600770A priority Critical patent/NL8600770A/nl
Priority to DE8787200372T priority patent/DE3779802T2/de
Priority to EP87200372A priority patent/EP0243988B1/de
Priority to US07/025,554 priority patent/US4859630A/en
Priority to CA000532338A priority patent/CA1298000C/en
Priority to JP62070515A priority patent/JPS62242354A/ja
Publication of NL8600770A publication Critical patent/NL8600770A/nl

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
NL8600770A 1986-03-26 1986-03-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting. NL8600770A (nl)

Priority Applications (6)

Application Number Priority Date Filing Date Title
NL8600770A NL8600770A (nl) 1986-03-26 1986-03-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
DE8787200372T DE3779802T2 (de) 1986-03-26 1987-03-02 Verfahren zur herstellung einer halbleiteranordnung.
EP87200372A EP0243988B1 (de) 1986-03-26 1987-03-02 Verfahren zur Herstellung einer Halbleiteranordnung
US07/025,554 US4859630A (en) 1986-03-26 1987-03-13 Method of manufacturing a semiconductor device
CA000532338A CA1298000C (en) 1986-03-26 1987-03-18 Method of making a semiconductor device comprising contacting through an opening of reduced size
JP62070515A JPS62242354A (ja) 1986-03-26 1987-03-26 集積回路の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8600770A NL8600770A (nl) 1986-03-26 1986-03-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
NL8600770 1986-03-26

Publications (1)

Publication Number Publication Date
NL8600770A true NL8600770A (nl) 1987-10-16

Family

ID=19847772

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8600770A NL8600770A (nl) 1986-03-26 1986-03-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.

Country Status (6)

Country Link
US (1) US4859630A (de)
EP (1) EP0243988B1 (de)
JP (1) JPS62242354A (de)
CA (1) CA1298000C (de)
DE (1) DE3779802T2 (de)
NL (1) NL8600770A (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE461428B (sv) * 1988-06-16 1990-02-12 Ericsson Telefon Ab L M Foerfarande foer att paa ett underlag av halvledarmaterial framstaella en bipolaer transistor eller en bipolaer transistor och en faelteffekttransistor eller en bipolaer transistor och en faelteffekttransistor med en komplementaer faelteffekttransistor och anordningar framstaellda enligt foerfarandena
JPH02291150A (ja) * 1989-04-28 1990-11-30 Hitachi Ltd 半導体装置
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
US5268314A (en) * 1990-01-16 1993-12-07 Philips Electronics North America Corp. Method of forming a self-aligned bipolar transistor
KR940001402B1 (ko) * 1991-04-10 1994-02-21 삼성전자 주식회사 골드구조를 가지는 반도체소자의 제조방법
GB9219268D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Semiconductor device incorporating a contact and manufacture thereof
US5416031A (en) * 1992-09-30 1995-05-16 Sony Corporation Method of producing Bi-CMOS transistors
US5459083A (en) * 1993-03-01 1995-10-17 Motorola, Inc. Method for making BIMOS device having a bipolar transistor and a MOS triggering transistor
US5619072A (en) * 1995-02-09 1997-04-08 Advanced Micro Devices, Inc. High density multi-level metallization and interconnection structure
US6281562B1 (en) * 1995-07-27 2001-08-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device which reduces the minimum distance requirements between active areas
US6124189A (en) * 1997-03-14 2000-09-26 Kabushiki Kaisha Toshiba Metallization structure and method for a semiconductor device
KR100290903B1 (ko) * 1998-02-25 2001-06-01 김영환 반도체소자 및 이의 제조방법
KR100275962B1 (ko) 1998-12-30 2001-02-01 김영환 반도체장치 및 그의 제조방법_
US7629210B2 (en) 2000-05-15 2009-12-08 Nec Corporation Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction
US20010043449A1 (en) 2000-05-15 2001-11-22 Nec Corporation ESD protection apparatus and method for fabricating the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU499808B1 (en) * 1978-05-18 1979-05-03 Ypsilantis, John Alphanumeric display
JPS567463A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor device and its manufacture
US4346512A (en) * 1980-05-05 1982-08-31 Raytheon Company Integrated circuit manufacturing method
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
JPS5775453A (en) * 1980-10-29 1982-05-12 Fujitsu Ltd Semiconductor device and manufacture thereof
DE3205022A1 (de) * 1981-02-14 1982-09-16 Mitsubishi Denki K.K., Tokyo Verfahren zum herstellen einer integrierten halbleiterschaltung
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material

Also Published As

Publication number Publication date
CA1298000C (en) 1992-03-24
EP0243988B1 (de) 1992-06-17
EP0243988A1 (de) 1987-11-04
JPH0529147B2 (de) 1993-04-28
US4859630A (en) 1989-08-22
JPS62242354A (ja) 1987-10-22
DE3779802T2 (de) 1993-01-14
DE3779802D1 (de) 1992-07-23

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Legal Events

Date Code Title Description
A1B A search report has been drawn up
BV The patent application has lapsed