NL8202913A - Besturingsvolgordeketen voor een emulator. - Google Patents

Besturingsvolgordeketen voor een emulator. Download PDF

Info

Publication number
NL8202913A
NL8202913A NL8202913A NL8202913A NL8202913A NL 8202913 A NL8202913 A NL 8202913A NL 8202913 A NL8202913 A NL 8202913A NL 8202913 A NL8202913 A NL 8202913A NL 8202913 A NL8202913 A NL 8202913A
Authority
NL
Netherlands
Prior art keywords
emulator
control sequence
sequence circuit
decoding
circuit according
Prior art date
Application number
NL8202913A
Other languages
English (en)
Dutch (nl)
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of NL8202913A publication Critical patent/NL8202913A/nl

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
NL8202913A 1981-07-30 1982-07-20 Besturingsvolgordeketen voor een emulator. NL8202913A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28825581 1981-07-30
US06/288,255 US4447876A (en) 1981-07-30 1981-07-30 Emulator control sequencer

Publications (1)

Publication Number Publication Date
NL8202913A true NL8202913A (nl) 1983-02-16

Family

ID=23106381

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8202913A NL8202913A (nl) 1981-07-30 1982-07-20 Besturingsvolgordeketen voor een emulator.

Country Status (4)

Country Link
US (1) US4447876A (fi)
JP (1) JPS5819961A (fi)
DE (1) DE3228405A1 (fi)
NL (1) NL8202913A (fi)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8413933D0 (en) * 1984-05-31 1984-07-04 Columbia Automation Ltd Emulating timing characteristics of microprocessor
JPS60152962A (ja) * 1984-01-20 1985-08-12 Yokogawa Hokushin Electric Corp デ−タバストレ−サ
JPS61210437A (ja) * 1985-03-14 1986-09-18 Ando Electric Co Ltd インサ−キツト・エミユレ−タの制御方法
JPS6226561A (ja) * 1985-07-26 1987-02-04 Toshiba Corp パ−ソナルコンピユ−タ
JPH0727471B2 (ja) * 1985-08-01 1995-03-29 日本電気株式会社 マイクロコンピュータ開発装置
US4769558A (en) * 1986-07-09 1988-09-06 Eta Systems, Inc. Integrated circuit clock bus layout delay system
US5210832A (en) * 1986-10-14 1993-05-11 Amdahl Corporation Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle
JPS63192139A (ja) * 1987-02-04 1988-08-09 Yokogawa Electric Corp 実行バスサイクル検出装置
JPS64140U (fi) * 1987-06-22 1989-01-05
US4975869A (en) * 1987-08-06 1990-12-04 International Business Machines Corporation Fast emulator using slow processor
US4951195A (en) * 1988-02-01 1990-08-21 International Business Machines Corporation Condition code graph analysis for simulating a CPU processor
JPH0235524A (ja) * 1988-03-14 1990-02-06 Advanced Micro Devicds Inc バスコンパチブルプログラマブルシーケンサ
US5596331A (en) * 1988-05-13 1997-01-21 Lockheed Martin Corporation Real-time control sequencer with state matrix logic
US5202976A (en) * 1988-12-30 1993-04-13 Hewlett-Packard Company Method and apparatus for coordinating measurement activity upon a plurality of emulators
US5093776A (en) * 1989-06-15 1992-03-03 Wang Laboratories, Inc. Information processing system emulation apparatus and method
US5077657A (en) * 1989-06-15 1991-12-31 Unisys Emulator Assist unit which forms addresses of user instruction operands in response to emulator assist unit commands from host processor
DE4042263A1 (de) * 1990-12-31 1992-07-02 Richt Stefan Verfahren zu erkennung des interruptstatus eines mikroprozessors
US5537624A (en) * 1991-02-12 1996-07-16 The United States Of America As Represented By The Secretary Of The Navy Data repacking circuit having toggle buffer for transferring digital data from P1Q1 bus width to P2Q2 bus width
JPH04350737A (ja) * 1991-05-29 1992-12-04 Nec Corp マイクロコンピュータ
US5687312A (en) * 1993-07-30 1997-11-11 Texas Instruments Incorporated Method and apparatus for processor emulation
US5835960A (en) * 1994-01-07 1998-11-10 Cirrus Logic, Inc. Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus
US5579263A (en) * 1994-12-22 1996-11-26 Sgs-Thomson Microelectronics, Inc. Post-fabrication selectable registered and non-registered memory
JPH10254738A (ja) * 1997-03-12 1998-09-25 Mitsubishi Electric Corp エミュレータ装置及びエミュレーション方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4050058A (en) * 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
US4210960A (en) * 1977-09-02 1980-07-01 Sperry Corporation Digital computer with overlapped operation utilizing conditional control to minimize time losses
JPS54114687A (en) * 1978-02-27 1979-09-06 Toyoda Mach Works Ltd Sequence controller

Also Published As

Publication number Publication date
JPS5819961A (ja) 1983-02-05
JPS6246895B2 (fi) 1987-10-05
US4447876A (en) 1984-05-08
DE3228405A1 (de) 1983-02-17
DE3228405C2 (fi) 1987-01-29

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Legal Events

Date Code Title Description
BT A document has been added to the application laid open to public inspection
A85 Still pending on 85-01-01
BV The patent application has lapsed