NL8006770A - FIELD TRANSISTOR IN THE FORM OF A THIN FOIL. - Google Patents

Description

VO 1301

Transistor with field action in the form of a thin film.

The invention relates to a transistor with a field action in the form of a thin film, and more particularly to a transistor with a field action in the form of a thin film, formed of an amorphous alloy, which contains at least silicon and fluorine.

In this regard, reference is made to U.S. Patents 4,217,374 and 4,226,898.

Silipium is the foundation for the massive crystalline semiconductor industry, and is the material used in virtually all commercial integrated chains produced today. * 10 When crystalline semiconductor technology reached a commercial state, it became the foundation for today's massive industry for the manufacture of semiconductor devices. This was due to the ability of the naturally-learned to grow substantially error-free germanium, and in particular silicon crystals, and then to change them into additional materials with areas therein having a p and n conductivity. This was accomplished by diffusing into such crystalline material parts per million of giving (n) or receiving (p) stimulation materials, which were introduced as substitute impurities into the substantially pure crystalline materials to enhance their electrical conductivity and for controlling the p or n conductivity thereof.

The semiconductor manufacturing methods for making p-n junction crystals involve extremely complicated, time-consuming and expensive operations, as well as high processing temperatures.

Thus, such crystalline materials used in transistors and other current controllers are produced under very precisely controlled conditions by growing individual single silicon or germanium crystals, and when pn-30 junctions are required by stimulating such and single 8006770-2 cell. crystals with extremely small and critical amounts of stimulants. Such crystal growth methods produce relatively small crystal disks on which the integrated circuits are formed.

In the scale-integration technology of such disks, the small area of the crystal disk limits the overall size of the integrated circuits that can be formed thereon. In applications requiring large-scale areas, such as in display technology, the crystal disks cannot be manufactured with the required or desired large areas.

The organs are formed at least in part by diffusing p- or n-stimulants into the substrate. Furthermore, each member is formed between insulating channels, which are diffused into the bottom layer. The packing density (the number of members per unit of surface area of the disk surface) is also limited on the silicon disks due to the leakage current in each member and the energy required to operate the members, both of which generate heat, which is undesirable. The silicon discs do not spread heat easily. The leakage current also adversely affects the life of the battery or the energy cell in portable applications.

In a MOS circuit, the switching speed is directly related to the gate length, the shortest length having the highest speed. The diffusion methods, photolithography and other crystalline manufacturing methods limit the shortness at which the gate length can be performed.

Furthermore, the packing density is extremely important because the cell size is exponentially related to the cost of each organ.

A reduction in die size with e.g. a factor of 2 results in a reduction in costs on the order of a factor 6.

In summary, crystal silicon transistor and integrated circuit parameters, which are not changeable as desired, require large amounts of material, high processing temperatures, whereby they can only be produced on discs with a relative 8006770 Λ. Λ - 3 - small Small area and in production Costly and time consuming. Organs based on amorphous silicon can overcome these drawbacks of crystal silicon. Amorphous silicon can be made faster, more easily, at lower temperatures and in larger areas than crystal silicon.

Accordingly, considerable effort has been made to develop methods for easily depositing amorphous semiconductor alloys or foils, each of which may comprise relatively large areas, if desired, limited only by the size of the deposition equipment, and which may be stimulated to form p ~ and n materials to form pn junction transistors and members, which are better in cost and / or performance than those produced by their crystalline counterparts. For many years this work was largely unproductive. Films of amorphous silicon or germanium (Group IV] are usually quadruple coordinated and found to have microcavities, as well as meandering bonds and other errors, which produce a high density of localized states in their energy gap. The presence of a high density of localized states in the energy gap of semiconductor films of amorphous silicon, such films could not be successfully stimulated or otherwise modified to shift the fermin level close to the conduction or valence bands, making them unsuitable for making of pn junctions for transistors and other current controller applications.

In an effort to minimize the aforementioned difficulties with amorphous silicon and germanium, WESpear and PGLs Comber of the "Carnegie Laboratory of Physios, 30 University of Dundee", in Dundee, Scotland, conducted research on "Substitutional Doping of Amorphous Silicon, "reported in a paper published in" Solid State Communications ", Vol.17, biz.1193 - 1196, 1975, with a view to reducing localized states in the energy gap in amorphous 35 silicon or germanium in order to make it approach more intrinsically crystalline q η n 7 7 π - u - silicon or germanium, and substitutionally stimulate the amorphous materials with appropriate conventional stimulants, such as in stimulating crystalline materials, to make them extrinsic and of a p or n conductivity.

The reduction of the localized states was accomplished by a glow discharge deposition of amorphous silicon films, in which a gaseous silane (CSiH 2) was passed through a reaction tube, in which the gas was decomposed by a high-frequency glow discharge and deposited on a substrate at a substrate temperature of about 500-800 ° K [227-327 ° C). The material thus deposited on the substrate was an intrinsically amorphous material consisting of silicon and hydrogen. To produce amorphous material, a gas of hydrogen phosphorus CPH (η for a π conductivity or a gas of diborane CB2Hg) for a p conductivity was premixed with the silane gas and passed through the glow discharge reaction tube under the same operating conditions.

The gaseous concentration of the stimulants used was -2 between about 5 x 10 and 10 parts by volume. The material thus deposited was believed to contain substituent phosphorus or boronum mulant and was found to be eccentric and of the n or p conductivity.

Although it was not known to these researchers, it has now become known through the work of others that the hydrogen in the silane combines at an optimum temperature with many of the wobbling bond of the silicon during glow deposition for significant reduce the density of the localized states in the energy gap in order to make the electronic properties of the amorphous material closer to that of the corresponding crystalline material.

D.I. Jones, W.E. Spear, P.G. LeComber, S.Li, and R. Martins also worked on preparing a Ge: H from GeH, using similar deposition techniques. The material obtained showed a high density of localized states in the 8006770 ♦ * -5 energy gap thereof. Although the material could be stimulated. its effectiveness was significantly reduced from that available with an Si: H. In this work, reported in "Philosophical Magazine Θ," 5 Vol. 39, p. 147 (1979), the authors concluded that, due to the high density of slit states, the material obtained "... is a less attractive material than a-Si for stimulation studies and potential applications."

The inclusion of hydrogen in the foregoing silane process 10 not only has limitations due to the fixed hydrogen to silicon ratio in silane, but different Si: H bonding shapes, which is very important, entail new anti-bonding states, which adversely affect can have in these materials. Therefore, there are basic limitations to reducing the density of localized states in these materials, which states are particularly harmful in terms of effective p-, as well as n-stimulating. The resulting density of states of the silane deposited materials leads to a narrow discharge width, which in turn limits the effectiveness of members whose operation depends on the flow of free carriers. The method of making these materials using only silicon and hydrogen also results in a high density due to surface conditions affecting all of the previous parameters.

After the development of the glow discharge deposition of silicon from silane gas, research was conducted on the sputter deposition of amorphous silicon foils in the atmosphere of the mixture of argon (necessary for sputter deposition) and molecular hydrogen to achieve the effects. to determine such molecular hydrogen on the properties of the deposited amorphous silicon foil. This study indicated that the hydrogen acted as a leveling agent, which bound to reduce localized states in the energy gap. However, the extent to which the localized states in the energy gap were reduced upon deposition by sputter deposition was much less than achieved by the silane deposition described above. The p and n stimulation materials described above were also used in the cathode sputtering process to produce p and n stimulated materials.

These materials had a lower stimulation efficiency than the materials produced in the glow discharge method. Neither method efficiently produced p-stimulated materials with sufficiently high receiving electrode concentrations to produce commercial p-n junction organs. The n-stimulation efficiency was below desirable and acceptable commercial levels, and the p-stimulation was particularly undesirable as it increased the number of localized states in the band gap.

Various methods of manufacturing and constructing thin film transistors and members have been proposed, wherein the different films of the transistor are made of different materials with different electrical properties. Thin film existing transistors are e.g. proposed using nickel oxide films, silicon films, amorphous silicon films and amorphous silicon and hydrogen films formed from silane, as mentioned above. Various geometric shapes have also been proposed, such as a flat MOS construction.

The known deposition of amorphous silicon, which has been changed by hydrogen from the silane gas, in an attempt to make it more resemble crystalline silicon, and which has been stimulated in the manner of stimulating crystalline silicon, has properties which all important aspects are less than that of stimulated crystalline silicon. As reported by LeComber and Spear and others, as noted above, the op. silane-based transistor members, the leakage current is not more than 10 11 A, 6 the saturation current appears to be about 5 x 10 A, the 4 switching frequency of the member is about 10 Hz, and the stability is poor because the material with time decreases in quality.

It has been proposed to make a solar cell, which is in principle an 8006770-photosensitive rectifier, using an amorphous alloy containing silicon and fluorine, as disclosed in said U.S. Patents 4,217,374 and 4,275.S9Q.

In accordance with the invention, there is provided a thin film field-effect transistor having a source region, further from a drain region, of a gate insulator, of a thin film-deposited amorphous alloy containing at least silicon and fluorine and is coupled to the source region, the drain region and the gate insulator, and of a gate electrode in contact with the gate insulator.

The amorphous alloy preferably also contains hydrogen, such as an amorphous alloy a-Si: F,: H, wherein a is between 80 and 98 a D c atom%, b between 1 and 10 atom% and c 1 and 10 atom -%.

The field-effect transistor may have different geometries, such as a V-MOS structure, and may be deposited on different sublayers with an insulator between the active regions of the field-effect transistor in the form of a thin film. conductive base layer, such as a metal. The transistors can be deposited on an insulator, a semiconductor, an insulated metal or an insulated semiconductor substrate. Due to the ability to be formed on different substrates and the small leakage and operating current, the transistors can also be formed on top of each other, i.e. stacked.

The field film transistor in the form of a thin film may have various desirable properties depending on the particular selected geometry and film thickness of the selected amorphous silicon / fluorine material, such as e.g. a saturation direct current of not more than 10 Å and up to or more than A10 Å, an upper cutoff frequency of at least more than 10 MHz, a high ratio of about 10 7 of the resistor when switched off.

condition to the resistance in the turned on state, and a very low leakage current of about 10 ^ A or less. Furthermore, the alloy does not deteriorate over time.

Accordingly, a first object of the invention is to provide a field-effect transistor member in the 8006770-8 shape of a thin film, which member includes a source region, further a drain region, a gate insulator and a gate electrode in contact with the gate insulator, which member is characterized by a thin film deposited amorphous alloy containing at least silicon 5 and fluorine coupled to the source region, lift drain region and the gate insulator.

A second object of the invention is to provide a field action transistor member in the form of a thin film, which member contains a source region, further a drain region, a gate insulator, a thin film deposited semiconductor alloy coupled to the source region, the drain area and the gate insulator, which member is characterized by a V-MOS construction.

The invention is further elucidated with reference to the drawing, in which: Fig. 1 is a vertical section of an embodiment provided with metal source and drain regions, similar to a flat MGS transistor

Figure 2 is a circuit diagram of the transistor shown in Figure 1; Fig. 3 is a vertical section of a second embodiment, comprising semiconductor source and drain regions;

Figure 4 is a circuit diagram of the transistor shown in Figure 3;

Fig. 5 is a vertical sectional view of another embodiment including metal source and drain regions similar to a V-MOS transistor;

Figure 6 is a circuit diagram of the transistor shown in Figure 5;

Figure 7 is a vertical section of an embodiment similar to the transistor shown in Figure 5, including semiconductor source and drain regions;

Figure 8 is a circuit diagram of the transistor shown in Figure 7; and

Fig. 9 is a vertical section of a transistor similar to the transistors shown in Figs. 1-35, but with a different geometrical construction.

Referring now in more detail to the drawing, FIG. a thin-film field-effect transistor 10 is shown. As shown, the transistor 10 is formed on a bottom layer 12 of insulating material, which may consist of a silicon material, a layer of polymer material, or an insulator on top of a metal. In accordance with the present teachings, a thin alloy layer 14 is deposited on the bottom layer 12, which contains silicon and fluorine, and which can also contain hydrogen, which layer can be stimulated to form an N or P alloy. On top of this blank ring layer 14 is a layer or tape 16 of insulating material, such as a field oxide, and spaced therebetween is another layer or tape 18 of insulating material, such as a field oxide.

A channel or opening 20 is biv. by conventional photo-15 lithographic techniques formed between the two bands 16 and 18.

A source metal conductor 22 is deposited over the belt 16, a portion of which is in contact with the alloy layer 14 to form a scrap resistance contact at the interface between the source metal 22 and the amorphous alloy layer 14.

In a similar manner, a drain metal conductor or layer 24 is deposited over the insulating tape 18, a portion of which is in contact with the alloy layer 14 spaced from the source metal 22. The interface between the drain metal 24 and the amorphous layer 14 provides another scrap metal contact. A gate 25 'insulator layer 26 of insulating material, such as a gate oxide or gate nitride 26, is deposited over the source metal 22 and the drain metal 24 and contacts the amorphous alloy layer 14 between the source and drain metal. A gate conductor 28, which may be made of any suitable metal, such as aluminum or molybdenum, is deposited on this layer 26 of gate insulating material. A further layer 30 of insulating material is deposited on the gate conductor to render the member passive, which material is referred to as a field oxide.

The insulating layers 16 and 30 are connected prior to the next adjacent transistor, source 22 being connected 8006770-10 bond with an external conductor. The insulating layer 16 forms the insulator for the next member, similar to the insulator 13 of the illustrated transistor 10.

The gate insulator layer 26 and the tapes 16 and 18 of insulating material, referred to as a field oxide, may be made of a metal oxide, silicon dioxide or other insulator, such as silicon nitride. The source metal 22 and drain metal 24 may be formed of any suitable conductive metal such as aluminum, molybdenum or a high activity metal such as gold, pal-10 ladium, platinum or chromium. The gate insulator can be a nitride, silicon dioxide or silicon nitride material.

In accordance with the present teaching, an alloy containing silicon and fluorine, which may also contain hydrogen, is used to form the amorphous alloy layer 14. This alloy provides the aforementioned desirable properties, which can be used for many different chains. The alloy layer 14 is preferably made of a-Sia:: Hc, wherein a is between 80 and 98 atomic%, b is between 1 and 10 atomic% and c is between 1 and 10 atomic%.

The alloy can be stimulated with a stimulant from Group V or Group III of the Periodic System in an amount of between 10 and 1000 parts per million (ppm).

The stimulation materials and the degree of stimulation can be different.

The thickness of the alloy layer 14 of amorphous material can be between 10 and 500 nm, the thickness used being about 100 nm. The source metal 22 and the drain metal 24 may also have thicknesses between 50 and 2000 nm, with an applied thickness being about 200 nm. Although, according to the description, the gate 3Q conductor 28 is made of metal, it may be made of Indian desirably, of a stimulated semiconductor material.

Depending on the geometry of the different layers and the thicknesses of the different layers, a field-acting transistor can be constructed in the manner described above, with the leakage current being about 10 A to provide 8 00 6 77 0 - 11 - of a high resistance when switched off and a saturation DC current of approximately 10 A.

When constructing the thin film field effect transistor 10 shown in FIG. 1, the material layers, and in particular the alloy layer 14, are deposited by various deposition techniques, preferably by glow discharge.

A typical gate CG], source (S) and drain CD] circuit diagram of the field-effect transistor 10 is shown in FIG. 2.

Referring now to FIG. 3, a planar constructed thin film field transistor 40 is shown, which like transistor 10 is formed on an insulated bottom layer 42. On top of the bottom layer material 42, e.g. An alloy layer 44, which contains silicon and fluorine and preferably also hydrogen, is deposited by glow discharge and may be of the N or F type. Two layers of insulating material 46 and 48 are made on this alloy layer 44, which are made of a field oxide and according to FIG. 3 with an opening 50 between them. Above the insulating layers 46 and 48, a source alloy layer 52 and a drain alloy layer 54 are deposited, which also contain silicon and fluorine, and preferably also hydrogen. The source 52 and the drain alloy 54 are amorphous N or P alloys. An N-P or P-N junction is then formed at the interface where layers 52 and 54 contact alloy layer 44.

After depositing layers 52 and 54, a gate insulator layer 56, referred to as a gate oxide 56, is deposited over the source region 52, the exposed portion of the amorphous layer 44 and the drain region 54. Then, a gate conductor 58 is deposited over the gate insulator 46, and a passivating insulating layer 60 is deposited on top of the gate conductor 58, which layer consists of a field oxide.

A typical gate (GJ, source CS) and drain CD] circuit diagram of transistor 40 is shown in Figure 4.

The difference between transistor 40 and transistor 10 is that the drain and source regions or conductors 52 and 54 of transistor 40 are made of a semiconductor material and preferably 8006770-12 of sen a-Si: F: H alloy.

In Fig. 5, a new V-MOS construction, shown as a field film transistor 70 in the form of thin films, manufactured in accordance with the present teachings is shown. First, a layer or strip of drain metal 74 is deposited on a substrate 72, where a center portion is cut or etched. On top of the discharge metal 74 is deposited a thin layer or band of amorphous alloy 76 in which a center portion is cut or etched in line with the cut portion of the layer 74. Similarly, a layer of source metal 78 is deposited on the layer 76 and a corresponding center portion thereof is cut away. Also, all layers can be etched in one step following the deposition of all layers.

Then, a gate insulator 80, referred to as a gate oxide, is deposited over the source metal 78 and in the resulting center space 82 in the form of a V-cut and on the beveled edges of the layer portions 74, 76 and 78 and over the exposed underlayer 72. Next, a gate conductor 84 is deposited on the gate insulator 82, and a layer 86 of insulating material, referred to as a field oxide, is deposited over the gate metal conductor 84 as a passivating layer.

This particular V-MOS construction with the open space 80 has the advantage that a very short distance L is established between the source metal 74 and the drain metal 78 through the alloy layer 76. The layer thickness or distance L has a results in a high operating frequency and a higher saturation current than the transistor 25 of Figures 1 and 3. The leakage current may increase relative to the shapes of Figures 1 and 3.

A typical gate (G), source (S3, and drain (D)) chain theme of the transistor 70 is shown in FIG. 6.

In FIG. 7, another V-MOS transistor 90 having a thin film field action, formed on a substrate 92, the alloy layers 94, 96, and 98 having silicon and fluorine CN or P type] is shown. are deposited on the bottom layer 92. The respective layers 94, 96 and 98 have a cut-away or etched center portion 100. Then, a gate insulator 102, referred to as a gate oxide, is deposited over the edge of the layer 98 and in contact with the 8006770 - T3 - exposed edges of the layers 94, 96 and 98 and also the exposed part of the bottom layer 92, as shown. A gate conductor 104 is deposited over the insulating layer 102, finally, a layer 106 of insulating material, such as a field oxide, is deposited over the gate conductor 104. The transistor 90 operates using the opposite biased PN junctions, formed between layers 94 and 96 and between 96 and 98.

The transistor 90 is similar to the transistor 70 as shown in FIG. 5 except that the source region 98 and drain 10 region 94 are made of a semiconductor alloy such as α-Si: F: H.

The V-MOS construction of transistors 70 and 90 is advantageously used with any semiconductor deposited material, such as e.g. but not exclusively a silicon alloy containing at least silane-deposited hydrogen.

A typical circuit diagram of transistor 90 is shown in Figure 8.

Referring now to Figure 9, another field-effect transistor 110 is made in accordance with the present teaching.

The transistor 110 is formed on a metal substrate 111 on which a thin layer of insulating material 112 is deposited, which separates the active components of the transistor 110 from the metal substrate 111 and yet is sufficiently thin that the heat generated in the transistor 110 is the metal substrate can flow, which forms a heat accumulator for this.

The thin film field effect transistor 110 is formed by depositing a source conductor layer 114 made of metal or an N or P semiconductor alloy. A drain conductor 116 is deposited on the insulating layer 112 and is also made of a metal or a PN semiconductor alloy. On top of the conductors 114 and 116, an intrinsic or slightly stimulated alloy layer 118 is deposited, such as the a-Si: F already described. : H alloy.

On top of the alloy layer 118 is deposited a gate insulator 120, which may consist of a silicon oxide or a silicon nitride.

On top of the gate insulator 120, a gate conductor layer 122 is deposited, 8006770 - HI - which may consist of a metal or semiconductor material. A passivating layer 124 is deposited over the gate conductor 122.

The different transistors IQ, 40, 70, 90 and 110 may be formed in a matrix, so that the source region or the drain region extends as a Y axis conductor over the deposited under layer 112. Then the drain or source region is deposited to form a separate drain or source region, which is then connected to an X axis guide. Then, the gate electrode is deposited so that it extends parallel to the Y axis to form a Y axis gate conductor. In this manner, the transistors 10, 50, 70, 90 and 110 with field action can be used in conjunction with PROM members to form the isolator in a memory r circuit therefor, which circuit includes a memory region and the isolator.

The present field film transistor in the form of thin films and the various embodiments thereof, as described, provide a transistor which is very small and yet has very good operating properties, as mentioned above. The. the top insulating layer of the transistors, such as 124 in FIG. 9, can be used to form the insulating layer for another transistor to be formed thereon to provide a stacked transistor shape, and thus further increase the packing density of the members. This is possible because the layers have been deposited and due to the low operating and leakage current of the organs.

From the foregoing description, it is apparent that a thin film field-effect transistor comprising an alloy layer of a-Si: F: H according to the present teaching has a number of advantages,

The planar structures of Figures 1, 3, and 9 may also be formed in reverse order from the shown sequence with the gate at the bottom. The scrap barriers can also be a MIS [metal insulator semiconductor] contact. The gate conductor in an organ may also consist of metal, polysilicon or stimulated semiconductor material with a different metal or semiconductor drain material, instead of both being made of the same metal or semiconductor material.

8006770

Claims (27)

1. Field-effect transistor member in the form of thin films, which member contains a source region, further a drain region, one. gate insulator and a port electrode in contact with the gate insulator, characterized by a thin film-deposited amorphous alloy (14; 44; 76; 96; 118) containing at least silicon and fluorine coupled to the source region (22; 52 ; 78; 98; 114), the drain region (24; 54; 74; 94; 116) and the port insulator (26; 56; 80; 102; 120). 2. Transistor member according to claim 1, characterized in that the amorphous alloy also contains hydrogen. Transistor member according to claim 1 or 2, characterized in that the amorphous alloy has a thickness between 10 and 500 nm. Transistor member according to any one of the preceding claims, characterized in that the drain region has a thickness between 50 and 2000 nm. Transistor member according to any one of the preceding claims, characterized in that the source region has a thickness between 50 and 2000 nm. 6. Transistor member according to any one of the preceding claims, characterized in that the gate insulator consists of a metal oxide. Transistor member according to any one of the preceding claims, characterized in that the source region is made of a metal. Transistor member according to any one of the preceding claims, characterized in that the drain region is made of a metal. Transistor member according to any one of claims 1 to 6 or 8, characterized in that the source region is made of a semiconductor alloy. 10. Transistor member according to any one of claims 1-7 or 9, characterized in that the drain region is made of a semiconductor alloy. Transistor member according to any one of the preceding claims, characterized in that the paort electrode is made of a metal. 8006770 -16.- Transistor member according to any one of claims 1-10, characterized in that the gate electrode is made of a semiconductor alloy. Transistor member according to any one of claims 2-12, wherein the amorphous alloy consists of Si: F. H, wherein a is between 80 and 98, b is between 1 and 10 and c is between 1 and 10 atomic%. Transistor member according to any one of the preceding claims, characterized by a flat MOS construction CIO, 40, 110). 15. Transistor member according to any one of the preceding claims, characterized by a number of flat MOS constructions stacked on top of one another. Transistor member according to any one of claims 1 to 13, characterized by a V-MOS construction (70, 90). Transistor member according to any one of the preceding claims, characterized in that it is deposited on a metal substrate. Transistor member according to any one of claims 1 to 16, characterized in that it is deposited on a glass substrate. Transistor member according to any one of claims 1 to 16, characterized in that it is deposited on a polymeric substrate. Transistor member according to claim 17, characterized by a thin layer of insulating material C112) between the transistor (110). and the metal bottom layer (111), so that the thermal path between the transistor and the metal bottom layer is only a very small distance, so that the metal bottom layer can act as an effective heat accumulator for distributing heat from the transistor with field action in the form of thin films. Transistor member according to any one of the preceding claims, characterized by a leakage current of less than 10 ^ A. Transistor member according to any one of the preceding claims, characterized by a switch-off frequency of more than 10 MHz. 23. Transistor member according to any one of the preceding claims, characterized by a saturation direct current of about 10 A. Transistor member according to any one of claims 1-20, characterized by a leakage current of less than 10 10 A, further by a "6 35 saturation direct current of more than 10 A and an upper output 8006770 • IT switching frequency of more than 10 MHz. . Transistor member according to any one of the preceding claims, characterized in that it is made with a vapor deposition technique. 26 Transistor member according to claim 25, characterized in that it is made by a glow discharge technique. 27. Thin-field field transistor member comprising a source region, further a drain region, a gate insulator, a thin film deposited semiconductor alloy coupled to the source region, the drain region and the gate-10 insulator, and gate electrode in contact with the gate insulator, characterized by a V-MOS construction (70, 90]. 8006770