CA1163377A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- CA1163377A CA1163377A CA000428672A CA428672A CA1163377A CA 1163377 A CA1163377 A CA 1163377A CA 000428672 A CA000428672 A CA 000428672A CA 428672 A CA428672 A CA 428672A CA 1163377 A CA1163377 A CA 1163377A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- thin film
- field effect
- effect transistor
- amorphous alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 46
- 230000005669 field effect Effects 0.000 claims abstract description 43
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 35
- 239000000956 alloy Substances 0.000 claims abstract description 35
- 239000012212 insulator Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910000808 amorphous metal alloy Inorganic materials 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 18
- 239000001257 hydrogen Substances 0.000 claims abstract description 18
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 11
- 239000011737 fluorine Substances 0.000 claims abstract description 11
- 238000010276 construction Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 13
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 10
- 101150068246 V-MOS gene Proteins 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract 1
- 239000000463 material Substances 0.000 description 41
- 239000004020 conductor Substances 0.000 description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 description 19
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 12
- 229910000077 silane Inorganic materials 0.000 description 12
- 239000013078 crystal Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 11
- 239000010408 film Substances 0.000 description 11
- 239000002019 doping agent Substances 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 239000002178 crystalline material Substances 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000878 H alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 241000347389 Serranus cabrilla Species 0.000 description 1
- VDRSDNINOSAWIV-UHFFFAOYSA-N [F].[Si] Chemical compound [F].[Si] VDRSDNINOSAWIV-UHFFFAOYSA-N 0.000 description 1
- 229910017817 a-Ge Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- -1 alumi-~ ~ ~33~7 num Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- KRTSDMXIXPKRQR-AATRIKPKSA-N monocrotophos Chemical compound CNC(=O)\C=C(/C)OP(=O)(OC)OC KRTSDMXIXPKRQR-AATRIKPKSA-N 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/685—Hi-Lo semiconductor devices, e.g. memory devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8615—Hi-lo semiconductor devices, e.g. memory devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Bipolar Transistors (AREA)
Abstract
ABSTRACT
A thin film, field effect transistor device having a source region, a drain region, a gate insulator, a thin film deposited amorphous alloy including at least silicon and fluorine coupled to the source region, the drain region and the gate insulator and a gate electrode in contact with the gate insulator. Preferably, the amorphous alloy also contains hydrogen and is a-Sia:Fb:Hc, where a is between 80 and 98 atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent. The field effect transistor can have various geometries, such as a V-MOS-like con-struction and can be deposited on various sub-strates with an insulator substrate between the active regions of the thin film, field effect tran-sistor and a conducting substrate. The thin film, field effect transistor can have various desirable characteristics depending upon the particular geom-etry chosen and thickness of the alloy such as, for example, a DC saturation current up to or greater than 10-4 amp, an upper cut off frequency at least above 10 MHz, a high OFF resistance: ON resistance
A thin film, field effect transistor device having a source region, a drain region, a gate insulator, a thin film deposited amorphous alloy including at least silicon and fluorine coupled to the source region, the drain region and the gate insulator and a gate electrode in contact with the gate insulator. Preferably, the amorphous alloy also contains hydrogen and is a-Sia:Fb:Hc, where a is between 80 and 98 atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent. The field effect transistor can have various geometries, such as a V-MOS-like con-struction and can be deposited on various sub-strates with an insulator substrate between the active regions of the thin film, field effect tran-sistor and a conducting substrate. The thin film, field effect transistor can have various desirable characteristics depending upon the particular geom-etry chosen and thickness of the alloy such as, for example, a DC saturation current up to or greater than 10-4 amp, an upper cut off frequency at least above 10 MHz, a high OFF resistance: ON resistance
Description
~ 3 ~377 Case 556.2 This is a divisional application oE Canadian application Serial Number 366,712 filed December 12, 1980.
The present invention relates to a thin film, field effect transistor, and more specifically to a thin film, field eEfect transistor of the type formed from an amorphous alloy including at least silicon and fluorine. In this respect, reference is made to U.S. Patent No 4 4,217,374 Stanford R.
Ovshinsky and Masatsugu I~u entitled: AMORPHOUS
SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE SEMI-CONDUCTORS and U.S. Patent No. 4,226,898 Stan-ford R. Ovshinsky and Arun Madan, of the sametitle.
-~ Silicon is the basis of the huge crystalline semiconductor industry and is the material which is utilized in substantially all the commercial inte-grated circuits now producedO When crystalline semiconductor technology reached a commercial state, it became the foundation of the present huge semi-conductor device manufactur;ng industry. This was due to the a~ility of the scientist to grow sub-stantially defect-free germanium and particularly silicon crystals, and then turn them into extrinsic ; materials with p-type and n-type conductivity re-gions therein. This was accomplished by diffusing into such cxystalline material parts per million o~
~ 16~3~
donor ~n) or acceptor (p) dopant materials intro-duced as substitutional impurities into the sub-stantially p~re crystalline materials, to increase their electrical conductivity and to control their being either of a p or n conduction type.
The semiconductor fabrication proces~es for màking p-n junction crystals involve extremely complex, time consuming and expensive procedures as well as high processing temperatures. Thus, these ln crystalline materials used in transistors and other current control devices are produced under very carefully controlled conditions by growing indi-vidual single silicon or germanlum crystals, where p-n junctions are required by doping such single crystals with extremely sma:ll and critical amounts of dopants. These crystal growing processes pro duce relatively small crystal wafers upon which the integrated circuits are formed.
In wafer scale integration technology the small area crystal wafer limits the overall size of the integrated circl~it which can be formed thereon.
In applications requiring large scale areas, such as in the display technology, the crystal wafers cannot be manufactured with as large areas as re-
The present invention relates to a thin film, field effect transistor, and more specifically to a thin film, field eEfect transistor of the type formed from an amorphous alloy including at least silicon and fluorine. In this respect, reference is made to U.S. Patent No 4 4,217,374 Stanford R.
Ovshinsky and Masatsugu I~u entitled: AMORPHOUS
SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE SEMI-CONDUCTORS and U.S. Patent No. 4,226,898 Stan-ford R. Ovshinsky and Arun Madan, of the sametitle.
-~ Silicon is the basis of the huge crystalline semiconductor industry and is the material which is utilized in substantially all the commercial inte-grated circuits now producedO When crystalline semiconductor technology reached a commercial state, it became the foundation of the present huge semi-conductor device manufactur;ng industry. This was due to the a~ility of the scientist to grow sub-stantially defect-free germanium and particularly silicon crystals, and then turn them into extrinsic ; materials with p-type and n-type conductivity re-gions therein. This was accomplished by diffusing into such cxystalline material parts per million o~
~ 16~3~
donor ~n) or acceptor (p) dopant materials intro-duced as substitutional impurities into the sub-stantially p~re crystalline materials, to increase their electrical conductivity and to control their being either of a p or n conduction type.
The semiconductor fabrication proces~es for màking p-n junction crystals involve extremely complex, time consuming and expensive procedures as well as high processing temperatures. Thus, these ln crystalline materials used in transistors and other current control devices are produced under very carefully controlled conditions by growing indi-vidual single silicon or germanlum crystals, where p-n junctions are required by doping such single crystals with extremely sma:ll and critical amounts of dopants. These crystal growing processes pro duce relatively small crystal wafers upon which the integrated circuits are formed.
In wafer scale integration technology the small area crystal wafer limits the overall size of the integrated circl~it which can be formed thereon.
In applications requiring large scale areas, such as in the display technology, the crystal wafers cannot be manufactured with as large areas as re-
-2-~ ' .
i ~ ~33'~7 quired or desired. The devices are formed, at least in part, by diffusing p or n-type dopants into the substrate. Further, each device is formed between isolation channels which are diffused into the substrate~ Packing density (the n~mber of devices per unit area of wafer surface) is also limited on the silicon wafers, because of the lea~-age current in each device and the power necessary to operate the devices, each of which generate heat which is undesirable. ~he silicon wafers do not readily dissipate heat. Alsor the leakage current adversely affects the battery or power cell life-time in portable applications.
In MOS type circuitry the switching speed is related directly to the gate length with the small-est length having the highest speed. The diffusion processes, photolithography and other crystalline manufacturing processes limit how short the gate length can be made.
2n ~urther, the packing density is extremely important because the cell size is exponentially related to the cost of each device. For instance, a decrease in die size by a factor of two results in a decrease in cost on the order of a ~actor of six.
~ ~ ~33'~'~
In summary, crystal silicon transistor andintegrated circuit parameters which are not vari-able as desired, require large amounts of material, high processing temperatures, are only producible only on relatively small area wafers and are expen-sive and time consuming to produce. Devices based upon amorphous silicon can eliminate these crystal silicon disadvantages. Amorphous silicon can be made faster, easier, at lower temperatures and in larger areas than can crystal silicon.
Accordingly, a considerable effort has been made to develop processes for readily depositing amorphous semiconductor alloys or films each of which can encompass relatively large areas, if desired, limited only by the size of the deposition equipment, and which could be doped to form p-type and n-type materials to form p-n junction tran-sistors and devices superior in cost and/or opera-tion to those produced by their crystalline coun-terparts. For many years such work was substan~tially ~nproductive. Amorphous silicon or germa-nium (Group IV) films are normally four-fold co-ordinated and were found to have microvoids and dangling bonds and other defects which produce a 1 ~ ~33~7 high density of localized states in the energy gap thereof. The presence of a high density of local ized states in the energy gap of amorphous silicon semiconductor Eilms resulted in such films not being successfully doped or otherwise modified to shift the Fermi level close to the conduction or valence bands making them unsuitable for making p-n junctions for transistors and other current control device applications.
ln In an attempt to minimize the aforementioned problems involved with amorphous silicon and ger-manium, W.E. Spear and P. G. Le Comber of Carnegie Laboratory of Physics, University of Dundee, in Dundee, Scotland did some work on "Substitutional Doping of Amorphous Silicon", as reported in a paper published in Solid State Communications, Vol.
17, pp. 1193-1195, 1975, toward the end of reducing the localized states in the energy gap in amorphous silicon or germanium to make the same approximate more closely intrinsic crystalline silicon or ger-- manium and of substitutionally doping the amorphous materials with suitable classic dopants, as in doping crystalline materials, to make them extrin-sic and of p or n conduction types.
~ 3 ~33~7 :. .
The reduction of the localized states was , accomplished by glow discharge deposition of amor-phous silicon films wherein a gas silane (SiH4) was passed through a reaction tube where the gas was decomposed by an r.f. glow discharge and deposited on a substrate at a substrate temperature of about 500-600K (227 327C). The material so deposited on the substrate was an intrinsic amorphous mate-rial consisting of silicon and hydrogen. To pro-ln duce amorphous material a gas of phosphine (PH3~for n type conduction or a gas of diborane (B2H6) for p type conduction were premixed with the silane gas and passed through the glow discharge reaction tube under the same operating conditions. The gaseous concentration of the dopants used was be-tween about 5 x 10-6 and 10-2 parts per volume.
The material so deposited included supposedly sub-stitutional phosphorus or boron dopant and was shown to be extrinsic and of n or p conduction type.
While it was not known by these researchers, it is now known by the work of others that the hydrogen in the silane combines at an optimum tem~
perature with many of the dangl~ng bonds of the , ~ ~
~: ~ 1 633~7 silicon during the glow discharge deposition, to substantially reduce the density of the localized states in the energy gap toward the end of making the electronic properties of the amorphous material approximate more nearly those of the corresponding crystalline material.
D.I. Jones, W.E. Spear, P.G. LeComber, S. Li, and R. Martins also worked on preparinS a-Ge:H from GeH4 using similar deposition techniques~ The material obtained gave evidence of a high density ~ of localized states in the energy gap thereof~
- Although the material could be doped the efficiency was substantially reduced from that obtainable with ;' a-Si:H. In this work reported in Philosophical Magazine B. Vol. 39, p. 147 (lg79) the authors conclude that because of the large density of gap states the material obtained is ". . . a less at-tractive material than a-Si for doping experiments and possible applica~ions."
The incorporation of hydrogen in the above silane method not only has limitations based upon the fixed ratio of hydrogen to silicon in silane, but, most importantly, various Si:H bonding con-figurations introduce new antibonding states which .'~ , .
'7 can have deleterious conse~uences in these mate-rials. Therefore, there are basic limitations in reducing the density of localized states in these materials which are particularly harmEul in terms of effective p as well as n doping. The resulting density of states of the silane deposited materials leads to a narrow depletion width which in turn limits the efficiencies of devices whose operation depends on the drift of free carriers. The method of making these materials by the use of only sil-icon and hydrogen also results in a high density of surface states which affects all the above param-eters.
After the development of the glow discharge deposition of silicon from silane gas was carried out, work was done on the sputter deposition of amorphous silicon films in the atmosphere of a mixture of argon (required by the sputtering de-position process) and molecular hydrogen, to deter-mine the results of such molecular hydrogen on thecharacteristics of the deposited amorphous silicon film. This research indicated that the hydrogen acted as a compensating agent which bonded in such a way as to reduce the localized states in the ~ ~ 6~7 energy gap. However~ the degree to which the lo-calized states in the energy gap were reduced in the sputter deposition process was much less than that achieved by the silane deposition process described above. The above described p and n dop-ant materials also were introduced in the sput-tering process to produce p and n doped materials.
These materials had a lower doping efficiency than the materials produced in the glow discharge pro-cess. Neither process produced efficient p-doped materials with sufficiently high acceptor con-centrations fox producing commercial p-n junction devices. The n-doping efficiency was below desir-able acceptable commerclal levels and the p-doping was particularly undesirable since it increased the number of localize~ states in the band gap.
Various methods of fabrication and construc-tion of thin film transistors and devices have been proposed wherein the various films of the tran-sistor are made of different materials having dif-ferent electrical characteristics. For example, thin film transistors have been proposed utilizing nickel oxide films, silicon films, amorphous sil-icon Ellms and amorphous silicon and hydrogen films ;
' ~ ~ ~3377 formed from silane as above mentioned~ Also, vari-ous geometrical configurations have been proposed such as a planar-MOS construction.
The prior deposition of amorE)hous silicon, which has been altered by hydrogen from the silane gas in an attempt to make it more closely resemble crystalline silicon and which has been doped in a manner like that of doping crystalline silicon, has characteristics which in all important respects are inferior to those of doped crystalline silicon. As reported by Le Comber and Spear and others refer-enced above, in the silane based transistor devi~es the leakage current may be as low as 10-11 amperes, the saturation current appears to be about 5 x 10-6 amperes, the device switchincl frequency appears to be about 104 Hz and the stability is poor since the material degrades with time.
It has been proposed to ma~e a solar cell which is essentially a photosensitive rectifier utilizing an amorphous alloy including silicon and .~ :
fluorine in the aforementioned U.S. Patent No.
4,217,374, issued 8/12/80 for Amorphous Semicon-ductor Equivalent to Crystalline Semiconductors, ~tan~ord R. Ovshinsky and Masatsugu Izu and U.S.
~ 3 63377 Patent No. ~,276,898, issued 10/7/80 of the same -title, Stanford R. Ovshinsky and ~run Madan.
We have found that these disadvantages rnay be overcome by providing a thin film, field effect transistor formed from a silicon, fluorine! and hydrogen amorphous alloy in various constructions. These transistors provide very low leakage currents, fast switching speeds, high OFF resistance; ON
resistance ratios,,and do not degrade with time. We also provide a new and improved V-MOS thin film~ field e~fect transistor formed from the above amorphous alloy.
According to the present invention there is provided a thin film, field effect transistor device including a source region, a drain region, a, gate insulator, a thin-film deposited semiconductor alloy coupled to the source region, the drain region and the gate insulator, and a gate electrode in contact with the gate insulator having a V-MOS like construction, Preferably, the amorphous alloy also contains hydrogen, such a,s an amorphous alloy a-Sia:Fb:H,c where a is between 80 and 98 atomic percentl b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.
csm~ ' ' 1 3 ~337~
The field effect transistor can have various geometries including a V-MOS like construction of the invention and can be deposited on various sub-strates with an insulator between the active re-gions of the thin film~ field effect transistor anda conducting substrate such as a metal. The tran-sistors can be deposited on an insulator, a semi-conductor, an insulated metal or an insulated semi-conductor substrate~ Because of the capability to be formed on various substrates and the low leakage and operating current, the transistors also can be formed on top of one another, i~e., stacked.
The thin film, field effect transistor can have various desirable characteristics depending upon the particular geometry chosen and thickness of the film of amorphous silicon fluorine material chosen such as, for example, A DC saturation cur-rent as low as 10-6 amperes and up to or greater ~han 10-4 amperes, an upper cut off frequency at least above 10 MHz, a high OFF resistance:ON resis-~ance ratio of about 107, and a very low leakage current of about 10-11 amps or less. Further, the alloy does not degrade with time.
.
'.;
~ -12-~ ;
.
~ 1 ~3377 The preferred embodiment of this invention will now be described by way of example, with re-ference to the drawings accompanying this specifi-cation in which:
Fig. 1 is a vertical sectional view of one embodiment of thin film deposited, field effect transistor made in accordance with the teachings of the present invention and having metal source and drain regions similar to a planar ~OS-type tran~
:~ 10 sistor.
Fig. 2 is a schematic circuit diagram of the ; transistor shown in Fig. 1.
Fig. 3 is a vertical sectional view through a second embodiment of a thin film deposited, field .~ 15 effect transistor similar to the transistor shown in Fig. 1, having semiconductor source and drain -~; regions.
` Fig. 4 is a schematic circuit diagram of the transistor shown in Fig. 3.
.
., ~ .
';
-13- .
~ ~ ~337~
Fig. 5 is a vertical sectional view of another embodiment of thin Eilm deposited, Eield effect transistor similar to the transistor shown in Fig.
1, having metal source and drain regions similar to a V-MOS-type transistor.
Fig. 6 is a schematic circuit diagram of the transistor shown in Fig. 5.
-~ Fig~ 7 is a vertical sectional view through a second embodiment of a thin film deposited, field effect transistor similar to the transistor shown in Fig. 5, having semiconductor source and drain regions.
Fig~ 8 is a schematic circuit diagram of the transistor shown in Fig. 7.
Fig. 9 is a vertical sectional view through a thin film deposited, field effect transistor, sim-ilar in function to the transistors shown in Figs.
1 8 but having a different geometrical construc-~` tion.
, . .
;~ 20 ~eferring now to the figures in greater de-tail, there is illustrated in Fig. 1 a thin film, field effect transistor 10 made in accordance with the teachings of the present invention. As shown, the transistor 10 is formed on a substrate 12 of ` ^14-insulating material which could be a silicon mate `rial, a layer of polymer material or an insulator on top of a metal. Deposited on the substrate 12 in accordance with the teachings of the present ; 5 invention is a thin alloy layer 14 including sil-icon and fluorine which can also contain hydrogen and which can be doped to form an N or P type al-loy. On top of this alloy layer 14 is a layer or -band 16 of insulating material such as a field oxide and spaced therefrom is another layer or band 18 of .insulating material such as a field oxide.
A channel or opening 20 is formed, as by con-ventional photolithography techniques, between the .~
two bands 16 and 18. A source metal conductor 22 is deposited over the band 1~ with a portion there-of in contact with the alloy layer 14 to form a Schottky barrier contact at the interface between the source metal 22 and the amorphous alloy layer 14.
In a similar manner a conductor or layer 24 of drain metal is deposited over the insulating band 18 with a portion thereof in contact with the alloy la~er 14 spaced from the source metal 22~ The in-terface between the drain metal 24 and the amor-~3 :~ 633~'~
phous layer 14 creates another Schottky barrier contact. A gate insulator layer 26 of insulating material such as gate oxide or gate nitride 26 is deposited over the source metal 22 and drain metal 24 and in contact with the amorphous alloy layer 14 between the source and drain metal. On this layer 26 of gate insulating material is deposited a gate conductor 28 which can be made of an~ suitable metal such as aluminum or molybdenum. On the gate conductor another layer 30 of insulating material is deposited to passivate the device, which is identified as a field oxide.
The insulating layers 16 and 30 would be join-ed before the next adjacent transistor with the source 22 connected to an external conductor. The insulating layer 16 forms the insulator for the next device similar to the insulator 18 of the transistor 10 shown.
The gate insulator layer 26 and the bands 16 and 18 of insulating material referred to as being a field oxide can be made of a metal oxider silicon dioxide or other insulator such as silicon nitride.
The source metal 22 and drain metal 24 can be form-ed of any suitable conductive metal such as alumi-~ ~ ~33~7 num, molybdenum or a high work function metal such as gold ~a~ladium, platinum or chromium. The gate insulator can be a nitride, silicon dioxide or ; silicon nitride material.
In accordance with the teachings of the pre-sent invention, an alloy containing silicon and fluorine which can also contain hydrogen is uti-lized for forming the amorphous alloy layer 14.
This alloy provides the desirable characteristics enumerated before which can be utilized for many different circuits. The alloy layer 14 is pre-ferably made of a-Sia:Fb:Hc where a is between 80 and 9~ atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.
The alloy can be doped with a dopant from Group V or Group III of the Periodic Table mate-rials in an amount constituting between 10 and 1000 parts per million (ppm). The dopant materials and amount of doping can vary.
The thickness of the alloy layer 14 of amor-phous material can be between 100 and 5D00 Ang-stroms, one thickness utilized being approximately 1000 Angstroms. The source metal 22 and the drain metal 24 can also have thicknesses ranging from 500 9 3 ~3~'~'7 to 20,000 Angstroms with one utilized thickness being of approximately 2000 Angstroms. The gate conductor 28 although described as being made of metal, can be made of a doped semiconductor mate-rial if desired.
Depending upon the geometry of the various layers and thicknesses of the various layers, a field effect transistor can be constructed as d~-scribed above wherein the leakage current is ap-1~ proximately 10-11 amperes thereby to provide a high OFF resistance and a DC saturation current of ap-proximately 10 4 amperes-.
In constructing the thin film, field effect transistor 10 shown in Fig. 1, the layers of mate-rial, and particularly the alloy layer 14, aredeposited by various deposition techniques, pre-ferably by glow discharge.
A conventional schematic gate IG), source ~S~
and drain (D) circuit diagram of the field effect transistor 10 is illustrated in Fig. 2.
Referring now to Fig~ 3, there is illustrated a planar constructed thin film, field effect tran-sistor 40 which, like the transistor 10, is formed on an insulated substrate layer 42. On top of the `~ ~ 6~3~7 .
substrate material 42 is deposited, such as by glow discharge, an alloy layer 44 including silicon and fluorine which also preferably includes hydrogen and can be o~ the N or P type. On this alloy layer 44 are deposited two layers of insulating material 46 and 48 which are referred to in Fig. 3 as being made o a field oxide with an opening 50 formed therebetween. Above the insulating layers 46 and 48 are deposited, respectively~ a source alloy layer 52 and a drain alloy layer 54 which also ^; include ~ilicon and fluorine and preferably include hydrogen. The source 52 and the drain alloy 54 are N or P type amorphous alloys. An N-P or P-N junc-tion is then formed at the interface where the layers 52 and 54 make contact with the alloy layer 44.
After depositing the layers 52 and 54, a gate insulator layer 56 r~ferred to as a gate oxide 56 is deposited over the source region 52, the exposed portion of the amorphous layer 44 and the drain region 54. Then a gate con~uctor 58 is deposited over the gate insulator ~ and a passivating insu-lating layer 60 is deposited on top of the gate conductor 58, identified as a field oxide.
~ ~ ~3~
A conventional schematic gate 'G), source (S) and drain (D) circuit diagram of the transistor 40 is illustrated in Fig. 4.
The difference between the transistor 40 and the transistor 10 is that the drain and source regions or conductors 52 and 54 of the ~:ransistor 40 are made of a semiconductor material and prefer-ably an a-Si:F:H alloy.
In Fig. 5 there is illustrated a new V-MOS
like construction illustrated in a thin film~ field effect transistor 70 made in accordance with the teachings of the present invention. On a substrate layer 72 is first deposited a layer or band of ! drain metal 74 which has a central portion thereof 5 cut or etched away. On top of the drain metal 74 is deposited a thin layer or band of amorphous a~loy 76 which has a central portion cut or etched away aligned with the cut away portion of layer 74.
Similarly, a layer of source metal 78 is deposited on the layer 76 and a corresponding central portion thereof is cut away. Alternately, all the layers can be etched in one step following the deposition of all the layers. Then a ~ate insulator 80 re-ferred to as a gate oxide is deposited over the ~ ~ ~3377 source metal 78 and into the resulting central V-cut space 82 and onto the inclined edges of the layer portions 74, 76 and 78 and over the exposed substrate 72~ Then a gate conductdr 84 is de-posited on the ~ate insulator 82 and a layer 86 ofinsulating material identified as a field oxide is deposited over the gate metal conductor 84 as a passivating layer.
This particular V-MOS like construction with the open space 80 has the advantage that a very short distance L is established between the source metal 74 and the drain metal 78 through the alloy layer 76. The layer thickness or distance L re-sults in a high operating frequency, and a higher saturation current than the transistor configu-ration of Figs. 1 and 3. The leakage current may increase over the configuration of Figs. 1 and 3.
A conventional schematic gate (G), source ~S) and drain (D) diagram of the transistor 70 is shown in Fig. 6.
In Fig. 7 is illustrated another V-MOS like thin film, field effect transistor 90 formed on a substrate 92 with alloy layers 94, 96 and 98 having silicon and fluorine (N or P type) deposited on the
i ~ ~33'~7 quired or desired. The devices are formed, at least in part, by diffusing p or n-type dopants into the substrate. Further, each device is formed between isolation channels which are diffused into the substrate~ Packing density (the n~mber of devices per unit area of wafer surface) is also limited on the silicon wafers, because of the lea~-age current in each device and the power necessary to operate the devices, each of which generate heat which is undesirable. ~he silicon wafers do not readily dissipate heat. Alsor the leakage current adversely affects the battery or power cell life-time in portable applications.
In MOS type circuitry the switching speed is related directly to the gate length with the small-est length having the highest speed. The diffusion processes, photolithography and other crystalline manufacturing processes limit how short the gate length can be made.
2n ~urther, the packing density is extremely important because the cell size is exponentially related to the cost of each device. For instance, a decrease in die size by a factor of two results in a decrease in cost on the order of a ~actor of six.
~ ~ ~33'~'~
In summary, crystal silicon transistor andintegrated circuit parameters which are not vari-able as desired, require large amounts of material, high processing temperatures, are only producible only on relatively small area wafers and are expen-sive and time consuming to produce. Devices based upon amorphous silicon can eliminate these crystal silicon disadvantages. Amorphous silicon can be made faster, easier, at lower temperatures and in larger areas than can crystal silicon.
Accordingly, a considerable effort has been made to develop processes for readily depositing amorphous semiconductor alloys or films each of which can encompass relatively large areas, if desired, limited only by the size of the deposition equipment, and which could be doped to form p-type and n-type materials to form p-n junction tran-sistors and devices superior in cost and/or opera-tion to those produced by their crystalline coun-terparts. For many years such work was substan~tially ~nproductive. Amorphous silicon or germa-nium (Group IV) films are normally four-fold co-ordinated and were found to have microvoids and dangling bonds and other defects which produce a 1 ~ ~33~7 high density of localized states in the energy gap thereof. The presence of a high density of local ized states in the energy gap of amorphous silicon semiconductor Eilms resulted in such films not being successfully doped or otherwise modified to shift the Fermi level close to the conduction or valence bands making them unsuitable for making p-n junctions for transistors and other current control device applications.
ln In an attempt to minimize the aforementioned problems involved with amorphous silicon and ger-manium, W.E. Spear and P. G. Le Comber of Carnegie Laboratory of Physics, University of Dundee, in Dundee, Scotland did some work on "Substitutional Doping of Amorphous Silicon", as reported in a paper published in Solid State Communications, Vol.
17, pp. 1193-1195, 1975, toward the end of reducing the localized states in the energy gap in amorphous silicon or germanium to make the same approximate more closely intrinsic crystalline silicon or ger-- manium and of substitutionally doping the amorphous materials with suitable classic dopants, as in doping crystalline materials, to make them extrin-sic and of p or n conduction types.
~ 3 ~33~7 :. .
The reduction of the localized states was , accomplished by glow discharge deposition of amor-phous silicon films wherein a gas silane (SiH4) was passed through a reaction tube where the gas was decomposed by an r.f. glow discharge and deposited on a substrate at a substrate temperature of about 500-600K (227 327C). The material so deposited on the substrate was an intrinsic amorphous mate-rial consisting of silicon and hydrogen. To pro-ln duce amorphous material a gas of phosphine (PH3~for n type conduction or a gas of diborane (B2H6) for p type conduction were premixed with the silane gas and passed through the glow discharge reaction tube under the same operating conditions. The gaseous concentration of the dopants used was be-tween about 5 x 10-6 and 10-2 parts per volume.
The material so deposited included supposedly sub-stitutional phosphorus or boron dopant and was shown to be extrinsic and of n or p conduction type.
While it was not known by these researchers, it is now known by the work of others that the hydrogen in the silane combines at an optimum tem~
perature with many of the dangl~ng bonds of the , ~ ~
~: ~ 1 633~7 silicon during the glow discharge deposition, to substantially reduce the density of the localized states in the energy gap toward the end of making the electronic properties of the amorphous material approximate more nearly those of the corresponding crystalline material.
D.I. Jones, W.E. Spear, P.G. LeComber, S. Li, and R. Martins also worked on preparinS a-Ge:H from GeH4 using similar deposition techniques~ The material obtained gave evidence of a high density ~ of localized states in the energy gap thereof~
- Although the material could be doped the efficiency was substantially reduced from that obtainable with ;' a-Si:H. In this work reported in Philosophical Magazine B. Vol. 39, p. 147 (lg79) the authors conclude that because of the large density of gap states the material obtained is ". . . a less at-tractive material than a-Si for doping experiments and possible applica~ions."
The incorporation of hydrogen in the above silane method not only has limitations based upon the fixed ratio of hydrogen to silicon in silane, but, most importantly, various Si:H bonding con-figurations introduce new antibonding states which .'~ , .
'7 can have deleterious conse~uences in these mate-rials. Therefore, there are basic limitations in reducing the density of localized states in these materials which are particularly harmEul in terms of effective p as well as n doping. The resulting density of states of the silane deposited materials leads to a narrow depletion width which in turn limits the efficiencies of devices whose operation depends on the drift of free carriers. The method of making these materials by the use of only sil-icon and hydrogen also results in a high density of surface states which affects all the above param-eters.
After the development of the glow discharge deposition of silicon from silane gas was carried out, work was done on the sputter deposition of amorphous silicon films in the atmosphere of a mixture of argon (required by the sputtering de-position process) and molecular hydrogen, to deter-mine the results of such molecular hydrogen on thecharacteristics of the deposited amorphous silicon film. This research indicated that the hydrogen acted as a compensating agent which bonded in such a way as to reduce the localized states in the ~ ~ 6~7 energy gap. However~ the degree to which the lo-calized states in the energy gap were reduced in the sputter deposition process was much less than that achieved by the silane deposition process described above. The above described p and n dop-ant materials also were introduced in the sput-tering process to produce p and n doped materials.
These materials had a lower doping efficiency than the materials produced in the glow discharge pro-cess. Neither process produced efficient p-doped materials with sufficiently high acceptor con-centrations fox producing commercial p-n junction devices. The n-doping efficiency was below desir-able acceptable commerclal levels and the p-doping was particularly undesirable since it increased the number of localize~ states in the band gap.
Various methods of fabrication and construc-tion of thin film transistors and devices have been proposed wherein the various films of the tran-sistor are made of different materials having dif-ferent electrical characteristics. For example, thin film transistors have been proposed utilizing nickel oxide films, silicon films, amorphous sil-icon Ellms and amorphous silicon and hydrogen films ;
' ~ ~ ~3377 formed from silane as above mentioned~ Also, vari-ous geometrical configurations have been proposed such as a planar-MOS construction.
The prior deposition of amorE)hous silicon, which has been altered by hydrogen from the silane gas in an attempt to make it more closely resemble crystalline silicon and which has been doped in a manner like that of doping crystalline silicon, has characteristics which in all important respects are inferior to those of doped crystalline silicon. As reported by Le Comber and Spear and others refer-enced above, in the silane based transistor devi~es the leakage current may be as low as 10-11 amperes, the saturation current appears to be about 5 x 10-6 amperes, the device switchincl frequency appears to be about 104 Hz and the stability is poor since the material degrades with time.
It has been proposed to ma~e a solar cell which is essentially a photosensitive rectifier utilizing an amorphous alloy including silicon and .~ :
fluorine in the aforementioned U.S. Patent No.
4,217,374, issued 8/12/80 for Amorphous Semicon-ductor Equivalent to Crystalline Semiconductors, ~tan~ord R. Ovshinsky and Masatsugu Izu and U.S.
~ 3 63377 Patent No. ~,276,898, issued 10/7/80 of the same -title, Stanford R. Ovshinsky and ~run Madan.
We have found that these disadvantages rnay be overcome by providing a thin film, field effect transistor formed from a silicon, fluorine! and hydrogen amorphous alloy in various constructions. These transistors provide very low leakage currents, fast switching speeds, high OFF resistance; ON
resistance ratios,,and do not degrade with time. We also provide a new and improved V-MOS thin film~ field e~fect transistor formed from the above amorphous alloy.
According to the present invention there is provided a thin film, field effect transistor device including a source region, a drain region, a, gate insulator, a thin-film deposited semiconductor alloy coupled to the source region, the drain region and the gate insulator, and a gate electrode in contact with the gate insulator having a V-MOS like construction, Preferably, the amorphous alloy also contains hydrogen, such a,s an amorphous alloy a-Sia:Fb:H,c where a is between 80 and 98 atomic percentl b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.
csm~ ' ' 1 3 ~337~
The field effect transistor can have various geometries including a V-MOS like construction of the invention and can be deposited on various sub-strates with an insulator between the active re-gions of the thin film~ field effect transistor anda conducting substrate such as a metal. The tran-sistors can be deposited on an insulator, a semi-conductor, an insulated metal or an insulated semi-conductor substrate~ Because of the capability to be formed on various substrates and the low leakage and operating current, the transistors also can be formed on top of one another, i~e., stacked.
The thin film, field effect transistor can have various desirable characteristics depending upon the particular geometry chosen and thickness of the film of amorphous silicon fluorine material chosen such as, for example, A DC saturation cur-rent as low as 10-6 amperes and up to or greater ~han 10-4 amperes, an upper cut off frequency at least above 10 MHz, a high OFF resistance:ON resis-~ance ratio of about 107, and a very low leakage current of about 10-11 amps or less. Further, the alloy does not degrade with time.
.
'.;
~ -12-~ ;
.
~ 1 ~3377 The preferred embodiment of this invention will now be described by way of example, with re-ference to the drawings accompanying this specifi-cation in which:
Fig. 1 is a vertical sectional view of one embodiment of thin film deposited, field effect transistor made in accordance with the teachings of the present invention and having metal source and drain regions similar to a planar ~OS-type tran~
:~ 10 sistor.
Fig. 2 is a schematic circuit diagram of the ; transistor shown in Fig. 1.
Fig. 3 is a vertical sectional view through a second embodiment of a thin film deposited, field .~ 15 effect transistor similar to the transistor shown in Fig. 1, having semiconductor source and drain -~; regions.
` Fig. 4 is a schematic circuit diagram of the transistor shown in Fig. 3.
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., ~ .
';
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~ ~ ~337~
Fig. 5 is a vertical sectional view of another embodiment of thin Eilm deposited, Eield effect transistor similar to the transistor shown in Fig.
1, having metal source and drain regions similar to a V-MOS-type transistor.
Fig. 6 is a schematic circuit diagram of the transistor shown in Fig. 5.
-~ Fig~ 7 is a vertical sectional view through a second embodiment of a thin film deposited, field effect transistor similar to the transistor shown in Fig. 5, having semiconductor source and drain regions.
Fig~ 8 is a schematic circuit diagram of the transistor shown in Fig. 7.
Fig. 9 is a vertical sectional view through a thin film deposited, field effect transistor, sim-ilar in function to the transistors shown in Figs.
1 8 but having a different geometrical construc-~` tion.
, . .
;~ 20 ~eferring now to the figures in greater de-tail, there is illustrated in Fig. 1 a thin film, field effect transistor 10 made in accordance with the teachings of the present invention. As shown, the transistor 10 is formed on a substrate 12 of ` ^14-insulating material which could be a silicon mate `rial, a layer of polymer material or an insulator on top of a metal. Deposited on the substrate 12 in accordance with the teachings of the present ; 5 invention is a thin alloy layer 14 including sil-icon and fluorine which can also contain hydrogen and which can be doped to form an N or P type al-loy. On top of this alloy layer 14 is a layer or -band 16 of insulating material such as a field oxide and spaced therefrom is another layer or band 18 of .insulating material such as a field oxide.
A channel or opening 20 is formed, as by con-ventional photolithography techniques, between the .~
two bands 16 and 18. A source metal conductor 22 is deposited over the band 1~ with a portion there-of in contact with the alloy layer 14 to form a Schottky barrier contact at the interface between the source metal 22 and the amorphous alloy layer 14.
In a similar manner a conductor or layer 24 of drain metal is deposited over the insulating band 18 with a portion thereof in contact with the alloy la~er 14 spaced from the source metal 22~ The in-terface between the drain metal 24 and the amor-~3 :~ 633~'~
phous layer 14 creates another Schottky barrier contact. A gate insulator layer 26 of insulating material such as gate oxide or gate nitride 26 is deposited over the source metal 22 and drain metal 24 and in contact with the amorphous alloy layer 14 between the source and drain metal. On this layer 26 of gate insulating material is deposited a gate conductor 28 which can be made of an~ suitable metal such as aluminum or molybdenum. On the gate conductor another layer 30 of insulating material is deposited to passivate the device, which is identified as a field oxide.
The insulating layers 16 and 30 would be join-ed before the next adjacent transistor with the source 22 connected to an external conductor. The insulating layer 16 forms the insulator for the next device similar to the insulator 18 of the transistor 10 shown.
The gate insulator layer 26 and the bands 16 and 18 of insulating material referred to as being a field oxide can be made of a metal oxider silicon dioxide or other insulator such as silicon nitride.
The source metal 22 and drain metal 24 can be form-ed of any suitable conductive metal such as alumi-~ ~ ~33~7 num, molybdenum or a high work function metal such as gold ~a~ladium, platinum or chromium. The gate insulator can be a nitride, silicon dioxide or ; silicon nitride material.
In accordance with the teachings of the pre-sent invention, an alloy containing silicon and fluorine which can also contain hydrogen is uti-lized for forming the amorphous alloy layer 14.
This alloy provides the desirable characteristics enumerated before which can be utilized for many different circuits. The alloy layer 14 is pre-ferably made of a-Sia:Fb:Hc where a is between 80 and 9~ atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.
The alloy can be doped with a dopant from Group V or Group III of the Periodic Table mate-rials in an amount constituting between 10 and 1000 parts per million (ppm). The dopant materials and amount of doping can vary.
The thickness of the alloy layer 14 of amor-phous material can be between 100 and 5D00 Ang-stroms, one thickness utilized being approximately 1000 Angstroms. The source metal 22 and the drain metal 24 can also have thicknesses ranging from 500 9 3 ~3~'~'7 to 20,000 Angstroms with one utilized thickness being of approximately 2000 Angstroms. The gate conductor 28 although described as being made of metal, can be made of a doped semiconductor mate-rial if desired.
Depending upon the geometry of the various layers and thicknesses of the various layers, a field effect transistor can be constructed as d~-scribed above wherein the leakage current is ap-1~ proximately 10-11 amperes thereby to provide a high OFF resistance and a DC saturation current of ap-proximately 10 4 amperes-.
In constructing the thin film, field effect transistor 10 shown in Fig. 1, the layers of mate-rial, and particularly the alloy layer 14, aredeposited by various deposition techniques, pre-ferably by glow discharge.
A conventional schematic gate IG), source ~S~
and drain (D) circuit diagram of the field effect transistor 10 is illustrated in Fig. 2.
Referring now to Fig~ 3, there is illustrated a planar constructed thin film, field effect tran-sistor 40 which, like the transistor 10, is formed on an insulated substrate layer 42. On top of the `~ ~ 6~3~7 .
substrate material 42 is deposited, such as by glow discharge, an alloy layer 44 including silicon and fluorine which also preferably includes hydrogen and can be o~ the N or P type. On this alloy layer 44 are deposited two layers of insulating material 46 and 48 which are referred to in Fig. 3 as being made o a field oxide with an opening 50 formed therebetween. Above the insulating layers 46 and 48 are deposited, respectively~ a source alloy layer 52 and a drain alloy layer 54 which also ^; include ~ilicon and fluorine and preferably include hydrogen. The source 52 and the drain alloy 54 are N or P type amorphous alloys. An N-P or P-N junc-tion is then formed at the interface where the layers 52 and 54 make contact with the alloy layer 44.
After depositing the layers 52 and 54, a gate insulator layer 56 r~ferred to as a gate oxide 56 is deposited over the source region 52, the exposed portion of the amorphous layer 44 and the drain region 54. Then a gate con~uctor 58 is deposited over the gate insulator ~ and a passivating insu-lating layer 60 is deposited on top of the gate conductor 58, identified as a field oxide.
~ ~ ~3~
A conventional schematic gate 'G), source (S) and drain (D) circuit diagram of the transistor 40 is illustrated in Fig. 4.
The difference between the transistor 40 and the transistor 10 is that the drain and source regions or conductors 52 and 54 of the ~:ransistor 40 are made of a semiconductor material and prefer-ably an a-Si:F:H alloy.
In Fig. 5 there is illustrated a new V-MOS
like construction illustrated in a thin film~ field effect transistor 70 made in accordance with the teachings of the present invention. On a substrate layer 72 is first deposited a layer or band of ! drain metal 74 which has a central portion thereof 5 cut or etched away. On top of the drain metal 74 is deposited a thin layer or band of amorphous a~loy 76 which has a central portion cut or etched away aligned with the cut away portion of layer 74.
Similarly, a layer of source metal 78 is deposited on the layer 76 and a corresponding central portion thereof is cut away. Alternately, all the layers can be etched in one step following the deposition of all the layers. Then a ~ate insulator 80 re-ferred to as a gate oxide is deposited over the ~ ~ ~3377 source metal 78 and into the resulting central V-cut space 82 and onto the inclined edges of the layer portions 74, 76 and 78 and over the exposed substrate 72~ Then a gate conductdr 84 is de-posited on the ~ate insulator 82 and a layer 86 ofinsulating material identified as a field oxide is deposited over the gate metal conductor 84 as a passivating layer.
This particular V-MOS like construction with the open space 80 has the advantage that a very short distance L is established between the source metal 74 and the drain metal 78 through the alloy layer 76. The layer thickness or distance L re-sults in a high operating frequency, and a higher saturation current than the transistor configu-ration of Figs. 1 and 3. The leakage current may increase over the configuration of Figs. 1 and 3.
A conventional schematic gate (G), source ~S) and drain (D) diagram of the transistor 70 is shown in Fig. 6.
In Fig. 7 is illustrated another V-MOS like thin film, field effect transistor 90 formed on a substrate 92 with alloy layers 94, 96 and 98 having silicon and fluorine (N or P type) deposited on the
3 3 7 7 '`.
substrate 92. The respective layers 94, 96 and 98 have a central portion 100 cut or etched away thereof~ Then a gate insulator 102 identified as a gate oxide is deposited over the edge of the layer S 98 and contacts the exposed edges of the layers 94, 96, and 98 and also the exposed portion of the substrate 92 as shown. A gate conductor 104 is deposited over the insulator layer 102 and lastly a layer 106 of insulating materialy such as a field oxide, is deposited over the gate conductor 104.
The transistor 90 operates utilizing the oppositely biased P-N junctions formed between layers 94 and 96 and between 96 and 98.
The transistor 90 is similar to the transistor lS 70 as shown in FigO 5 except that the source region 98 and drain region 94 is macle of a semiconduotor alloy, such as a-Si:F:H. The V-MOS like construc-tion of the invention illustrated by transistors 70 and 90 is advantageously utilized with any depos-ited semiconductor material, such as but not only asilicon alloy containing at least hydrogen as de~
posited from silane.
A conventional schematic circuit diagram of the transistor 90 is illustrated in Fig. 8.
` ~ 3 633~7 Referring now to Fig. 9, there is illustrated -therein another field effect transistor 110 made in accordance with the teachings of the present inven-tion. The transistor 110 is formed on a metal ; 5 substrate 111 which has deposited thereon a thin -layer of insulating material 112 which separates the active components of the transistor 110 from the metal substrate 111 and yet is thin enough so that heat generated in the transistor 110 can flow to the metal substrate which forms a heat sink therefor.
The thin film, field effect transistor 110 is formed by depositing a source conductor layer 114 made of metal or N or P type semiconductor alloy~
A drain conductor 116 is deposited on the insu-lating layer 112 and also is made of a metal or a P
or N type semiconductor alloyO On top of the con-ductors 114 and 116 is deposi.ted an intrinsic or lightly doped alloy layer 118, such as the a-Si:F:~
alloy previously described.
On top of the alloy layer 118 is deposited a gate insulator 120 which can be a silicon oxide or a silicon nitrideO On top of the gate insulator 120 is deposited a gate conductor layer 122 which ~ ~ 63~377 can be a metal or semiconductor material. A pas - sivating layer 124 is deposited over the gate con-ductor 122.
The various transistors 10, 40, 70, 90, and 110 can be formed in a matrix so that either the source or drain region extends as a Y axis con-ductor across the deposited substrate 112. Then, the drain or source region is deposited to form a segregated drain or source region which is then lC connected to an X axis conductor. Then the gate electrode is deposited so as to extend parallel to the Y axis to form a Y axis gate conductor. In this way, the field effect transistors 10, 40, 70 90, and 110 can be utilized in conjunction with PROM devices to form the isolating device in a memory circuit therefor which comprises a memory region and the isolating device.
The thin film, field effect transistor of the present invention and the various specific embodi-ments thereof described herein provide a transistorwhich is very small and yet has very good operatlng characteristics as enumerated above. The top in-sulating layer of the transistors, such as 124 in Fig. 9, can be utilized to form the insulating ~ 1 ~33~7 layer for another transistor to be formed thereon to provide a stacked transistor configuration and hence further increase the packing density of the devices. This i5 possible because the layers are deposited and because of the low operating and leakage current of the devices.
From the foregoing description it will be apparent that a thin film, field effect transistor incorporating an alloy layer of a-Si:F:H therein according to the teachillgs of the present invention has a numbee of advantages.
The planar structures of Figs. 1, 3 and 9 also can be formed in inverse order to that shown with the gate on the bottom. The Schottky barriers also can be an MIS (metal insulator semiconductor) con-tact~ Also, the gate conductor in a device can be metal, polysilicon or doped semiconductor material with a different metal or semiconductor drain ma-terial, instead of both being of the same metal or semiconductor material.
This divisional application includes subject matter disclosed and claimed in copending Canadian application 366,712.
substrate 92. The respective layers 94, 96 and 98 have a central portion 100 cut or etched away thereof~ Then a gate insulator 102 identified as a gate oxide is deposited over the edge of the layer S 98 and contacts the exposed edges of the layers 94, 96, and 98 and also the exposed portion of the substrate 92 as shown. A gate conductor 104 is deposited over the insulator layer 102 and lastly a layer 106 of insulating materialy such as a field oxide, is deposited over the gate conductor 104.
The transistor 90 operates utilizing the oppositely biased P-N junctions formed between layers 94 and 96 and between 96 and 98.
The transistor 90 is similar to the transistor lS 70 as shown in FigO 5 except that the source region 98 and drain region 94 is macle of a semiconduotor alloy, such as a-Si:F:H. The V-MOS like construc-tion of the invention illustrated by transistors 70 and 90 is advantageously utilized with any depos-ited semiconductor material, such as but not only asilicon alloy containing at least hydrogen as de~
posited from silane.
A conventional schematic circuit diagram of the transistor 90 is illustrated in Fig. 8.
` ~ 3 633~7 Referring now to Fig. 9, there is illustrated -therein another field effect transistor 110 made in accordance with the teachings of the present inven-tion. The transistor 110 is formed on a metal ; 5 substrate 111 which has deposited thereon a thin -layer of insulating material 112 which separates the active components of the transistor 110 from the metal substrate 111 and yet is thin enough so that heat generated in the transistor 110 can flow to the metal substrate which forms a heat sink therefor.
The thin film, field effect transistor 110 is formed by depositing a source conductor layer 114 made of metal or N or P type semiconductor alloy~
A drain conductor 116 is deposited on the insu-lating layer 112 and also is made of a metal or a P
or N type semiconductor alloyO On top of the con-ductors 114 and 116 is deposi.ted an intrinsic or lightly doped alloy layer 118, such as the a-Si:F:~
alloy previously described.
On top of the alloy layer 118 is deposited a gate insulator 120 which can be a silicon oxide or a silicon nitrideO On top of the gate insulator 120 is deposited a gate conductor layer 122 which ~ ~ 63~377 can be a metal or semiconductor material. A pas - sivating layer 124 is deposited over the gate con-ductor 122.
The various transistors 10, 40, 70, 90, and 110 can be formed in a matrix so that either the source or drain region extends as a Y axis con-ductor across the deposited substrate 112. Then, the drain or source region is deposited to form a segregated drain or source region which is then lC connected to an X axis conductor. Then the gate electrode is deposited so as to extend parallel to the Y axis to form a Y axis gate conductor. In this way, the field effect transistors 10, 40, 70 90, and 110 can be utilized in conjunction with PROM devices to form the isolating device in a memory circuit therefor which comprises a memory region and the isolating device.
The thin film, field effect transistor of the present invention and the various specific embodi-ments thereof described herein provide a transistorwhich is very small and yet has very good operatlng characteristics as enumerated above. The top in-sulating layer of the transistors, such as 124 in Fig. 9, can be utilized to form the insulating ~ 1 ~33~7 layer for another transistor to be formed thereon to provide a stacked transistor configuration and hence further increase the packing density of the devices. This i5 possible because the layers are deposited and because of the low operating and leakage current of the devices.
From the foregoing description it will be apparent that a thin film, field effect transistor incorporating an alloy layer of a-Si:F:H therein according to the teachillgs of the present invention has a numbee of advantages.
The planar structures of Figs. 1, 3 and 9 also can be formed in inverse order to that shown with the gate on the bottom. The Schottky barriers also can be an MIS (metal insulator semiconductor) con-tact~ Also, the gate conductor in a device can be metal, polysilicon or doped semiconductor material with a different metal or semiconductor drain ma-terial, instead of both being of the same metal or semiconductor material.
This divisional application includes subject matter disclosed and claimed in copending Canadian application 366,712.
Claims (18)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A thin film, field effect transistor device including a source region, a drain region, a gate insulator, a thin-film deposited semiconductor alloy coupled to said source region, said drain region and said gate insulator, and a gate electrode in contact with said gate insulator having a V-MOS like construction.
2. A thin film, field effect transistor of the type formed substantially in layers on a substrate, said transistor including a drain region, a gate region, a source region, a gate insulator, and a gate electrode wherein the improvement comprising:
said drain region layer formed on at least a portion of said substrate; an amorphous alloy layer formed over at least a portion of said drain region; said source region layer formed over at least a portion of said amorphous alloy layer;
at least one diagonal cut across said source region layer, said amorphous alloy layer, and said drain region layer forming a diagonally exposed surface; said gate region formed in said amorphous alloy layer, between said source layer and said drain layer; said gate insulator formed over at least a portion of said diagonally exposed surface and covering at least said alloy layer and a portion of said source layer and said drain layer; and said gate electrode in contact with at least a portion of said gate insulator adjacent to said gate region.
said drain region layer formed on at least a portion of said substrate; an amorphous alloy layer formed over at least a portion of said drain region; said source region layer formed over at least a portion of said amorphous alloy layer;
at least one diagonal cut across said source region layer, said amorphous alloy layer, and said drain region layer forming a diagonally exposed surface; said gate region formed in said amorphous alloy layer, between said source layer and said drain layer; said gate insulator formed over at least a portion of said diagonally exposed surface and covering at least said alloy layer and a portion of said source layer and said drain layer; and said gate electrode in contact with at least a portion of said gate insulator adjacent to said gate region.
3. The thin film, field effect transistor accord-ing to claim 2 wherein said drain region layer is made of an amorphous alloy that is deposited on at least a portion of said substrate; said amorphous alloy layer is formed over at least a portion of said drain alloy layer; and said source region layer is made of an amorphous alloy that is deposited on at least a portion of said amorphous alloy layer.
4. The thin film, field effect transistor accord-ing to claim 2 wherein said amorphous alloy includes sili-con and fluorine.
5. The thin film, field effect transistor accord-ing to claims 2 to 4 wherein said amorphous alloy also contains hydrogen.
6. The thin film, field effect transistor accord-ing to claims 2 to 4 wherein said amorphous alloy is a SiaFbHC wherein a is between 80 and 98, b is between 1 and 10, and c is between 1 and 10 in atomic percent.
7. The thin film, field effect transistor accord-ing to claims 2 to 4 being deposited on a metal substrate.
8. The thin film, field effect transistor accord-ing to claims 2 to 4 being deposited on a glass substrate.
9. The thin film, field effect transistor accord-ing to claims 2 to 4 being deposited on a polymer sub-strate.
10. The thin film, field effect transistor accord-ing to claims 2 to 4 having a leakage current below 10-10 amperes, a DC saturation current above 10-6 amperes, and an upper cut-off frequency above 10MHz.
11. The thin film, field effect transistor accord-ing to claims 2 to 4 being made with vapor deposition technique.
12. The thin film, field effect transistor accord-ing to claims 2 to 4 being made by glow discharge tech-nique.
13. The thin film, field effect transistor accord-ing to claims 2 to 4 wherein said transistor includes two adjacent diagonal surfaces that form a V-type structure.
14. The thin film, field effect transistor accord-ing to claim 2 wherein said drain region layer is made of a drain metal that is deposited on at least a portion of said substrate; said amorphous alloy layer is formed over at least a portion of said drain metal; said source region layer is made of a source metal that is deposited on at least a portion of said amorphous alloy layer; said diagonal cut across said source metal, said alloy layer, and said drain metal forming said diagonally exposed surface; said gate region formed in said amorphous alloy layer, between said source layer and said drain layer; said gate insulator is formed over at least a portion of said diagonally exposed surface and covering at least said alloy layer and a portion of said source layer and said drain layer; said gate elec-trode in contact with at least a portion of said gate in-sulator and adjacent to said gate region; and a passivating layer is formed over at least a portion of said source metal layer, said gate insulator and said gate electrode.
15. The thin film, field effect transistor accord-ing to claim 14 wherein said amorphous alloy includes sil-icon and fluorine.
16. The thin film, field effect transistor accord-ing to claim 15 wherein said amorphous alloy also contains hydrogen.
17. The thin film, field effect transistor accord-ing to claims 14 to 16 wherein said amorphous alloy is a SiaFbHC wherein a is between 80 and 98, b is between 1 and 10, and c is between 1 and 10 in atomic percent.
18. The thin film, field effect transistor accord-ing to claims 14 to 16 wherein said transistor includes two adjacent diagonal surfaces that form a V-type structure.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10301179A | 1979-12-13 | 1979-12-13 | |
| US06/103,011 | 1979-12-13 | ||
| US20827880A | 1980-11-19 | 1980-11-19 | |
| US208,278 | 1980-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1163377A true CA1163377A (en) | 1984-03-06 |
Family
ID=26799985
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000366712A Expired CA1153480A (en) | 1979-12-13 | 1980-12-12 | Thin film transistor |
| CA000428672A Expired CA1163377A (en) | 1979-12-13 | 1983-05-20 | Thin film transistor |
| CA000460196A Expired CA1188008A (en) | 1979-12-13 | 1984-08-01 | Thin film transistor |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000366712A Expired CA1153480A (en) | 1979-12-13 | 1980-12-12 | Thin film transistor |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000460196A Expired CA1188008A (en) | 1979-12-13 | 1984-08-01 | Thin film transistor |
Country Status (14)
| Country | Link |
|---|---|
| KR (2) | KR840001605B1 (en) |
| AU (2) | AU538008B2 (en) |
| BE (1) | BE886630A (en) |
| CA (3) | CA1153480A (en) |
| DE (2) | DE3051063C2 (en) |
| FR (1) | FR2474763B1 (en) |
| GB (2) | GB2067353B (en) |
| IE (1) | IE51076B1 (en) |
| IL (1) | IL61679A (en) |
| IT (1) | IT1193999B (en) |
| MX (1) | MX151189A (en) |
| NL (2) | NL8006770A (en) |
| SE (1) | SE8008738L (en) |
| SG (1) | SG72684G (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294796B1 (en) | 1982-04-13 | 2001-09-25 | Seiko Epson Corporation | Thin film transistors and active matrices including same |
| US5698864A (en) * | 1982-04-13 | 1997-12-16 | Seiko Epson Corporation | Method of manufacturing a liquid crystal device having field effect transistors |
| US5736751A (en) * | 1982-04-13 | 1998-04-07 | Seiko Epson Corporation | Field effect transistor having thick source and drain regions |
| FR2527385B1 (en) * | 1982-04-13 | 1987-05-22 | Suwa Seikosha Kk | THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR |
| US5365079A (en) * | 1982-04-30 | 1994-11-15 | Seiko Epson Corporation | Thin film transistor and display device including same |
| US5677547A (en) * | 1982-04-30 | 1997-10-14 | Seiko Epson Corporation | Thin film transistor and display device including same |
| US5650637A (en) * | 1982-04-30 | 1997-07-22 | Seiko Epson Corporation | Active matrix assembly |
| US4547789A (en) * | 1983-11-08 | 1985-10-15 | Energy Conversion Devices, Inc. | High current thin film transistor |
| US4620208A (en) * | 1983-11-08 | 1986-10-28 | Energy Conversion Devices, Inc. | High performance, small area thin film transistor |
| US4633284A (en) * | 1983-11-08 | 1986-12-30 | Energy Conversion Devices, Inc. | Thin film transistor having an annealed gate oxide and method of making same |
| US4543320A (en) * | 1983-11-08 | 1985-09-24 | Energy Conversion Devices, Inc. | Method of making a high performance, small area thin film transistor |
| US4752814A (en) * | 1984-03-12 | 1988-06-21 | Xerox Corporation | High voltage thin film transistor |
| US4673957A (en) * | 1984-05-14 | 1987-06-16 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
| US4769338A (en) * | 1984-05-14 | 1988-09-06 | Energy Conversion Devices, Inc. | Thin film field effect transistor and method of making same |
| US4670763A (en) * | 1984-05-14 | 1987-06-02 | Energy Conversion Devices, Inc. | Thin film field effect transistor |
| US4668968A (en) * | 1984-05-14 | 1987-05-26 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
| KR100741798B1 (en) * | 2004-12-30 | 2007-07-25 | 엘지전자 주식회사 | Washing machine with a integrated drier |
| CN112420821B (en) * | 2020-10-29 | 2021-11-19 | 北京元芯碳基集成电路研究院 | Y-shaped gate structure based on carbon-based material and preparation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3384792A (en) * | 1965-06-01 | 1968-05-21 | Electro Optical Systems Inc | Stacked electrode field effect triode |
| US4115799A (en) * | 1977-01-26 | 1978-09-19 | Westinghouse Electric Corp. | Thin film copper transition between aluminum and indium copper films |
| US4217374A (en) * | 1978-03-08 | 1980-08-12 | Energy Conversion Devices, Inc. | Amorphous semiconductors equivalent to crystalline semiconductors |
| DE2820331C3 (en) * | 1978-05-10 | 1982-03-18 | Lüder, Ernst, Prof. Dr.-Ing., 7000 Stuttgart | Thin film field effect transistor and process for its manufacture |
| GB2052853A (en) * | 1979-06-29 | 1981-01-28 | Ibm | Vertical fet on an insulating substrate |
-
1980
- 1980-12-09 DE DE3051063A patent/DE3051063C2/de not_active Expired - Fee Related
- 1980-12-09 IL IL61679A patent/IL61679A/en unknown
- 1980-12-09 DE DE3046358A patent/DE3046358C2/en not_active Expired
- 1980-12-10 GB GB8039608A patent/GB2067353B/en not_active Expired
- 1980-12-11 MX MX185169A patent/MX151189A/en unknown
- 1980-12-12 IT IT26642/80A patent/IT1193999B/en active
- 1980-12-12 KR KR1019800004728A patent/KR840001605B1/en active
- 1980-12-12 BE BE0/203147A patent/BE886630A/en not_active IP Right Cessation
- 1980-12-12 IE IE2615/80A patent/IE51076B1/en unknown
- 1980-12-12 SE SE8008738A patent/SE8008738L/en unknown
- 1980-12-12 AU AU65313/80A patent/AU538008B2/en not_active Ceased
- 1980-12-12 CA CA000366712A patent/CA1153480A/en not_active Expired
- 1980-12-12 NL NL8006770A patent/NL8006770A/en not_active Application Discontinuation
- 1980-12-12 FR FR8026402A patent/FR2474763B1/en not_active Expired
-
1983
- 1983-05-20 CA CA000428672A patent/CA1163377A/en not_active Expired
- 1983-10-06 GB GB08326775A patent/GB2131605B/en not_active Expired
-
1984
- 1984-05-21 AU AU28451/84A patent/AU554058B2/en not_active Ceased
- 1984-06-18 NL NL8401928A patent/NL8401928A/en not_active Application Discontinuation
- 1984-07-14 KR KR1019840004146A patent/KR850000902B1/en not_active IP Right Cessation
- 1984-08-01 CA CA000460196A patent/CA1188008A/en not_active Expired
- 1984-10-17 SG SG726/84A patent/SG72684G/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR850000902B1 (en) | 1985-06-26 |
| KR850001478A (en) | 1985-02-18 |
| BE886630A (en) | 1981-04-01 |
| GB2067353B (en) | 1984-07-04 |
| AU554058B2 (en) | 1986-08-07 |
| DE3051063C2 (en) | 1991-04-11 |
| SE8008738L (en) | 1981-06-14 |
| KR830004680A (en) | 1983-07-16 |
| MX151189A (en) | 1984-10-09 |
| CA1153480A (en) | 1983-09-06 |
| GB2131605B (en) | 1985-02-13 |
| CA1188008A (en) | 1985-05-28 |
| DE3046358A1 (en) | 1981-09-17 |
| FR2474763A1 (en) | 1981-07-31 |
| IT8026642A0 (en) | 1980-12-12 |
| IE51076B1 (en) | 1986-10-01 |
| IL61679A0 (en) | 1981-01-30 |
| KR840001605B1 (en) | 1984-10-11 |
| GB8326775D0 (en) | 1983-11-09 |
| IL61679A (en) | 1984-11-30 |
| GB2067353A (en) | 1981-07-22 |
| AU2845184A (en) | 1984-09-13 |
| FR2474763B1 (en) | 1987-03-20 |
| AU6531380A (en) | 1981-06-18 |
| GB2131605A (en) | 1984-06-20 |
| AU538008B2 (en) | 1984-07-26 |
| NL8006770A (en) | 1981-07-16 |
| IE802615L (en) | 1981-06-13 |
| SG72684G (en) | 1985-03-29 |
| IT1193999B (en) | 1988-08-31 |
| DE3046358C2 (en) | 1987-02-26 |
| NL8401928A (en) | 1984-10-01 |
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