CA1188008A

CA1188008A - Thin film transistor

Info

Publication number: CA1188008A
Application number: CA000460196A
Authority: CA
Inventors: Scott H. Holmberg; Richard A. Flasck
Original assignee: Energy Conversion Devices Inc
Current assignee: Energy Conversion Devices Inc
Priority date: 1979-12-13
Filing date: 1984-08-01
Publication date: 1985-05-28
Also published as: IL61679A0; MX151189A; FR2474763B1; BE886630A; AU2845184A; GB2067353B; GB2131605B; IT8026642A0; NL8401928A; FR2474763A1; KR830004680A; DE3046358A1; GB2131605A; AU538008B2; IL61679A; NL8006770A; KR840001605B1; SG72684G; SE8008738L; IT1193999B

Abstract

ABSTRACT

A thin film, field effect transistor device having a source region, a drain region, a gate insulator, a thin film deposited amorphous alloy including at least silicon and fluorine coupled to the source region, the drain region and the gate insulator and a gate electrode in contact with the gate insulator. Preferably, the amorphous alloy also contains hydrogen and is a-Sia:Fb:Hc, where a is between 80 and 98 atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent. The field effect transistor can have various geometries, such as a V-MOS-like con-struction and can be deposited on various sub-strates with an insulator substrate between the active regions of the thin film, field effect tran-sistor and a conducting substrate. The thin film, field effect transistor can have various desirable characteristics depending upon the particular geom-etry chosen and thickness of the alloy such as, for example, a DC saturation current up to or greater than 10-4 amp, an upper cut off frequency at least above 10 MHz, a high OFF resistance: ON resistance

Description

This is a divlsional applica~ion of Can~dian applicatior Serial Number 366,712 fil.ed December 12, 1980.
The p~esent invention relates to a thin ~i~m, field effect transistor, and more 5pecifical~y to thin film, field effect transistor of the type formed ~Crom an amorphous allo~ including a~ leas~
silicon and fluorine. In this respect~ reference is made to U.S. Patent No. 4,~17,374 Stan~ora R.
Ovshinsky and Masatsugu Izu entitled: ~MORPHOUS
SEMICONDUCTORS EQUIVALENT ~O CRYSTAL1INE SE~I-C~NDUCT0RS and U.S. Patent No. 4,226~8~8 Stan-1~ ford R. Ovshinsky and Arun Mad~.n, of the sametitle~
~ on is the basis OL the huge crys~allin~
semiconductor industry and is the ~aterial which is utilized in substantially all the commercial inte~
grated cir~uits now produced. When crys~a~line semic~nductor technolog~ reached a commerclal st~te, it beca~e the foundation o the present huse semi-conductor device manufacturing indus~r~. Thi~ was ~ue ~o ~he ability of the scientist to grow sub-stantially defect-free germanium and par~icularly silicQn crystals, ana then turn them in~ ex~rinsic materials with p-type and n-type conductivi~y re-gions t~erein. This was accomplis~ed by dl~fusing into such cryst~ e material parts per mi~lion o clonor (n~ or acceptor (p) dopant materials intro-duced as substitutional imp~rities in~o the sub-stantially pure crystalline materials, to increase their electric~l conductivity and to con~rol ~heir belng either o~ a p or n conduction type.
The semiconductor fabrication processes for ~aking p-n junction crystals ;nvolve extremely complex, ti~e consuming and expensive proce~ures as well as high p~ocessing temperatures, Thus, ~hese 1~ crystalline materials used in transis~ors an~ o~her curxent control device5 ar~ produced un~r very care~ully controlled conditions by growing indi-vidual single silicon or germanium crystals; where p-n junctions are require~ by doping such single cr~stals with extremely small ana critical amoun~s ~f dopantsO These crystal growing processes pro-duce relatively 5mall crystal wafers upo~ which the intecgrated ~ircuits are formed.
In wafer scale inteyration ~ech~olog~ the ~mall area crystal waer limits the overall s;~e o~
the integra~ed circ~lit which can be ~ormed thereon~
Xn applications requiring large scale ~reas, such as in the display technology, the cr~s~al wafers cannot be manufaotured with as la~ge areas as re --2~

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quired or desircd. The devices are formed~ at least in part, by difusing p or n-~ype dopants into the sub~trate. Further, each ae~ice is forTned between isolation channels which are diffuse~ into the substrate~ Packiny density gt~e nu~er ~f devices per unit area of wafe~ surace) is also limited on the silicon wafers~ because o~ the leak-age curr~nt in each device an2 the p~we~ necessary to operate the device5, each of which gene~a~e heat which is undesirable. The silic~ wafers aO n~
readily ~issipate heat. Also, ~he leakage cur~ent adversely affects the battery or poT~er cell llfe-time in portable applicati~ns~
In MOS type circuitry the swi~ching speed is related directly to ~he gate length with the sma~l es~ length havin~ the highes~ speea- The ~llïfusic~n pr~cesses, photolithograph~ and other crys alline manufacturing processes lim;t how short t~e ~ate leng~h can be ma~
~urther, the packing density ~s ex~remely imp~rtan~ because the cell size ls exponen~ially related to the cos~ c~f each de~ice . For in~ance a decLease n ~ie size by a acJcor of two results in a decrease in cost on ~he order ~f a factor o ~ix.

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Xn sumrn~ry, crystal silicon tr~ns~t:~r an~t inte~rat:ed circuit pararneters which are not vari-ahle as desired, require large amounts of material, hîgh p~ocessing temperatures, are only producible 5 only on relatively small area wa:~ers ana are expen sive ~nd time consuming to produce. Devic:es ~ased upon amorphous silicon can elimina~e these crys~l silicon dlsadvantages. Amorphou~; siïicon an be made faster, easier ~ at lower temperatu~es and ln 0 larger areas than can crystal silicon.
AccoY~in~ y, a ~onsiderable o~Eor~ has been made to develop processes for rea~ily deposit:ing amorphous semicondurtor alloys or films each of which can enc:ompass relatively large areas It i 15 desired7 limited only b~ the size O~ thf~ aepc~si~:ion equipment~ and Which could be doped 'co fc~rm p-~pe and n-type materials to orm p-n iunc~iGn tran-s3.5tox 5 and devices super ior in cost ~nd~r opera-tion to those produced by their c:rys~alline co~
20 terparts~ Fox many ~ears ~iuch work was subs;~an--tiall~ unp~oduc~ive~ Amorphou~i si~lcon or germa--nium tGroup ~V~ f ilms are rlormally four-ï~ld co ordinated and were founa ~co ha~Te micro~roi~ls an~
dangling lbonds and o~her defects whic:h produce a ~`:

hi~h density of localiæed states in the e.~erg~ gap thereo~. The presence of a high densi~y of local-ized states in the energy gap of ~morphous silicon semiconductor films resulted in such films not beîng successfully doped vr otherwise modified t~
shift the ~ermi level close ~o the conducti~n or valence bands maki~g them unsuitable for making p-n junctions for ~ransistors and other current control device appl ications.
n In an attempt to minimize the aoremen~ionea pro~lems involved with amorphous silicon an~ ger-~aniu~, W.E. Spear and P. G. Le Com'~e~ ~ Carnegie Laboratory of Physics~ University of Dundee~ ;n Dundee, Scotland did some work on "'Substitutional ~oping of Amorphous Silicon", as repQrted in a paper publishe~ in Solid State Communications, V~l~
17 t pp~ 1193-1195, 1975, toward the en~ o~ reducing the local ized state5 in the energy gap in amo~pho~us silicon or germanium to make the same appr~a~ima~:e 20 more closely intrinsi :: cr~7stalline 5i:1Licon or ger-maniurn and of substitutionally dopin~ the amorphous materials with suitable c:lassic dopan~s j, as în doping cr~stalline Itlaterlals~ to make t~em ex~rirD--sic and of p or n conduction types,, The reduction o the localized states was , acomplished by glow discharye ~eposition of arnor-phous sil icon f ilms wherein a gas silane SS;H4 ) was passed throuyh a reaction tube where the gas was S decompose~ by an r ~ f . glow aischarge ana depc~si~:ea orl a substrate a~ a suhstrate te~nperature o about 5~0-60UK ~27-32~C). The material sc~ deposi~e~l on the substrate was an intrinsic amorE~olls ma~e rial consisting of silicon an~l hydroyen. To pro--1~ duce amorphous material a gas ~ phosphine ~PH
for n-type conducti~n or a gas ~ ~di~c,r~ne ~B2~6~
for p-type conduction were premixed with ~he silane gas and passed through the glow ~ischarge reactlon tube under the same operating conditions The 15 g~seous concentration o~ the dopants use~l was be-tween about 5 x 10-~ and lD-2 parts per volume~
he material so deposite~l inclu~ied supposedlLy ~;ub-s~itutional phosphorus or boron aopan~ and wa~;
shown tc3 be extrinsic and of n or p con~uc~ion 20 type..
While it wa~ n~t known by ~hese research~rs~
it is now ~cnown by th~ work o~ o~hers ~hal~ the hydrogen in the silane combines at an ~ptimum l~e~n-perature with many of the aangling bOnas of th ~~; ~

,~

c~o~
silicon during the glow discharge deposition~ to substantiall~ reduce the density of the locali~ed s~a~es in the ener~y gap toward the end of m~kin~
the electronic properties of the amorphous mater;al 5 approximate more nearly those of the corresponding crystalline material.
D~I~ Jones, W.E. Spear, P.G. heComber, S, Li J
and R. Martins also worked on preparing a~Ge~R from GeH4 using similar deposition techni~ues. The ma,erial o~tainea gave evidence o a high densi~y of localized sta~es in the energy gap thereof.
Al~hough the material could be doped the efficiency was substantially reduced from that obtainable with a-Si~I. In this work reported in Philosophical ~agaz~ne B. Vol. 39, p. 147 ~}9793 the authors conGlude that because of the large densit~ of ~ap states t.he material obtalned is "~ . ~ a less a~-tracti~e material than a-Si or dopin~ experiments and possi~le applications."
The incorporation ~f hydrogen in the above ~ilane Method not only has limi~.ations based upon the fixed ratio o hydrogen to silicon 1~ silane, ~ut, most importantly, various Si:H bonaing con-~igu~a~ions int~oduce new antibonding s~ates whic~

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can h~ve aeleterious corlsequences in t~ese mate-rials. ~herefore, there are basic limitations in reduclng the density of localized states in these materials which are particularly harm~ul in terms of ef~ective p as well as n doping. ~he resulting density of states of the silane d~posited materials lea~s to a narrow depletion width which in turn limits the efficiencies of devices whose operation depends on the dri~t of ~ree carriers. The method o~ making these materlals by the use of only sil-icon ~nd ~ydrog~n also r~sults i~ a high density o~
surface states which a~fects all the ~bo~e param-eters.
After the development of the glow disc~ar~e 1~ ~ep~si~ion of silicon from silane gas was car~ied ou~, work was done on the sputter deposltion of amorphous silicon ~ilms in the atmosphere ~f a mix~ure of argon ~required ~ ~he s~u~tering ~e-pDSi~io~ process~ and molecular hydrogen, ~o deter-~0 mine the re5ults of such mole~ular hydrogen on thecharacteristics of the deposited amorphous silic~n film. ~his research indicated that the hydrogen ac~ea as a c~mpensating agent which bon~ed in such a wa~ as to reduce the localized states in the energ~ ~ap. However, the degree to which the lo~
cali~ed states in the energy gap were reduced in the sputter deposition process was much less than that achieved ~y the silane deposition pro-ess described above. The above described p and n dop-ant m~terials also were in~roduced in ~he spu~-tering process to produce p and n doped materials.
These materials had a low.er doping efficiency than th~ materials produced in the glow dischar~e pro-cess. Neither process produced ef~icient p-doped materials with sufficiently high acceptor con-centrations or producing commercial p n junc~ion ~evices. The n-doping efficiency was below des}r-able acceptable commercial levels and the p-doping was particu~arly undesirable since it in~reased the number of localized states in the band ~ap~
Various methods of fabrication and col-struc-~ion of thin film transistors and devices have been proposed wherein the various films o~ the tran-sis~or are made of different materials having di-erent electrical characteristics, For exampl~, thin ilm transistors have been propos~d utilizing nickel oxide ilms, silicon ~ilms, amorphous si~--icon ilms and amorphous silicon and hydroge~l fil~.~s _9_ i ~ormed from silane as above ~entioned. ~150, va~i-ous geometrical configurations have been proposed such as a planar-MOS construction.
~'he prior deposition of amorphous silicon~
which has been altered by hydro~en from ~he silane ~as in an attempt to ~a~e it more closely resemble crystalli~e silicon and which has been doped in a mannex like hat of doping crystalline silicon, has charac~eris~ics which in all impor~ant respects are inferior to ~hose of doped crystalline silicon. As rep~r~ed by Le Comber and Spear and others refer-enced above, in the silane based transistor devices the leakage current may be as low as 10~1~ ampPres, t.he saturation cu~rent appears to be ~bout 5 x 10 1~ am~eres~ the device switchin~ requency appears ~o ~e about 104 ~x and the stability is pOQr ~ince the material degrades with time.
~ t has been proposed to ma'~e a solar cell which is essentially a photosen~itive rectiier

2~ u~iliæ;ng an amorphous alloy including silicon and ~luorine in the aforementioned U~Sr Patent No.
4~2~7O374~ issued ~ /83 for Amorphous Semicon-duct~r Equivalen~ to Cr~s~alline Semiconductors, Stanft:srd R~ Ovshirisky and ~lasatsugu ~zu and U. S .

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Patent No. 4,276,898, issued lO/7/80 of the same title, Stanford R. Ovshinsky and Arun Madan.
We have found that these disadvantages may be overcome by providing a thin filmJ field effect transistor formed from a silicon, fluorine, and hydrogen amorphous alloy in various constructions. These transistors provide very low leakage currents, fast switching speeds, high OFF resistance; ON
resistance ratios, and do not degrade with time. We also provide a new and improved V-MOS thin film, field efect transistor formed from the above amorphous alloy.
According to the present invention there is provided a thin film, field effect transistor device including a source region, a drain region, a gate insulator, a thin-film deposited semiconductor alloy coupled to the source region, the drain region and the gate insulator, and a gate electrode in contact with the gate insulator having a V-MOS like construction.
Preferably~ the amorphous alloy also contains hydrogen, such as an amorphous alloy a-Sia:Pb:H where a is between 80 and 98 atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.

The :Eield effec~ transistor c~n have various geometries including a V-MOS like constLUctiOn of the invention and can be depos;ted on various sub-strates with an insulator between the ac~ive re-5 gic)ns o~ the thin film, field effect ~ransistvr anda cc~rlaucting substrate such as a meltal.. The tran-sistor6 can ~e ~leposi`ted on an insulator ~ a semi~
conf3uctor D an insulaJced metal ~r ar~ insula~ea semi-conductr:r subs'crate. ~3ecause o~E the capability to ~t3 ~e iEormed on various substra~es and the low leakage and operating current t the transisto~s also can be ~ormed on top of one another, i.e. r st~cked.
The t~in ~ilm, ~ield efec~ lcransistor ~::an h~ve ~axious desirable charac'ceristics depending 1~ ~pc~n the pa~ticular geometry c:hosen ~nd thickness of thP ilm of amorphous silicon 1uorine material ~:ho~ien suclh as, iEo~ example, ~ DC satul atic?n cur-rent as low as 10-~ ampe~es and up to or grea~er ~han 10-4 amperes~ an upper cut off frequency a~
leas~ above 1~ MHz~ a high OF~` resis~ance:ON resis~
~ance ~atio of about 10~, and a vPry l~sY leakage current o~ about 10-1~ amps or less. Fur~her, the al31oy does not degrade with time4 The preferred ~mbodimellt of this inventior-will now he described by way of exarnple~ with re-ference to the drawings accompanying this specii-ca~ion in which:
~igO 1 is a vertical sectional view ~f one embo~iment of thin film deposited, ~iela e~fect transistor ~ade in accordance with the teachings ~f the presen~ in~ention and havin~ metal s~urce and drain ~e~ions similar to a planar MOS-type tran-sis}or~
Fig~ ~ is a schemat;c circuit ~ia~ram of the transistor shown in Fig. 1.
~ 'ig. 3 is a ver~ical sectional view throug~ a se~cnd em~o~imen~ of a tllln film dep~sited~ field 15 ~eXec~ transistor similar to ~he transistor shown in Fig. 1, having semiconductor source and ~rain regions.
~ igO 4 is a schematic circuit diagram of the transist~r shown in ~ig. 3~

Fig. 5 is a vertical sectional vi~w ~f another em~odiment of thin ~ilm deposited, field effect ~ransistor similar to the transistor sh~wn in ~ig.
1, having metal source and drain regions similar to a V-MOS-type transistor.
Fi~. 6 is a schematic circuit dia~ram of the ~ransistox shown in ~ig. S.
~ ig. 7 is a vertical sectional view through a secon~ em~odiment of a thin film deposited~ field e~fec~ transistor similar to the transistor shown in Fig. 5~ having semiconductor source an~ ~raîn regions.
Fig. 8 is a schematic cirouit diagram o ~he transistor shown in Fig. 7.
1~ Fig. 9 is a vertical sectional view through a ~hin film deposited, field effect transistor~ ~im-ilar in function to the transis~ors shown in Fi~s.
1-8 ~ut havin~ a a;fferent ~eometrical construc-~ ~11..
- ~erring now to the figures in greater de-tail~ ~here is illustrated in ~ thin film~
iel~ effec~ transistor 10 made in accordance with the teachings o the present invention. As shown, ~h~ t~ansistor 10 is formed on a substrate 12 of ¢3~3 insulating materi~l which eould be a silicon mate-`ri~l, a layer ~f polymer material ~r an insulator on top of a metal. ~eposited on the substrate 12 in accordance with the teachings of the present invention is a thin alloy layer 14 including sil~
icon and ~lu~rine which can also contain ~yaro~en and which can be doped to form an ~ or P type al~
loy. On top of this alloy layer 14 is a layer or ~and 16 o insulating material such as a ~ield 1~ oxide and s~aced therefrom is ano~her layer or band 18 of insulating material such as a field oxide.
A channel or opening 2n is formed, as by con-vention~l ph~tolithography techniques, bet~leen the two ~ands 16 and 18. A source metal condLIctor ~2 is deposited over the band lG ~lith a portion there o~ in contact with the alloy layer 14 to form a S~hottky barrier contac~ at the in~er~ace ~etween t~ s~urce metal 22 and the amorphous alloy layer 14 ~
:20 In a similar manner a c::onductor or layer 24 of drzln me~al is deposited over the insulating band 18 with a por~ion thereof in s:~ontact with t~e alloy layer 14 spaced from the source metal 22 . ~he in terface between the drain me~al 24 and the am~r-~15-phous layer 1~ creates another Schottky barrier COllt~Ct~ A ~ate insulator layer 26 of insulating material such as gate oxide ox gate nitride 26 is deposited over the source metal 22 and drain metal 2~ and in contact with the amorphous alloy laye~ 14 be~ween the source and drain ~etal, On thîs layer ~ ~f gate insulating materi~l is ~ep~sited a gate con~uc~or 28 which can be made of any suita~le metal such as aluminum or molybdenum. On the yate ~0 conductor ar.other layer 30 o insulating material is ~eposited to passivate the devl e, which is identified as a ~ield oxide.
The insulating layers 16 and 30 would be join-e~ before the next adjacent transistor wit~ the ~urce 22 connected to an ex~ernal conductor, ~he insulating layer 16 forms the insula~or or ~he next device similar to the insulato~ ~8 of the tran~;stor 10 shown.
~he gate insulator layer 26 and the bands 1~
~0 and 18 of insulating material referxed to as being a field ~xide can be made of a metal o~;de, silicon dioxlde or o~her insulator such as silicon nitride.
The source me~al 2~ and drain metal 24 can be form-e~ of any suitable conductiYe metal such as alumi-num~ molybdenum or a high work :Eunction metal such as gol~ m~ platinum ~r chromium. T}le ga~e insul~tor can be a nitride r sili~on dioxide ~r silioon nitride material.
In accordance Wi~}l the ~eachings of ~he pre--sent invention, an alloy containin~ silic~n ans~
f l uorirle which can also c:ontain hyarogen i5 Uti--lized 3~or forming the amorphous alloy la~yer 1~.
~his ~lloy provide~ the desirable chara:::ter~s~ics enumerated before which can be u~iîized :Ec3r m~ny di:~feren~ circuits. The alloy ~ a~er 14 is pre--:Eeliably made of a Sia~ H~ where ~ is between 80 and ~ atomlc percellt, ~ is betwee~ 1 an~ 10 atomic peroent and c is between 1 and 1~ atomic percen~.
1~ The alloy can be doped with a ~dopan'c r~m { roup V DX /Group III of t31e Periodic ~able ma~e rials in an amount constituting between lt) a~ :LUOû
parts per million (ppm~. The ~opan~ rna~erials and ~mQ-ln~ c) doping ca2 Yary.
~he thickness of ~che alloy l~er 1~ oiE amor-phol~s mater ial can be between 1~0 and SQ~ Ang--stroms, one ~hickness utiliæed bein~ ~pproximate15r lOn~ Angstroms The source me'cal 2;~ an~ ~he arain metal 2~ can alsc~ have thicknesses ranging fJ:om ~00 --17 ~

to 2D ,noo Angstroms with one utilized thickness being of appro~imately 20no ~ngstroms. The ~ate conductor 2~ although described as be.ncl Inaae ~f metal~ c~n be made of a doped ~emicon~uctor mate-rial i~ desired.
Depending upon the geometry of the various layPrs and thicknesses of the variou~ layers~ a fiela effect transistor can be constructed as de-scribed ab~ve wherein the leakage curren~ i5 ap-1~ proximat~ly 10-11 amperes thereby t~ pr~vi~e ~ high OF~ resistance and a DC saturation curren~ of ap-proxima~ely 10-4 amperes.
~ n constructing the thin film~ fiel~ ~f~ect transistor 1~ shown in Fig. 1~ the layers of mate-rial~ and particular~y the alloy layer 14, aredeposited by various deposition techniques, pre-~r~b~y ~y ~low disch~rge~
A conventional schematic g~e ~ source ~S3 and drain (D~ cir~ult diagram of ~he ~iela e~fec~

2~ transistor 10 is illustrate~ in ~ig~ 2 ~ e~errin~ now to ~ig. 3p there is illus~ra~e~
a pl~nar constructed thln film~ ~iel~ e~fect ~ran-sistor 40 which~ like the transls~or 10, is formed on an insulated su~strate ~ayer 42^ ~n ~op o~ t~e substrate mate~ial 42 is deposi~ed, such as by ~low ..~ischarge, an alloy layer q~ including silicon ana fluorine which also preferably includes hydrogen an~ can be of the N or P type. On this alloy layer 5 ~4 are deposited two layers of insulatin~ mate~lal 46 and ~8 which are referred to in ~ig. 3 as bei~
mad2 vf a field oxide with an ~pening 50 f~rmea therebetween. Ab~ve the insulatin~ layers ~ ~n~
~ are depvsited, respectively, a source all~y 1~ layer 52 and a drain alloy layer 54 which also include silicon and fluorine and pr~ferably inciude~
hydrogen~ The source 52 and ~he drain al~oy 5~ are M ~r P type amorphous alloys. An N-P or P-~ ~unc-$ion ~s then formed at the interface where ~e la~ers 52 and 54 ~a~e contact wi~h ~he alloy l~yer

4~.
~fter depositing the l~yers ~2 and 54, a ga~e insulator layer 56 referred t~ as a ~ate oxide 56 is deposlted ove~ the source region 52, ~he expose~
. 20 por~ion of the amorphous layer 44 an~ t~e ~rain region $4~ ~he~ a ga~e conauctor 58 i5 ~eposite~
over the gate insulator ~ and a passivating insu-- lating layer 6~ is dep~sited on ~op ~ the y~te conductor 5$, ldenti~ied as a fiel~ oxiae ( ~ conventional schem~tic ~ate ~G), s~urce (5) and drain 5D) oircuit di~gram o the transist~r 40 is illustra~ed in Fi~ 4.
'~he diference between the transis~or ~ an~
the transistor 10 is that the drain and s~urce regions or conduc~ors 52 and 54 o the ~ransis~or 40 are mad~ of a semicon~uc~or ma~erial ana prefer-ably an a-Si:~ H alloy.
In ~ig. ~ there is illustra~ea a new ~~~OS
like construction illustrated in a ~hin ~ilm~ ield e~fect transistor 70 made in accor~ance with t~e t~achings of the presen~ invention~ On a subst~ra~e layer 72 is irst aeposited a layer or band o~
drain metal 74 which has a central por~ion thereof cut o.r e~ched away. On top of ~he ~r~in me~al 74 is dep~sited a thin la~er or band o~ amorphous alloy ~ which has a central por~;on cut o~ etched away aligned with ~he cut away portio~ o layer 74.
5imilarly, a layer of source metal 78 iæ ~epos- te~
~n the layer 76 and a correspon~ln~ central p~r~i~n thereo is cut awa~. Alternately~ all the layers can be etchea in one step following the ~epQs;tion of all the layers. Then a oate ins~la~or 8n re-ferred to as a gate oxide is depositea over ~he source metal 78 and into the resulti~ cen~ra~ ~-c:ut space 8~ and onto the inclinea ed~e5 of the layer portions ~4, 76 and 78 and over the ~xposed substrate 72. Then a gate conductor 84 is de-

5 posited on the gate insulator 8~ and a la~er ~6 ofinsulating material identified as a ~Eield oxide is dep~sited over the gate metal c~n~uctor 84 as a passiva~ing layer.
This particular V-MOS like construc~ion wit}
10 the open space 80 has the advan~a~e ~ha~ a very short aistance I. is esta13lishe~ bPCc~Jeen ~e source metal 74 and the drain metal 7~ ~hrc-gh ~he all~
layer 76.. The layer thic:kness or distance L re-sults in a high operating fre~uency, and a higher 15 saturatlon s::urrex)t than the transi~tor con:Eigu-ration of :~igs. :1 and 3. The leakage curren~: ma~
increase over the conf ig~lra~:ion o:E l~igs~ 1 and 3 ,.
A a::onventional schematic: ~a~e ~ J ~;ource tS~
and drain (D3 diagram of the transistor 70 is shown 20 in Fig. 60 ~ n ~ig. 7 is illustrate~l ano~her ~-MOS like thin film, field efect ~ransistor 9~1 for~nea on a substrate 9 2 with al1oy 1ayers 94 O- 9 6 and 98 havin~
silicc)n ana fluorine (N or P type~ deposited on the ~ 3~

substrate 92. ~he respective la~ers 9~ 7 96 ~r.~ 98 have a central portion 100 cut or etched awa~
the~eof. ~hen a gate insulator 102 identified as a gate oxide is dep~sitea over the e~e of ~he layer S g8 and contacts the exp~sed edyes o~ the l~yers 94, 96, and 98 and also the exposed p~r~ion vf the substrate 92 as shown. A g~te conduc~or 1~4 is deposite~ over the insula~or layer 1~2 an~ las~ly a la~7er 106 of insula~ing m~ter;al, such as a iel~
10 oxi.de ,. is deposited over the gate conduc~or ~ ~4.
~he transistor 90 operates uciliæing ~he oppositely ~iased P-N junct:ions formed be~ween layers 9~ an~l 96 and between 96 and 9~. .
~he transistor 90 is similar to ~he ~ransistor lS 70 as shown in Fig. S except tha~ ~he source re~ion 9$ and drain region 94 is maae o~ a semlconductor alloy, such as a-$i:F:H. ~he ~J-~OS like con~;tru tion of th~ inverltion illus~ra'cea by 'cransi~tors 7Q
and 90 is advantageously utilized with ~n~ ~epos-~0 ited semiconduetor ~aterial, sue~ as ~u~ ~o~ o~ly asilicon alloy containing at leas~ ~ydrogen as de-p~sited from silane~
A eonventi~nal schematie eireult ~ia~ram ~f the transistor 90 is illu~tra~e~ in ~igO 8 -2~-.

c~

Referring now to Fig. 9, there is illustr~ted therein another field efect transistor 110 maae in accordance wi~h the teachings o ~he presen~ inven~
~ion. The transistor 110 is formed on ~ me~a7 substrate 111 which has deposited ~hereon a t~in layer o insulating material 112 which sepa~a~es the active components o the transistor 110 from the ~netal ~ubstrate 111 and yet is thi~ enough so that heat generated in the transistor 110 can flow 1~ to the metal substrate which forms a hea~ sink therefor~
The thin film, field effec~ transistor 110 is fo~med by depositing a source con~uctor layer 114 made o~ metal or N or P type semiconductor ~lloy~
A drain conductor 116 is aeposite~ on the insu-latin~ layer 11~ and also is made of a meta~ or ~ P
ox N t~pe semiconductor alloy. On top of t.he con-ductors 114 and 116 is deposited an intrin~ic or lightly doped alloy layer 118; such ~s the a Si~
~0 alloy previously described, On top o~ ~he alloy layer 118 i5 ~eposite~ a gate lnsulator 120 which c~n be a silicon oxide or a silicon nitride. On top of the gate insula~
i5 ~eposited a ~a~e conductor la~er 122 w~ich -~3-OF~

can be a metal or semiconductor materi~l~ A pas-.. sivatin~ layer 1~ is deposited over the g~te ~on-duc~or 1~.
The various transistors 10~ 40, 70, 9~ an~
110 san be formed in a ma~rix so that either the source or drain reyion ex~ends as a Y axis con-~uctor across the deposited substra~e ~12. Thenr t~.e drain or source region is depo5i~ed to orm a segregated drain or source region ~hich is ~en connected to an X axis conductor~ Then the ~ate electxode is deposited so as to extena parallel ~he Y ax;s ~o form a ~ a~is ga~e conauctor, In this wayr the field effect transis~ors 10, 40~ 70D
90, and 110 can be utilized in coniunction with 1~ P~OM ~evic~s to form the isola~in~ dev;ce in a memory circuit therefor which compr;se~ a memo~y region and the isola~ing device~
The thin film~ field effe~t transist~r o the present inven~io~ and the vaxious speci~ic embodi-ments thereof described herein proviae a ~ransi~tor which is very small and ye~ has ~ery goo~ operating characteristlcs as enumeratea above. The top ins-sula~ing layer of the transistor53 such as 124 in Fi~o 9~ can be utilize~ to fvrm ~he ~nsula~ing -2~-~,, l~y~ Eor another transistor to be formea ~hereon to provide a ~tacked transistor configura~ion an~
hence urther increase the packing ~ensity of the devices. ~his is possible bec~use the layers a~e deposited and because of the low operatin~ an~
leakage current ~ the devices.
From the ~regoing description it will be apparent that a thin film; field effe~ transistor incorporating an alloy layer o a-Si,~ herein 1~ according to the teachings of the presen~ invention has a number of advantages, ~ h~ planar structures of Figs. 1~ 3 and 9 also can be foxmed in inverse order to t~at sh~wn with the gate on the ~ottom. The Scho~ky barriers also can ~e an MIS lmetal insulator semiconduc~or~ c~n-tact. Also~ the ~ate conductor in a device ~an ~e metal, polysilicon or doped semiconduc~or material with a ~ifferent metal or semicon~uc~or ~rain ma-terial, instead o~ both being of ~he same me~al or 2~ semiconductor material.
This divisional application includes su~j~ct matter disclosed and claimed in co~ending Cana~ian application 366,7120

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE
DEFINED AS FOLLOWS:

1. A thin film, field effect transistor device including a source region, a drain region, a gate insulator, a thin-film deposited semicon-ductor alloy coupled to said source region, said drain region and said gate insulator, and a gate electrode in contact with said gate insulator having a V-MOS like construction.

2. A transistor device according to claim 1, wherein the V-MOS like construction includes the source region and the drain region being positioned one above the other, and vertically arrayed with respect to a substrate, and the deposited semiconductor alloy extending between and in contact with the source region and the drain region, and wherein the gate insulator and the gate electrode are positioned to apply an electric field to the semiconductor alloy between the source region and the drain region to cause electrical conduction therebetween

3. A transistor device according to claim 2, wherein the deposited semiconductor is an n-type semiconductor.

4. A transistor device according to claim 2, wherein the deposited semiconductor is an amorphous alloy.

5. A transistor device according to claim 4, wherein the alloy includes fluorine.

6. A transistor device according to claim 4, wherein the alloy includes silicon and hydro-gen.

7. A transistor device according to claim 6, wherein the alloy has the empirical formula SiaFbHC wherein a is between 80 and 98, b is between 1 and 10, and c is between 1 and 10 in atomic percent.

8. A transistor device according to claim 2, wherein the drain, and the source regions are deposited materials.

9. A transistor device according to claim 8, wherein the drain region is a p-type semicon-ductor.

10. A transistor device according to claim 8, wherein the drain region is a metal or an amorphous alloy.

11. A transistor device according to claim 8, wherein the source region is a p-type semicon-ductor.

12. A transistor device according to claim 8, wherein the source region is a metal or an amorphous alloy.

13. A transistor device according to claim 8, wherein the deposited semiconductor has a thickness of between 100 and 5,000 angstroms.

14. A transistor device according to claim 8, wherein the drain region has a thickness of between 500 and 20,000 angstroms.

15. A transistor device according to claim 8, wherein the source region has a thickness of between 500 and 20,000 angstroms.

16. A transistor device according to claim 8, wherein the gate insulator comprises an oxide layer.

17. A transistor device according to claim 16, wherein the gate insulator is a deposited layer.

18. A transistor device according to claim 8, wherein the drain region is deposited on the substrate, and extends as a y-axis conductor across the substrate to an adjacent thin film, field effect transistor device; an x-axis conduc-tor extends from another adjacent thin film, vertical field effect transistor device to the source; and the gate electrode extends horizon-tally parallel to the y-axis to an adjacent, thin film, vertical field effect transistor.

19. A transistor device according to claim 8, comprising a covering insulating layer and a further thin film, vertical field effect transis-tor device stacked on top of the first transistor device.

20. A thin film, field effect transistor of the type formed substantially in layers on a sub-strate, said transistor including a drain region, a gate region, a source region, a gate insulator, and a gate electrode wherein the improvement com-prising:

said drain region layer formed on at least a portion of said substrate; an amorphous alloy layer formed over at least a portion of said drain region; said source region layer formed over at least a portion of said amorphous alloy layer; at least one diagonal cut across said source region layer, said amorphous alloy layer and said drain region layer forming a diagonally exposed surface;
said gate region formed in said amorphous alloy layer, between said source layer and said drain layer; said gate insulator formed over at least a portion of said diagonally exposed surface and covering at least said alloy layer and a portion of said source layer and said drain layer; and said gate electrode in contact with at least a portion of said gate insulator adjacent to said gate region.

21. The thin film, field effect transistor according to claim 20, wherein said drain region layer is made of an amorphous alloy that is depos-ited on at least a portion of said substrate; said amorphous alloy layer is formed over at least a portion of said drain alloy layer; and said source region layer is made of an amorphous alloy that is deposited on at least a portion of said amorphous alloy layer.

22. The thin film, field effect transistor according to claim 20, wherein said amorphous alloy includes silicon and fluorine.

23. The thin filmy field effect transistor according to claims 20 to 22, wherein said amor-phous alloy also contains hydrogen.

24. The thin film, field effect transistor according to claims 20 to 22, wherein said amor-phous alloy is a SiaFbHc wherein a is between to and 98, b is between 1 and 10, and c is between 1 and 10 in atomic percent.

25. The thin film, field effect transistor according to claims 20 to 22, being deposited on a metal substrate.

26. The thin film, field effect transistor according to claims 20 to 22, being deposited on a glass substrate.

27. The thin film, field effect transistor according to claims 20 to 22, being deposited on a polymer substrate.

28. The thin film, field effect transistor according to claims 20 to 22, having a leakage current below 10-10 amperes, a DC saturation cur rent above 10-6 amperes, and an upper cut-off fre-quency above 10MHz.

29. The thin film, field effect transistor according to claims 20 to 22, being made with vapor deposition technique.

30. The thin film, field effect transistor according to claims 20 to 22, being made by glow discharge technique.

31. The thin film, field effect transistor according to claims 20 to 22, wherein said tran-sistor includes two adjacent diagonal surfaces that form a V-type structure.

32. The thin film, field effect transistor according to claim 20, wherein said drain region layer is made of a drain metal that is deposited on at least a portion of said substrate; said amorphous alloy layer is formed over at least a portion of said drain metal; said source region layer is made of a source metal that is deposited on at least a portion of said amorphous alloy layer; said diagonal cut across said source metal, said alloy layer, and said drain metal forming said diagonally exposed surface, said gate region formed in said amorphous alloy layer, between said source layer and said drain layer; said gate in-sulator is formed over at least a portion of said diagonally exposed surface and covering at least said alloy layer and a portion of said source layer and said drain layer; said gate electrode in contact with at least a portion of said gate in-sulator and adjacent to said gate region; and a passivating layer is formed over at least a por-tion of said source metal layer, said gate insula-tor and said gate electrode.

33. The thin film, field effect transistor according to claim 32, wherein said amorphous alloy includes silicon and fluorine.

34. The thin film, field effect transistor according to claim 33, wherein said amorphous alloy also contains hydrogen.

35. The thin film, field effect transistor according to claims 32 to 34, wherein said amor-phous alloy is a SiaFbHC wherein a is between 80 and 98, b is between 1 and 10, and c is between 1 and 10 in atomic percent.

36. The thin film, field effect transistor according to claims 32 to 34, wherein said tran-sistor includes two adjacent diagonal surfaces that form a V-type structure.