JP3266185B2 - Method for manufacturing polycrystalline semiconductor thin film - Google Patents

Method for manufacturing polycrystalline semiconductor thin film

Info

Publication number
JP3266185B2
JP3266185B2 JP09522398A JP9522398A JP3266185B2 JP 3266185 B2 JP3266185 B2 JP 3266185B2 JP 09522398 A JP09522398 A JP 09522398A JP 9522398 A JP9522398 A JP 9522398A JP 3266185 B2 JP3266185 B2 JP 3266185B2
Authority
JP
Japan
Prior art keywords
thin film
polycrystalline semiconductor
semiconductor thin
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP09522398A
Other languages
Japanese (ja)
Other versions
JPH11274080A (en
Inventor
国弘 塩田
純一 半那
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP09522398A priority Critical patent/JP3266185B2/en
Publication of JPH11274080A publication Critical patent/JPH11274080A/en
Application granted granted Critical
Publication of JP3266185B2 publication Critical patent/JP3266185B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は,多結晶半導体薄膜
の製造方法に関し,詳しくは,低温で形成されるポリシ
リコン(poly−Si)等の多結晶半導体薄膜の製造
方法に関する。
The present invention relates to a method for manufacturing a polycrystalline semiconductor thin film, and more particularly, to a method for manufacturing a polycrystalline semiconductor thin film such as polysilicon (poly-Si) formed at a low temperature.

【0002】[0002]

【従来の技術】主に液晶表示装置(LCD)のスイッチ
ング素子として開発・実用化されてきたアモルファスシ
リコンTFTの高性能化・高精細化および,ガラス基板
上への回路形成実現のために,トランジスタの活性層に
多結晶シリコンを用いた多結晶シリコン薄膜電界効果型
トランジスタ(以下,poly−Si TFTと呼ぶ)
が開発されている。
2. Description of the Related Art Transistors are used mainly for improving the performance and definition of amorphous silicon TFTs, which have been developed and put into practical use as switching elements of liquid crystal display devices (LCDs), and for realizing circuits on glass substrates. Polycrystalline silicon thin film field effect transistor using polycrystalline silicon for the active layer (hereinafter referred to as poly-Si TFT)
Is being developed.

【0003】多結晶シリコンは,結晶材料であるため
に,非晶質材料であるアモルファスシリコンに比べて移
動度が100倍程度高いという利点を備えている。
Since polycrystalline silicon is a crystalline material, it has an advantage that its mobility is about 100 times higher than that of amorphous silicon which is an amorphous material.

【0004】一般的な,poly−Si TFTの製造
工程は,次の通りである。まず,基板であるガラス上に
SiO2 膜を形成し,次に,LPCVDでアモルファス
シリコン層を形成する。次に,このアモルファスシリコ
ン層を結晶化するためにエキシマレーザーでアニールを
行い多結晶シリコン層を形成する。
[0004] A general process for manufacturing a poly-Si TFT is as follows. First, an SiO 2 film is formed on glass as a substrate, and then an amorphous silicon layer is formed by LPCVD. Next, in order to crystallize the amorphous silicon layer, annealing is performed with an excimer laser to form a polycrystalline silicon layer.

【0005】次に,エッチングで各TFT素子ごとに分
離し,さらにゲートSiO2 層,ゲート電極の順に形成
した後で,イオン注入法やイオンドーピング法を用いて
ソース及びドレイン領域を形成する。最後に配線を形成
しTFTが完成する。
Next, after separating each TFT element by etching and forming a gate SiO 2 layer and a gate electrode in this order, source and drain regions are formed by ion implantation or ion doping. Finally, wiring is formed to complete the TFT.

【0006】このようにTFTは,数々の工程を経て形
成されるが,その特性,主に電界効果移動度を決定する
のは活性層を形成する多結晶シリコン層の結晶性であ
る。この場合の結晶性とは,多結晶半導体薄膜を構成す
る各結晶のシリコン原子の配置が単結晶シリコンのそれ
にどれだけ近いかという意味はもちろんあるが,それ以
外に粒径サイズや表面の平坦性という内容も含む。
As described above, a TFT is formed through a number of steps, and its characteristics, mainly the field effect mobility, are determined by the crystallinity of the polycrystalline silicon layer forming the active layer. The crystallinity in this case means, of course, how close the arrangement of silicon atoms of each crystal constituting the polycrystalline semiconductor thin film is to that of single crystal silicon, but also the grain size and surface flatness. Including the contents.

【0007】この種の技術としては,特開平5−315
269号公報(以下,従来例1と呼ぶ)には,Sin
2n+2(n=1〜3)とGeF4 とを用いてGeを主成分
とする多結晶シリコンゲルマニウム(poly−SiG
e)薄膜を形成する方法が開示されている。
As this kind of technology, Japanese Patent Application Laid-Open No. 5-315
No. 269 (hereinafter referred to as Conventional Example 1) discloses that Si n H
Using 2n + 2 (n = 1 to 3) and GeF 4 , polycrystalline silicon germanium (poly-SiG
e) A method for forming a thin film is disclosed.

【0008】従来例1に開示の方法では,基板温度=3
00〜450℃条件の選択によりSiの混入あるいは合
金の生成を抑えGeエピタキシャル薄膜を成長するもの
である。
In the method disclosed in Conventional Example 1, the substrate temperature = 3
The selection of the condition of 00 to 450 ° C. suppresses the incorporation of Si or the formation of an alloy to grow a Ge epitaxial thin film.

【0009】また,特開平62−73624号公報(以
下,従来例2と呼ぶ)には,原料ガスSi2 6 ,Ge
4 からプラズマ化学相蒸着法によりアモルファスシリ
コンゲルマニウムを形成する方法が開示されている。
Japanese Patent Application Laid-Open No. 62-73624 (hereinafter referred to as Conventional Example 2) discloses that the raw material gases Si 2 H 6 , Ge
Method of forming the amorphous silicon germanium are disclosed by the F 4 plasma chemical deposition method.

【0010】また,特開平7−235490号公報(以
下,従来例3)には,基板上に30nm〜50nmの非
晶質シリコンを形成し,350〜500℃でアニールし
た後でエキシマレーザーアニールを照射することにより
多結晶シリコン薄膜を形成する方法が開示されている。
Japanese Patent Application Laid-Open No. 7-235490 (hereinafter referred to as Conventional Example 3) discloses that excimer laser annealing is performed after forming amorphous silicon of 30 nm to 50 nm on a substrate and annealing at 350 to 500 ° C. A method for forming a polycrystalline silicon thin film by irradiation is disclosed.

【0011】さらに,特開平5−182923号公報
(以下,従来例4)には,基板に非晶質シリコンを形成
し,非晶質シリコン内に不対結合手を多量に形成させる
ために,非晶質シリコンの結晶化温度以下の温度で加熱
アニールした後,エキシマレーザーアニールを照射する
ことにより,結晶性が高くしかもレーザーのエネルギー
密度に対する依存性が小さく,さらに均一性に優れた多
結晶シリコン薄膜を形成する方法が開示されている。
Japanese Patent Application Laid-Open No. 5-182923 (hereinafter referred to as Conventional Example 4) discloses that amorphous silicon is formed on a substrate and a large number of dangling bonds are formed in the amorphous silicon. Heat annealing at a temperature lower than the crystallization temperature of amorphous silicon, and then irradiating with excimer laser annealing, polycrystalline silicon with high crystallinity, small dependence on laser energy density, and excellent uniformity A method for forming a thin film is disclosed.

【0012】[0012]

【発明が解決しようとする課題】しかしながら,従来例
1においては,poly−Si(Ge)薄膜形成を行っ
ているが,成膜したpoly−Si(Ge)薄膜に関し
て,面配向と,粒径サイズを制御することに関しては,
全く開示されていない。
However, in the conventional example 1, a poly-Si (Ge) thin film is formed. However, with respect to the formed poly-Si (Ge) thin film, the plane orientation and the particle size As for controlling the
Not disclosed at all.

【0013】また,従来例2において,プラズマ化学相
蒸着法を用いてアモルファスシリコンゲルマニウムを堆
積しており,多結晶半導体薄膜を得るためには,上述し
たように,追加のアニール工程を有するという欠点を備
えている。
Further, in the conventional example 2, the amorphous silicon germanium is deposited by using the plasma chemical vapor deposition method, and as described above, an additional annealing step is required to obtain a polycrystalline semiconductor thin film. It has.

【0014】また,同様に,従来例3においても,非晶
質の薄膜を基板上に形成した後,レーザーアニールを行
うという点で,レーザーアニール工程以前において,基
板加熱する必要があり,このために工程数が増加すると
いう欠点を有する。
Similarly, also in the conventional example 3, since the amorphous thin film is formed on the substrate and then the laser annealing is performed, it is necessary to heat the substrate before the laser annealing step. And the number of steps is increased.

【0015】また,従来例3においては,多結晶半導体
薄膜の面方位や結晶粒径を大きく制御することについて
は,全く触れられていない。
Further, in the third conventional example, there is no mention of controlling the plane orientation and the crystal grain size of the polycrystalline semiconductor thin film to a large extent.

【0016】さらに,従来例4においても,非晶質薄膜
を基板上に形成した後にレーザーアニールを行うという
工程を用いており,多結晶半導体薄膜を得るためには,
レーザーアニール等の工程の時間がかかるとともに,基
板の加熱工程を有するという工程数がかかるという欠点
を有している。
Further, also in Conventional Example 4, a process of performing laser annealing after forming an amorphous thin film on a substrate is used. To obtain a polycrystalline semiconductor thin film,
It has the drawbacks that it takes a long time to perform steps such as laser annealing and the number of steps of heating the substrate.

【0017】また,従来例4においては,結晶性薄膜の
面配向を制御したり,結晶粒径を大きく制御することに
ついては,全く述べられていない。
Further, in the conventional example 4, there is no mention of controlling the plane orientation of the crystalline thin film or controlling the crystal grain size largely.

【0018】要するに,従来LPCVDで形成したアモ
ルファスシリコンをエキシマレーザーでアニールした場
合,シリコン原子の配置が単結晶シリコンのそれにどれ
だけ近いかという意味での結晶性は,非常に良好なもの
を得ることができる。
In short, when amorphous silicon formed by conventional LPCVD is annealed by an excimer laser, a very good crystallinity in terms of how close the arrangement of silicon atoms is to that of single crystal silicon is obtained. Can be.

【0019】そこで,さらに高移動度なTFTを実現す
るために,粒径サイズが5000〜10000オングス
トローム(以下,Aで示す)と比較的大きく表面の平坦
性が良好な多結晶半導体薄膜を実現するためには,数十
〜数百回のレーザースキャンが必要であった。これで
は,処理能力が低くなるために,量産用技術としては不
適当である。
Therefore, in order to realize a TFT with higher mobility, a polycrystalline semiconductor thin film having a relatively large particle size of 5,000 to 10,000 angstroms (hereinafter referred to as A) and excellent surface flatness is realized. For this purpose, tens to hundreds of laser scans were required. This is unsuitable for mass production technology because the processing capacity is low.

【0020】[0020]

【0021】そこで、本発明の一つの技術的課題は,多
結晶半導体薄膜の面配向や結晶粒径を制御することがで
きる多結晶半導体薄膜の製造方法を提供することにあ
る。
[0021] Accordingly, one technical object of the present invention is to provide a method for producing a polycrystalline semiconductor thin film capable of controlling the plane orientation and crystal grain size of the polycrystalline semiconductor thin film.

【0022】[0022]

【課題を解決するための手段】本発明によれば,基板面
上に多結晶半導体膜を直接形成する薄膜形成工程を有す
る多結晶半導体薄膜の製造方法であって、前記薄膜形成
工程は、Si −GeF 系反応性熱CVDプロセ
スであり、反応圧力が0.5〜0.8Torrである
と特徴とする多結晶半導体薄膜の製造方法が得られる。
According to Means for Solving the Problems] The present invention, having a thin film forming step of directly forming a polycrystalline semiconductor film on a substrate surface
A method for producing a polycrystalline semiconductor thin film, comprising:
The process is a Si 2 H 6 -GeF 4 based reactive thermal CVD process.
A scan method of the polycrystalline semiconductor thin film reaction pressure and this <br/> and features a 0.5~0.8Torr is obtained.

【0023】[0023]

【0024】[0024]

【0025】[0025]

【0026】[0026]

【0027】[0027]

【0028】[0028]

【0029】[0029]

【0030】[0030]

【0031】[0031]

【0032】[0032]

【0033】[0033]

【0034】[0034]

【0035】[0035]

【0036】[0036]

【発明の実施の形態】本発明の実施の形態を述べる前
に,本発明について更に,具体的に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, the present invention will be described more specifically.

【0037】本発明では,ガラス基板等を使用した半導
体装置である薄膜電界効果トランジスタ(TFT)の製
造工程において,高性能なデバイス特性つまり高移動度
なTFTを実現するような多結晶半導体薄膜を形成する
ために,予め基板上に多結晶半導体薄膜を形成し,さら
にその薄膜をエキシマレーザーによってアニールするこ
とで,少ない回数のレーザーアニールで高品質な多結晶
半導体薄膜を得る方法である。
According to the present invention, in a manufacturing process of a thin film field effect transistor (TFT) which is a semiconductor device using a glass substrate or the like, a polycrystalline semiconductor thin film realizing high performance device characteristics, that is, a TFT having high mobility is realized. In this method, a polycrystalline semiconductor thin film is formed on a substrate in advance, and the thin film is annealed with an excimer laser to obtain a high-quality polycrystalline semiconductor thin film by a small number of laser annealings.

【0038】さらに,より具体的には,レーザーアニー
ル前に予め多結晶半導体薄膜を形成する方法として次に
示す工程を用いている。
More specifically, the following steps are used as a method of forming a polycrystalline semiconductor thin film before laser annealing.

【0039】まず,Si2 6 とGeF4 の酸化還元反
応及びGeF4 のエッチング性を利用することで,He
をキャリアガスとして450℃という,比較的低温で多
結晶半導体薄膜が成長する。この時のSi2 6 とGe
4 及びHeの流量比は,実施の形態においては,2.
5:0.1:500を用いたが,好ましい範囲として
は,これらの流量比は,(2.0〜2.5):(0.0
8〜0.13):(450〜500)である。
First, by utilizing the oxidation-reduction reaction between Si 2 H 6 and GeF 4 and the etching property of GeF 4 , He
Is used as a carrier gas to grow a polycrystalline semiconductor thin film at a relatively low temperature of 450 ° C. At this time, Si 2 H 6 and Ge
In the embodiment, the flow ratio of F 4 and He is set to 2.
5: 0.1: 500 was used, but as a preferable range, these flow ratios are (2.0-2.5) :( 0.0
8 to 0.13): (450 to 500).

【0040】薄膜の成長プロセスを,成膜初期に結晶核
が発生する段階と発生した結晶核を選択的に成長させて
連続膜にする段階という2段階に分けることで,基板表
面から薄膜表面までの粒径サイズが均一で,その粒径自
体も任意のサイズに制御された多結晶半導体薄膜が形成
される。
The process of growing a thin film is divided into two stages: a stage in which crystal nuclei are generated in the initial stage of film formation and a stage in which the generated crystal nuclei are selectively grown to form a continuous film. Is formed, and the polycrystalline semiconductor thin film is formed in which the particle size itself is controlled to an arbitrary size.

【0041】この核発生段階の成膜圧力を0.45To
rr以下にすることで,結晶核の面方位が(111)優
先配向となり,最終的な多結晶半導体薄膜の面方位も
(111)優先配向となることから,表面のラフネスが
少ない多結晶半導体薄膜が形成される。
The film forming pressure in this nucleation stage is set to 0.45 To
By setting it to be equal to or less than rr, the plane orientation of the crystal nucleus becomes the (111) preferential orientation, and the plane orientation of the final polycrystalline semiconductor thin film also becomes the (111) preferential orientation. Is formed.

【0042】この多結晶半導体薄膜を使ってレーザーア
ニールすると,初めから比較的表面の平坦な膜を使用す
るためにレーザーアニール後の膜も平坦な表面となり,
また(111)面という隣り合った結晶同士の2次的結
晶成長が最も起こりやすい面に優先的に配向しており,
それぞれの粒径サイズも1000〜1500Aと比較的
大きくなっているために,レーザーアニール後の粒径も
大きなものが得られる。
When laser annealing is performed using this polycrystalline semiconductor thin film, a film having a relatively flat surface is used from the beginning, so that the film after laser annealing also has a flat surface.
Also, the (111) plane is preferentially oriented to the plane where the secondary crystal growth of adjacent crystals is most likely to occur,
Since each particle size is relatively large, such as 1000 to 1500 A, a large particle size after laser annealing can be obtained.

【0043】それでは,本発明の実施の形態について説
明する。
Next, an embodiment of the present invention will be described.

【0044】(第1の実施の形態)本発明の第1の実施
の形態では,as−depoで結晶性薄膜が形成可能な
Si2 6 −GeF4系反応性熱CVDにより多結晶半
導体薄膜を形成した後にエキシマレーザーでアニールす
る。この多結晶半導体薄膜を形成する際に,結晶核発生
及び密度制御→核成長という2段階のプロセスを用い
る。また,多結晶シリコン薄膜電界効果型トランジスタ
ー(以下,poly−Si TFTと呼ぶ)では,その
活性層を多結晶シリコン(以下,poly−Siと呼
ぶ)で構成している。
(First Embodiment) In a first embodiment of the present invention, a polycrystalline semiconductor thin film is formed by reactive thermal CVD of a Si 2 H 6 -GeF 4 system capable of forming a crystalline thin film as-depo. After the formation, annealing is performed with an excimer laser. In forming this polycrystalline semiconductor thin film, a two-step process of generating crystal nuclei and controlling density → nucleus growth is used. In a polycrystalline silicon thin film field effect transistor (hereinafter, referred to as a poly-Si TFT), the active layer is formed of polycrystalline silicon (hereinafter, referred to as poly-Si).

【0045】本発明の第1の実施の形態による多結晶半
導体薄膜の製造方法を一般的な作業手順に沿って図面に
より具体的に説明する。
The method for manufacturing a polycrystalline semiconductor thin film according to the first embodiment of the present invention will be described in detail with reference to the drawings along with a general operation procedure.

【0046】図1はSiO2 10の成膜が終了した基板
の断面図である。図2はSiO2 /Si基板を示す図で
ある。図3乃至図6は,図2に示すSiO2 /Si基板
上に,0.4Torr〜1.0Torrの間での各反応
圧力で夫々成膜した場合の多結晶半導体薄膜の粒子構造
を示す走査型電子顕微鏡写真である。また,図7は,反
応圧力の違いによるゲルマニウム含有多結晶シリコン
(以下,poly−Si(Ge)と呼ぶ)薄膜の成膜の
状態について示す図である。図8は,図7における核発
生段階における反応圧力と核密度およびそれぞれの核が
そのまま成長した場合の粒径サイズの関係を示す図であ
る。図9は図3乃至図6に示した薄膜のX線回折プロフ
ィールを示す図である。図10は図7で示した選択成長
条件で成膜したpoly−Si(Ge)薄膜の粒子構造
を示す断面走査型電子顕微鏡写真である。
FIG. 1 is a cross-sectional view of a substrate on which SiO 2 film formation has been completed. FIG. 2 is a view showing a SiO 2 / Si substrate. FIGS. 3 to 6 are scans showing the particle structure of the polycrystalline semiconductor thin film when formed on the SiO 2 / Si substrate shown in FIG. 2 at each reaction pressure between 0.4 Torr and 1.0 Torr. It is a scanning electron microscope photograph. FIG. 7 is a diagram showing a state of forming a germanium-containing polycrystalline silicon (hereinafter, referred to as poly-Si (Ge)) thin film due to a difference in reaction pressure. FIG. 8 is a diagram showing the relationship between the reaction pressure and the nucleus density in the nucleation stage in FIG. 7 and the particle size when each nucleus grows as it is. FIG. 9 is a view showing an X-ray diffraction profile of the thin film shown in FIGS. FIG. 10 is a cross-sectional scanning electron micrograph showing the particle structure of a poly-Si (Ge) thin film formed under the selective growth conditions shown in FIG.

【0047】図1を参照すると,ガラス基板11上には
膜厚約5000AのSiO2 10が形成されており,こ
のSiO2 10は原料ガスにSi2 6 とO2 を用いた
LPCVDで成されている。具体的には,まず,原料ガ
スにSi2 6 とGeF4 を用いた反応性熱CVD(以
下,Si2 6 −GeF4 系反応性熱CVDと呼ぶ)に
よって,基板温度450℃でSiO2 上にSi組成比が
95%以上のpoly−Si(Ge)薄膜を成膜する。
この場合,キャリアガスとしてHeを用い,各原料ガス
及びキャリアガスの流量比はSi2 6 :GeF4 :H
e=2.2:0.1:500とする。
Referring to FIG. 1, an SiO 2 film 10 having a thickness of about 5000 A is formed on a glass substrate 11, and this SiO 2 10 is formed by LPCVD using Si 2 H 6 and O 2 as source gases. Have been. Specifically, first, a reactive thermal CVD using Si 2 H 6 and GeF 4 as source gases (hereinafter, referred to as a Si 2 H 6 -GeF 4 system reactive thermal CVD) is performed at a substrate temperature of 450 ° C. to form SiO 2. A poly-Si (Ge) thin film having a Si composition ratio of 95% or more is formed on 2 .
In this case, He is used as the carrier gas, and the flow ratio of each source gas and the carrier gas is Si 2 H 6 : GeF 4 : H
e = 2.2: 0.1: 500.

【0048】図2に示す単結晶Si基板に成長した熱S
iO2 層をパターニングすることで,基板表面にSi面
が露出している部分21とSiO2 面で覆われている熱
SiO2 層20の部分があるSiO2 /Si基板に,p
oly−Si(Ge)薄膜を成膜し,0.4Torr〜
1.0Torrの間での各反応圧力における成膜の粒子
構造は,図3乃至6に示されている。
The thermal S grown on the single-crystal Si substrate shown in FIG.
By patterning the iO 2 layer, the SiO 2 / Si substrate having a portion 21 where the Si surface is exposed on the surface of the substrate and a portion of the thermal SiO 2 layer 20 which is covered with the SiO 2 surface is formed.
Poly-Si (Ge) thin film is formed, and 0.4 Torr ~
The particle structure of the film at each reaction pressure between 1.0 Torr is shown in FIGS.

【0049】図7に示すように,成膜圧力が低い状態か
ら徐々に,略0.48Torr及び略0.9Torrを
境界部として,選択成長→核発生→非選択成長という3
段階の成長プロセスに変化する。
As shown in FIG. 7, from the state where the film formation pressure is low, gradually growing at about 0.48 Torr and about 0.9 Torr as boundaries, selective growth → nucleation → non-selective growth.
Changes to a staged growth process.

【0050】図8に示すように,反応圧力によって,核
密度は,1E+9〜1E+11(cm-2)の間で変化す
る為,核発生圧力をコントロールすることで核密度を制
御することが可能となり,これは言い換えると200〜
2000Aの間で粒径サイズの制御が可能であるという
ことになる。たとえば粒径サイズが1500Aの核密度
は5E+10(cm-2)をとり,このような薄膜を得る
ためには,反応圧力0.55(Torr)で成膜する必
要があるということになる。
As shown in FIG. 8, since the nucleus density varies between 1E + 9 and 1E + 11 (cm −2 ) depending on the reaction pressure, it is possible to control the nucleus density by controlling the nucleation pressure. , This is 200 ~
It means that the particle size can be controlled between 2000A. For example, the core density of a particle size of 1500 A is 5E + 10 (cm -2 ), and in order to obtain such a thin film, it is necessary to form a film at a reaction pressure of 0.55 (Torr).

【0051】また,図9に示すように,結晶核の面方位
は,反応圧力によって(220)優先配向から(11
1)優先配向の間で変化し,前述したように反応圧力
0.55(Torr)で成膜した場合には(111)優
先配向になる。図10のpoly−Si(Ge)薄膜の
粒子構造を示す断面透過型電子顕微鏡(TEM)写真を
参照すると,図9を用いた説明において結晶核が発生し
た後に,引き続いて図7で示した選択成長条件で成膜し
た場合,粒径サイズは1000〜1500Aとなり,核
密度から逆算した粒径サイズとほぼ一致している。
As shown in FIG. 9, the plane orientation of the crystal nuclei changes from (220) preferential orientation to (11) depending on the reaction pressure.
1) The orientation changes between the preferred orientations, and when the film is formed at the reaction pressure of 0.55 (Torr) as described above, the orientation becomes the (111) preferred orientation. Referring to a cross-sectional transmission electron microscope (TEM) photograph showing the particle structure of the poly-Si (Ge) thin film in FIG. 10, after the generation of crystal nuclei in the description using FIG. 9, the selection shown in FIG. When the film is formed under the growth condition, the particle size is 1000 to 1500 A, which is almost the same as the particle size calculated from the core density.

【0052】このようにして成膜したpoly−Si
(Ge)薄膜を用いて,エキシマレーザーでアニールす
ると,粒径が非常に大きく表面の平坦なpoly−Si
(Ge)薄膜が得られる。これは,レーザーアニールす
る前のpoly−Si(Ge)膜が,表面が平坦で2次
的な結晶成長を最も起こしやすい(111)優先配向の
膜であり,粒径も1000〜1500Aという比較的大
きなサイズであったことに起因している。
The poly-Si film thus formed
When a (Ge) thin film is annealed with an excimer laser, poly-Si having a very large particle size and a flat surface is obtained.
(Ge) A thin film is obtained. This is because the poly-Si (Ge) film before laser annealing is a (111) preferentially oriented film having a flat surface and most likely to cause secondary crystal growth, and has a relatively small grain size of 1000 to 1500 A. This is due to the large size.

【0053】以上,説明したように,本発明の第1の実
施の形態においては,レーザーアニール前の材料とし
て,粒径サイズが1500A程度で,その構造が(11
1)優先配向に制御されたpoly−Si(Ge)薄膜
を成膜温度450℃で形成することで,レーザーアニー
ル後に粒径サイズが大きくて表面の平坦な薄膜を安価な
ガラス基板面上に形成することができる。
As described above, in the first embodiment of the present invention, as a material before laser annealing, the particle size is about 1500 A and the structure is (11).
1) By forming a poly-Si (Ge) thin film controlled at a preferred orientation at a deposition temperature of 450 ° C., a thin film having a large grain size and a flat surface is formed on an inexpensive glass substrate after laser annealing. can do.

【0054】(第2の実施の形態)本発明の第2の実施
の形態では,as−depoで結晶性薄膜が形成可能な
Si2 6 −GeF4 系反応性熱CVDにより多結晶半
導体薄膜を形成した後にエキシマレーザーでアニールす
る。この多結晶半導体薄膜を形成する際に,結晶核発生
及び密度制御→核成長という2段階のプロセスを用いる
が,核成長の際に基板表面とガスの流れる向きとのなす
角度を90〜0度の任意の角度で固定する。
(Second Embodiment) In a second embodiment of the present invention, a polycrystalline semiconductor thin film is formed by reactive thermal CVD of a Si 2 H 6 -GeF 4 system capable of forming a crystalline thin film as-depo. Is formed and then annealed with an excimer laser. When forming this polycrystalline semiconductor thin film, a two-stage process of generating crystal nuclei and controlling the density → nucleus growth is used, and the angle between the substrate surface and the gas flow direction during the nucleus growth is 90 to 0 degrees. Fixed at any angle.

【0055】本発明の第2の実施の形態による多結晶半
導体薄膜の製造方法を図面を用いて具体的に説明する。
A method for manufacturing a polycrystalline semiconductor thin film according to the second embodiment of the present invention will be specifically described with reference to the drawings.

【0056】図11(a),(b),及び(c)は核成
長の際に基板表面とガスの流れる向きのなす角度を夫々
90〜0度の間(90度,45度,0度)で変化させて
固定する方法の説明に供せられる図である。また,図1
2(a),(b),及び(c)は,図11(a),
(b),及び(c)の方法を用いた場合の核発生及び各
成長のプロセスを概略的に示す図である。さらに,図1
3は,ガス〜基板表面角度とアスペクト比(a/b)と
の関係を示す図である。
FIGS. 11 (a), 11 (b) and 11 (c) show the angle between the substrate surface and the direction of gas flow during nucleus growth between 90 and 0 degrees (90, 45 and 0 degrees, respectively). 7) is a diagram which is provided for describing a method of fixing by changing in FIG. Also, FIG.
2 (a), (b) and (c) correspond to FIGS.
It is a figure which shows schematically the process of nucleation and each growth in the case of using the method of (b) and (c). Furthermore, FIG.
FIG. 3 is a diagram showing a relationship between gas and substrate surface angle and aspect ratio (a / b).

【0057】ガラス基板上にpoly−Si(Ge)薄
膜を形成する際に,原料ガス及びキャリアガスの流量比
をSi2 6 :GeF4 :He=2.2:0.1:50
0〜600の割合とし,基板温度450℃,反応圧力
0.5〜0.8Torrの条件で核発生を行う。
When forming a poly-Si (Ge) thin film on a glass substrate, the flow ratio of the source gas and the carrier gas is set to Si 2 H 6 : GeF 4 : He = 2.2: 0.1: 50.
Nucleation is performed under the conditions of a substrate temperature of 450 ° C. and a reaction pressure of 0.5 to 0.8 Torr at a ratio of 0 to 600.

【0058】次に,図11(a),(b),及び(c)
に示すように,ガスノズル82から原料ガスのSi2
6 及びGeF4 とキャリアガスとを供給する向きを,矢
印83で示すように基板表面81から0〜90度の範囲
で固定し核成長を行う。この場合の成膜温度,原料ガス
及びキャリアガスの流量比は核発生時の条件と同じに
し,成膜圧力は1Torr以下とする。
Next, FIGS. 11 (a), (b) and (c)
As shown in, the raw material gas from the gas nozzle 82 Si 2 H
6 and GeF 4 and the supply direction of the carrier gas are fixed within a range of 0 to 90 degrees from the substrate surface 81 as indicated by an arrow 83 to perform nucleus growth. In this case, the film forming temperature, the flow ratio of the source gas and the carrier gas are the same as the conditions at the time of nucleation, and the film forming pressure is 1 Torr or less.

【0059】本発明の第2の実施の形態においては,表
面にすでに核が存在する基板に成膜すると,図12
(a),(b),(c)及び図13に示すように,基板
表面92と原料ガスの流れる向きとの角度が小さくなる
に従って,縦方向への成長量に対する横方向への成長量
の割合が大きくなる。つまり結晶核91の成長モード
が,等方的なものから横方向へ優先的なものに変化す
る。この横方向へ優先的な成長モードで成膜すると,非
常に薄い膜厚で大きな粒径サイズの薄膜を成長するとい
う等方的な成長モードでは不可能であった薄膜成長が可
能となる。
In the second embodiment of the present invention, when a film is formed on a substrate having a nucleus already present on the surface, FIG.
As shown in (a), (b), (c) and FIG. 13, as the angle between the substrate surface 92 and the flowing direction of the source gas becomes smaller, the growth amount in the horizontal direction with respect to the growth amount in the vertical direction is reduced. The percentage increases. That is, the growth mode of the crystal nuclei 91 changes from an isotropic mode to a preferential mode in the lateral direction. If a film is formed in this laterally preferential growth mode, it becomes possible to grow a thin film which is impossible in an isotropic growth mode in which a thin film having a very small thickness and a large grain size is grown.

【0060】図12に示すように,等方的な成長モード
で結晶93の粒径サイズが2000Aの薄膜を成長する
場合,膜厚は1000A以上必要になってしまうが,横
方向へ優先的な成長モードで成膜を行うと,500A程
度の薄膜で粒径サイズ2000Aというような薄膜の成
長が可能となる。
As shown in FIG. 12, when growing a thin film having a crystal grain size of 2000 A in the isotropic growth mode, the film thickness needs to be 1000 A or more, but preferentially in the lateral direction. When the film is formed in the growth mode, it is possible to grow a thin film having a particle size of 2000 A with a thin film of about 500 A.

【0061】このようにして成膜したpoly−Si
(Ge)薄膜を用いてエキシマレーザーでアニールする
と,膜厚が非常に薄くて粒径が非常に大きく表面の平坦
なpoly−Si(Ge)薄膜が得られる。この薄膜を
用いて成膜したTFTは活性層の薄膜化により,従来以
上の高速動作が可能となる。
The poly-Si film thus formed
When a (Ge) thin film is annealed with an excimer laser, a poly-Si (Ge) thin film having a very thin film thickness, a very large particle size and a flat surface is obtained. A TFT formed using this thin film can operate at a higher speed than before by thinning the active layer.

【0062】以上説明したように,本発明の第2の実施
の形態においては,レーザーアニール前のpoly−S
i(Ge)成膜における選択成長の段階において,原料
ガス,キャリアガスの流れる向きを基板表面に対して0
〜90度の範囲で固定することで,500A程度の薄膜
で2000A以上という大粒径サイズの薄膜形成が可能
となる。この膜を使用してレーザーアニールを行いTF
Tを作ると,活性層の薄膜化による容量の低下により,
従来以上の高速動作が可能となる。
As described above, in the second embodiment of the present invention, the poly-S
At the stage of selective growth in i (Ge) film formation, the flow direction of the source gas and the carrier gas is set to 0 with respect to the substrate surface.
By fixing in the range of up to 90 degrees, a thin film having a large particle size of 2000 A or more can be formed with a thin film of about 500 A. Laser annealing is performed using this film and TF
When T is made, the capacitance decreases due to the thinning of the active layer,
Higher speed operation than before becomes possible.

【0063】[0063]

【発明の効果】以上説明したように、本発明によれば
多結晶半導体薄膜の面配向や結晶粒径を制御することが
できる多結晶半導体薄膜の製造方法を提供することがで
きる。
As described above, according to the present invention ,
Controlling plane orientation and crystal grain size of polycrystalline semiconductor thin film
A method for manufacturing a polycrystalline semiconductor thin film that can be provided can be provided.

【0064】[0064]

【図面の簡単な説明】[Brief description of the drawings]

【図1】SiO2 10の成膜が終了した基板の断面図で
ある。
FIG. 1 is a cross-sectional view of a substrate on which deposition of SiO 2 has been completed.

【図2】SiO2 /Si基板を示す図である。FIG. 2 is a view showing a SiO 2 / Si substrate.

【図3】図2に示すSiO2 /Si基板上に,0.4T
orrの反応圧力で成膜した場合の多結晶半導体薄膜の
粒子構造を示す走査型電子顕微鏡写真である。
FIG. 3 shows a 0.4 T film on the SiO 2 / Si substrate shown in FIG.
3 is a scanning electron micrograph showing the particle structure of a polycrystalline semiconductor thin film when formed at a reaction pressure of orr.

【図4】図2に示すSiO2 /Si基板上に,0.6T
orrの反応圧力で成膜した場合の多結晶半導体薄膜の
粒子構造を示す走査型電子顕微鏡写真である。
FIG. 4 shows a 0.6T film on a SiO 2 / Si substrate shown in FIG.
3 is a scanning electron micrograph showing the particle structure of a polycrystalline semiconductor thin film when formed at a reaction pressure of orr.

【図5】図2に示すSiO2 /Si基板上に,0.8T
orrの反応圧力で成膜した場合の多結晶半導体薄膜の
粒子構造を示す走査型電子顕微鏡写真である。
FIG. 5 is a diagram showing a method of forming 0.8T on the SiO 2 / Si substrate
3 is a scanning electron micrograph showing the particle structure of a polycrystalline semiconductor thin film when formed at a reaction pressure of orr.

【図6】図2に示すSiO2 /Si基板上に,1.0T
orrの反応圧力で成膜した場合の多結晶半導体薄膜の
粒子構造を示す走査型電子顕微鏡写真である。
In [6] SiO 2 / Si substrate shown in FIG. 2, 1.0 T
3 is a scanning electron micrograph showing the particle structure of a polycrystalline semiconductor thin film when formed at a reaction pressure of orr.

【図7】反応圧力の違いによるPoly−Si(Ge)
薄膜の成膜の状態について示す図である。
FIG. 7: Poly-Si (Ge) due to difference in reaction pressure
It is a figure showing about the state of film formation of a thin film.

【図8】図7における核発生段階における反応圧力と核
密度およびそれぞれの核がそのまま成長した場合の粒径
サイズの関係を示す図である。
8 is a diagram showing a relationship between a reaction pressure and a nucleus density in a nucleus generation stage in FIG. 7 and a particle size when each nucleus grows as it is.

【図9】薄膜の反応圧力の違いによる優先配向の変化を
示すX線回折プロフィールである。
FIG. 9 is an X-ray diffraction profile showing a change in preferred orientation due to a difference in reaction pressure of a thin film.

【図10】図7で示した選択成長条件で成膜したpol
y−Si(Ge)膜の粒子構造を示す断面走査型電子顕
微鏡写真である。
FIG. 10 shows a pol film formed under the selective growth conditions shown in FIG.
It is a cross-sectional scanning electron microscope photograph which shows the particle structure of a y-Si (Ge) film.

【図11】(a)は核成長の際に基板表面とガスの流れ
る向きの角度を90度に固定した方法の説明に供せられ
る図である。(b)は核成長の際に基板表面とガスの流
れる向きの角度を45度に固定した方法の説明に供せら
れる図である。(c)は核成長の際に基板表面とガスの
流れる向きの角度を0度に固定した方法の説明に供せら
れる図である。
FIG. 11 (a) is a view used to explain a method in which the angle between the gas flow direction and the substrate surface is fixed to 90 degrees during nucleus growth. FIG. 4B is a diagram which is used for describing a method in which the angle between the substrate surface and the gas flowing direction is fixed to 45 degrees during nucleus growth. (C) is a diagram provided for explaining a method in which the angle between the substrate surface and the flowing direction of the gas is fixed to 0 degree during nucleus growth.

【図12】(a)は図11(a)の核発生及び核成長の
プロセスを概略的に示す図である。(b)は図11
(b)の核発生及び核成長のプロセスを概略的に示す図
である。(c)は図11(c)の核発生及び核成長のプ
ロセスを概略的に示す図である。
FIG. 12 (a) is a view schematically showing a process of nucleation and growth of FIG. 11 (a). (B) is FIG.
It is a figure which shows schematically the process of nucleation and nucleus growth of (b). (C) is a figure which shows roughly the process of the nucleation and nucleus growth of FIG.11 (c).

【図13】ガス〜基板表面角度とアスペクト比(a/
b)との関係を示す図である。
FIG. 13 shows gas to substrate surface angle and aspect ratio (a /
It is a figure which shows the relationship with b).

【符号の説明】[Explanation of symbols]

10 SiO2 11 ガラス基板 20 熱SiO2 層 21 Si面 81 基板表面 82 ガスノズル 83 ガスの流れる向き 91 結晶核 92 基板表面 93 結晶10 SiO 2 11 glass substrate 20 thermal SiO 2 layer 21 Si surface 81 substrate surface 82 flows gas nozzle 83 gas direction 91 crystal nuclei 92 substrate surface 93 crystals

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平9−8319(JP,A) 特開 平2−148831(JP,A) 特開 平3−159116(JP,A) 特開 平8−264440(JP,A) 秋季第58回応用物理学会学術講演会講 演予稿集(1997)4p−YD−2 秋季第58回応用物理学会学術講演会講 演予稿集(1997)4p−YD−3 (58)調査した分野(Int.Cl.7,DB名) H01L 21/20 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-9-8319 (JP, A) JP-A-2-14831 (JP, A) JP-A-3-159116 (JP, A) JP-A 8- 264440 (JP, A) Autumn 58th Annual Meeting of the Japan Society of Applied Physics Proceedings (1997) 4p-YD-2 Autumn 58th Annual Meeting of the Japan Society of Applied Physics Abstracts (1997) 4p-YD-3 (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/20

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板面上に多結晶半導体膜を直接形成す
る薄膜形成工程を有する多結晶半導体薄膜の製造方法で
あって、前記薄膜形成工程は、Si −GeF
反応性熱CVDプロセスであり、反応圧力が0.5〜
0.8Torrであること特徴とする多結晶半導体薄膜
の製造方法。
1. A method for manufacturing a polycrystalline semiconductor thin film having a thin film forming step of directly forming a polycrystalline semiconductor film on a substrate surface.
In addition, the thin film forming step is performed based on a Si 2 H 6 -GeF 4 system.
It is a reactive thermal CVD process and the reaction pressure is 0.5 to
A method for producing a polycrystalline semiconductor thin film, wherein the pressure is 0.8 Torr .
JP09522398A 1998-03-25 1998-03-25 Method for manufacturing polycrystalline semiconductor thin film Expired - Fee Related JP3266185B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09522398A JP3266185B2 (en) 1998-03-25 1998-03-25 Method for manufacturing polycrystalline semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09522398A JP3266185B2 (en) 1998-03-25 1998-03-25 Method for manufacturing polycrystalline semiconductor thin film

Publications (2)

Publication Number Publication Date
JPH11274080A JPH11274080A (en) 1999-10-08
JP3266185B2 true JP3266185B2 (en) 2002-03-18

Family

ID=14131759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09522398A Expired - Fee Related JP3266185B2 (en) 1998-03-25 1998-03-25 Method for manufacturing polycrystalline semiconductor thin film

Country Status (1)

Country Link
JP (1) JP3266185B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4456341B2 (en) * 2003-06-30 2010-04-28 株式会社日立国際電気 Semiconductor device manufacturing method and substrate processing apparatus
JP5152827B2 (en) 2007-03-22 2013-02-27 株式会社日立製作所 THIN FILM TRANSISTOR AND ORGANIC EL DISPLAY DEVICE USING THE SAME
JP4892579B2 (en) * 2009-03-30 2012-03-07 株式会社日立国際電気 Manufacturing method of semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
秋季第58回応用物理学会学術講演会講演予稿集(1997)4p−YD−2
秋季第58回応用物理学会学術講演会講演予稿集(1997)4p−YD−3

Also Published As

Publication number Publication date
JPH11274080A (en) 1999-10-08

Similar Documents

Publication Publication Date Title
JP3306258B2 (en) Method for manufacturing semiconductor device
US6835608B2 (en) Method for crystallizing amorphous film and method for fabricating LCD by using the same
JP2616741B2 (en) Method for manufacturing polycrystalline silicon-germanium thin film transistor
JP2000036465A (en) Single-crystal thin-film transistor manufactured through transition metal continuous transfer method
JPH07321323A (en) Thin film transistor and its manufacturing method
US20100041214A1 (en) Single crystal substrate and method of fabricating the same
US6326226B1 (en) Method of crystallizing an amorphous film
JP2505736B2 (en) Method for manufacturing semiconductor device
JP3357707B2 (en) Method for manufacturing polycrystalline semiconductor film and method for manufacturing thin film transistor
JP3266185B2 (en) Method for manufacturing polycrystalline semiconductor thin film
JPH1168109A (en) Production of polycrystalline thin film and production of thin-film transistor
JPH04139728A (en) Manufacture of polycrystalline field-effect transistor
JP2809152B2 (en) Method for manufacturing thin film transistor
JP3203652B2 (en) Semiconductor thin film manufacturing method
JP4357006B2 (en) Method for forming polycrystalline semiconductor thin film and method for manufacturing thin film transistor
JP3269730B2 (en) Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device
JP3090201B2 (en) Polycrystalline silicon film and semiconductor device
JPH0329316A (en) Formation of semiconductor thin film
KR100366960B1 (en) silicon crystallization method
JP2822394B2 (en) Method for manufacturing semiconductor device
KR100222913B1 (en) Process for forming polycrystalline silicon
KR20040061795A (en) fabrication method of a poly crystal silicon film
JP2661571B2 (en) Method for manufacturing thin film transistor
JPH03132074A (en) Manufacture of thin film and thin-film transistor
KR0128522B1 (en) Low temperature poly-silicon film structure and transistor, and making method thereof

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20011205

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080111

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090111

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100111

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110111

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110111

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120111

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130111

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130111

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140111

Year of fee payment: 12

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140111

Year of fee payment: 12

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees