KR100222913B1 - Process for forming polycrystalline silicon - Google Patents

Process for forming polycrystalline silicon Download PDF

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KR100222913B1
KR100222913B1 KR1019970005429A KR19970005429A KR100222913B1 KR 100222913 B1 KR100222913 B1 KR 100222913B1 KR 1019970005429 A KR1019970005429 A KR 1019970005429A KR 19970005429 A KR19970005429 A KR 19970005429A KR 100222913 B1 KR100222913 B1 KR 100222913B1
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thin film
silicon thin
polycrystalline silicon
deposition
particle size
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KR19980068689A (en
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안병태
이정노
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윤덕용
한국과학기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Abstract

본 발명은 다결정 규소박막의 제조방법에 관한 것으로, 좀더 상세하게는 폴라즈마 기상 화학 증착 방법을 이용하여 이중층 구조를 갖는 비정질 규소 박막을 증착한 후 이를 저온에서 열처리하여 입자크기가 큰 다결정 규소 박막을 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a polycrystalline silicon thin film, and more particularly, to deposit an amorphous silicon thin film having a double layer structure by using a plasma vapor deposition method, and then heat-processing it at low temperature to produce a polycrystalline silicon thin film having a large particle size. It relates to a manufacturing method.

본 발명의 목적은 종래의 방법에 비하여 비정질 규소박막의 증착 시 증착 조건만을 변화시켜 추가비용 증가가 없고, 또한 기존의 방법과 병행하여 사용할 경우 더욱 좋은 결과를 얻을 수 있는 새로운 다결정 규소박막의 제조방법을 제공함에 있다.It is an object of the present invention to change the deposition conditions of the deposition of amorphous silicon thin film as compared to the conventional method, there is no additional cost increase, and also a method of manufacturing a new polycrystalline silicon thin film that can achieve better results when used in combination with the existing method In providing.

즉, 본 발명은 이중층 구조의 비정질 규소박막의 증착도중 증착변수를 변화시켜 고상결정화하여 입자크기를 조절함을 특징으로 하는 다결정 규소박막의 제조방법이다.That is, the present invention is a method of manufacturing a polycrystalline silicon thin film, characterized in that the particle size is controlled by changing the deposition parameters during deposition of the amorphous silicon thin film of the double layer structure to adjust the particle size.

본 발명에 의한 다결정 규소박막은 액정 디스플레이, SRAM 등에 사용되는 TFT용 활성층, 태양전지 및 SOI 등에 사용될 수 있다.The polycrystalline silicon thin film according to the present invention can be used for an active layer for TFTs used in liquid crystal displays, SRAMs, etc., solar cells and SOI.

Description

다결정 규소박막의 제조방법Method of manufacturing polycrystalline silicon thin film

본 발명은 플라즈마 기상 화학 증착 방법을 이용하여 이중층 구조를 갖는 비정질 규소박막을 증착한 후 이를 저온에서 열처리하여 입자 크기가 큰 다결정 규소박막을 제조하는 방법에 관한 것이다.The present invention relates to a method for producing a polycrystalline silicon thin film having a large particle size by depositing an amorphous silicon thin film having a double layer structure using a plasma vapor chemical vapor deposition method and then heat-treating it at low temperature.

Static random access memory(SRAM)용 다결정 박막 트랜지스터(thin film transistor:TFT), 액정 디스플레이(liquid crystal display:LCD)용 TFT, 태양전지, silicon-on-insulator(SOI) 등에 다결정 규소박막의 응용이 급격히 증가함에 따라 유리등의 비정질 기판 위에서 입자 크기가 큰 다결정 규소 박막을 얻기 위한 여러 가지 방법이 제안되고 있다.Applications of polycrystalline silicon thin films are rapidly increasing in thin film transistors (TFTs) for static random access memory (SRAM), TFTs for liquid crystal displays (LCDs), solar cells, silicon-on-insulators (SOI), etc. Increasingly, various methods for obtaining a polycrystalline silicon thin film having a large particle size on an amorphous substrate such as glass have been proposed.

첫번째 방법으로는 비정질 규소박막의 화학증착에서 원료가스로 SiH4 대신 Si2H6를 이용하고 이를 600

Figure kpo00003
에서 열처리하여 다결정 규소박막을 얻는 방법으로 (R.B. Inversion, et. al., J. Appl. Phys., 1675(1987)입자 크기를 최고 5
Figure kpo00004
까지 얻을 수 있으나 원료 가스의 가격이 매우 비싸고 막의 균질성이 떨어진다는 단점이 있다.In the first method, Si2H6 is used instead of SiH4 as the source gas in the chemical vapor deposition of amorphous silicon thin film.
Figure kpo00003
(RB Inversion, et. Al., J. Appl. Phys., 1675 (1987)) to obtain a polycrystalline silicon thin film by heat treatment at
Figure kpo00004
Although it can be obtained up to the price of the source gas is very expensive and there is a disadvantage that the homogeneity of the film is poor.

두번째 방법은 LPCVD 혹은 여타 박막 제조방법으로, 비정질 혹은 다결정 규소박막을 증착한 후 이온 주입으로 비정질화 한 후 약 600

Figure kpo00005
에서 열처리하여 결정화하여 다결정 규소박막을 얻는 방법이다(A.T. Voutsas, et. al., J. Electrochem. Soc. 140, 871(1993). 이 방법으로는 약 2
Figure kpo00006
크기의 입자를 얻을 수 있으나, 이온주입 공정이 추가되어 대면적화에 어렵고 공정 비용이 많이 들게 되는 단점이 있다.The second method is LPCVD or other thin film fabrication method, which deposits an amorphous or polycrystalline silicon thin film and then amorphous by ion implantation.
Figure kpo00005
Crystallization by heat treatment in order to obtain a polycrystalline silicon thin film (AT Voutsas, et. Al., J. Electrochem. Soc. 140, 871 (1993).
Figure kpo00006
Particles of the size can be obtained, but the ion implantation process is added, making it difficult to make a large area and costly to process.

세번째 방법으로는, LASER를 이용하여 열처리하는 방법이 있다(일본공개 특허 제 평 4-144122호, 일본공개특허 평 3-25633호). 이는 일반적인 방법으로 규소박막을 증착한 후 LASER를 이용하여 용융 결정화 시키는 방법이다으로 대면적화에의 어려움과 고가격의 단점이 남아 있다.As a third method, there is a method of heat treatment using a LASER (Japanese Patent Laid-Open No. 4-144122, Japanese Patent Laid-Open No. 3-25633). This is a method of depositing a silicon thin film in a general manner and then melting crystallization using a LASER, and the disadvantages of large area and high cost remain.

본 발명자들은 상기한 종래기술의 단점을 해결하기 위하여 연구를 수행하던 중, 비정질 규소박막 증착도중, 증착변수 만을 변화시킴으로써 열처리 특성이 다른 이중층 구조의 비정질 규소박막을 얻을 수 있음을 알아내고 본 발명을 완성하였다.The present inventors found that during the study to solve the above-mentioned disadvantages of the prior art, the amorphous silicon thin film having a double layer structure having different heat treatment characteristics can be obtained by changing only the deposition parameters during the deposition of the amorphous silicon thin film. Completed.

본 발명의 목적은 종래의 방법에 비하여 비정질 규소박막의 증착 시 증착 조건만을 변화시켜 추가비용 증가가 없고, 또한 기존의 방법과 병행하여 사용할 경우 더욱 좋은 결과를 얻을 수 있는 새로운 다결정 규소박막의 제조방법을 제공함에 있다.It is an object of the present invention to change the deposition conditions of the deposition of amorphous silicon thin film as compared to the conventional method, there is no additional cost increase, and also a method of manufacturing a new polycrystalline silicon thin film that can achieve better results when used in combination with the existing method In providing.

따라서, 본 발명은 이중층 구조의 비정질 규소박막의 증착도중 증착변수를 변화시켜 고상결정화하여 입자크기를 조절함을 특징으로 하는 다결정 규소박막의 제조방법이다.Accordingly, the present invention is a method for producing a polycrystalline silicon thin film, characterized in that the particle size is controlled by changing the deposition parameters during deposition of the amorphous silicon thin film having a double layer structure to control the particle size.

제1도는 다결정 규소박막 제조 공정의 흐름도를 나타낸 것이다.1 shows a flowchart of a polycrystalline silicon thin film manufacturing process.

제2도는 본 발명에서 사용한 이중층 구조의 비정질 또는 미세결정질 박막의 개략도를 나타낸 것이다.2 shows a schematic view of an amorphous or microcrystalline thin film of a bilayer structure used in the present invention.

제3도는 기존의 방법(단일층 구조)과 본 발명에 의한 방법(이중층 구조)으로 제조한 다결정 규소 박막(두께 약 1000

Figure kpo00002
)의 입자 크기를 비교한 것이다.3 is a polycrystalline silicon thin film (thickness about 1000) manufactured by the conventional method (single layer structure) and the method according to the present invention (double layer structure).
Figure kpo00002
) Is a particle size comparison.

제4도는 본 발명에 의한 방법으로 증착 온도를 변화시켜 핵생성을 억제하는 아래층을 이용하여 입자크기를 증가시킨 결과를 나타낸 것이다.Figure 4 shows the result of increasing the particle size by using a lower layer to suppress the nucleation by changing the deposition temperature by the method according to the present invention.

본 발명은 SiH4 혹은 Si2H6를 이용하여 비정질 규소박막을 증착하는 데 있어서 증착 도중, 증착 변수를 변화시킴으로써 결정화 시의 핵생성 속도와 결정 성장 속도를 각각 조절하여 보다 큰 입자를 갖는 다결정 규소박막을 제조하는 방법에 관한 것이다. 아래에 그 제조 방법을 설명한다.In the present invention, in the deposition of an amorphous silicon thin film using SiH4 or Si2H6, by varying the deposition parameters during deposition, the polycrystalline silicon thin film having larger particles is produced by controlling the nucleation rate and crystal growth rate during crystallization, respectively. It is about a method. The manufacturing method is explained below.

제1도는 본 발명에서 사용된 제조 공정을 나타낸 것이다. 기판으로는 유리판, 석영판, Si wafer, 비정질(SiO2)이 입혀진 유리판, 비정질(SiO2)이 입혀진 석영판, 비정질(SiO2)이 입혀진 Si wafer를 사용하여 세척액으로 초음파 세척한 후 PEC VD chamber에 넣어 기판을 가열한 후 비정질 규소박막을 증착한다.Figure 1 shows the manufacturing process used in the present invention. As a substrate, the glass plate, quartz plate, Si wafer, glass plate coated with amorphous (SiO2), quartz plate coated with amorphous (SiO2), and Si wafer coated with amorphous (SiO2) were used for ultrasonic cleaning with a cleaning solution, and then placed in a PEC VD chamber. After heating the substrate, an amorphous silicon thin film is deposited.

비정질 규소박막을 증착 시 초기에는 증착조건을 조절하여 열처리 시의 핵생성 속도를 낮게 한다. 얇은 아래층이 증착되면 증착을 멈춘 후 다시 증착 조건을 조절하여 열처리 시의 결정성장 속도를 높게한다. 원하는 두께가 될 때까지 증착하여 증착을 종료한다. 이 때 변화시킬 수 있는 증착 변수는 각 층의 두께, 증착온도, RF power, 가스의 유속, 가스의 농도, 가스의 성분, 증착 압력 등이 있으며, 변화 범위는 다음과 같다. 증착 시 기판의 온도 범위는 RT(상온)

Figure kpo00007
600
Figure kpo00008
이며 증착된 막의 두께는 수 십
Figure kpo00009
Figure kpo00010
수
Figure kpo00011
까지 였고, flow rate은 1
Figure kpo00012
500sccm이었으며, RF power는 1
Figure kpo00013
600W이다. 비정질 규소박막의 증착시 SiH4, Si2H6 또는 이를 Ar, He 또는 H2, N2 gas로 희석시킨 것을 source gas로 사용하였다.At the time of depositing the amorphous silicon thin film, the deposition conditions are initially adjusted to lower the nucleation rate during the heat treatment. When a thin lower layer is deposited, the deposition stops and the deposition conditions are adjusted again to increase the crystal growth rate during heat treatment. Deposition is terminated by deposition until the desired thickness is reached. The deposition parameters that can be changed at this time are the thickness of each layer, deposition temperature, RF power, gas flow rate, gas concentration, gas composition, deposition pressure, and the like, and the change range is as follows. Temperature range of substrate during deposition is RT (room temperature)
Figure kpo00007
600
Figure kpo00008
And the thickness of the deposited film is tens
Figure kpo00009
Figure kpo00010
Number
Figure kpo00011
Flow rate was up to 1
Figure kpo00012
500 sccm, RF power is 1
Figure kpo00013
600W. In the deposition of the amorphous silicon thin film, SiH 4, Si 2 H 6 or Ar, He or H 2, N 2 gas was used as a source gas.

상기의 방법으로 증착된 규소박막을 열처리하여 입자의 크기가 큰 다결정 규소박막을 얻는다.The silicon thin film deposited by the above method is heat-treated to obtain a polycrystalline silicon thin film having a large particle size.

상기 방법으로 얻어진 다결정 규소박막응 아래층이 기판과 규소박막과의 계면사이에서의 핵생성을 억제하고, 위층이 결정 성장 속도를 높게 유지함으로써 고상결정화 결과 얻을 수 있는 최종 입자 크기를 아래 식에서 보듯이 크게 할 수 있다.The polycrystalline silicon thin film underlayer obtained by the above method inhibits nucleation between the interface between the substrate and the silicon thin film, and the top layer maintains a high crystal growth rate so that the final particle size obtained by the solid phase crystallization is large as shown in the following equation. can do.

Figure kpo00014
Figure kpo00014

g : 성장속도g: growth rate

I : 핵생성 속도I: nucleation rate

h : 막의 두께h: thickness of the film

k : 비례 상수k: proportional constant

또한 결정화가 잘 일어나지 않는 층을 아래층으로 이용하여 위층은 다결정이면서 아래층은 비정질인 규소박막을 얻을 수 있다.In addition, by using a layer in which crystallization hardly occurs as a lower layer, it is possible to obtain a silicon thin film of which the upper layer is polycrystalline and the lower layer is amorphous.

다음의 실시예에 의해 본 발명을 상세히 설명한다. 그러나, 본 발명이 다음의 실시예에 국한되는 것은 아니다.The present invention is explained in detail by the following examples. However, the present invention is not limited to the following examples.

[실시예 1]Example 1

유리 기판을 트리크로로에틸렌(trichloloethylen), 아세톤(aceton), 메탄올(methanol) 순으로 초음파 세척하였다. 기판을 플라즈마 화학증착기에 넣고 이중층의 아래층의 증착온도(150

Figure kpo00015
)로 예열시키고, 증착 압력은 0.4torr, radio-frequency(RF) 파우어는 10W, SiH4의 유량은 150sccm으로 하여 아래층을 두께 200
Figure kpo00016
로 증착하였다. RF 파우어를 끄고 이중층의 위층의 증착온도로 증착 조건을 변화시켰다. 이 때 다른 증착 조건은 그대로 하여 위층을 두께 800
Figure kpo00017
로 증착하였다. 증착된 비정질 규소박막을 질소 분위기 600
Figure kpo00018
에서 열처리하여 결정화하여 다결정 규소박막을 얻었다. 얻어진 다결정 규소박막의 입자크기를 기존의 방법에 의한 다결정 규소박막의 입자크기와 비교하여 제3도에 나타내었다.The glass substrates were ultrasonically cleaned in the order of trichloloethylen, acetone, methanol. The substrate was placed in a plasma chemical vapor deposition system and the deposition temperature of the lower layer of the
Figure kpo00015
Preheat), the deposition pressure is 0.4torr, the radio-frequency (RF) power is 10W, the flow rate of SiH4 is 150sccm and the lower layer is 200
Figure kpo00016
Was deposited. The RF power was turned off and the deposition conditions were varied with the deposition temperature of the upper layer of the bilayer. At this time, the thickness of the upper layer was 800
Figure kpo00017
Was deposited. Deposited amorphous silicon thin film in a nitrogen atmosphere 600
Figure kpo00018
It was crystallized by heat treatment at to obtain a polycrystalline silicon thin film. The particle size of the obtained polycrystalline silicon thin film is shown in FIG. 3 in comparison with the particle size of the polycrystalline silicon thin film by the conventional method.

[비교예 1]Comparative Example 1

실시예 1의 제조공정 중 '아래층'의 증착 공정을 제외하고 위층만 1000

Figure kpo00019
증착하여 결정화하여 다결정 규소박막을 제조하였다. 그 입자 크기를 제3도에 나타내었다.Only the upper layer except the deposition process of the 'lower layer' in the manufacturing process of Example 1
Figure kpo00019
Deposition and crystallization to prepare a polycrystalline silicon thin film. The particle size is shown in FIG.

[비교예 2]Comparative Example 2

아래층은 150

Figure kpo00020
에서 200
Figure kpo00021
, 위층은 400
Figure kpo00022
에서 800
Figure kpo00023
증착하는 것 이외에는 비교예 1과 동일하게 실시한 후 결정화하여 다결정 규소박막을 제조하였다. 그 투과 전자현미경의 암시야상을 제4도에 나타내었다.Downstairs is 150
Figure kpo00020
From 200
Figure kpo00021
, Upstairs is 400
Figure kpo00022
From 800
Figure kpo00023
A polycrystalline silicon thin film was prepared by performing the same procedure as in Comparative Example 1 except for depositing and crystallizing. The dark field image of the transmission electron microscope is shown in FIG.

[비교예 3]Comparative Example 3

위층을 400

Figure kpo00024
에서 1000
Figure kpo00025
증착하는 것 이외에는 비교예 2와 동일하게 실시한 후 결정화하여 다결정 규소박막을 제조하였다. 그 투과 전자현미경의 암시야상을 제4도에 나타내었다.400 upstairs
Figure kpo00024
In 1000
Figure kpo00025
A polycrystalline silicon thin film was prepared in the same manner as in Comparative Example 2 except for evaporation, followed by crystallization. The dark field image of the transmission electron microscope is shown in FIG.

본 발명의 방법으로 제조한 다결정 규소박막의 입자크기가 기존의 방법으로 제조한 다결정 규소박막의 입자 크기에 비하여 증가되었음을 제3도 및 제4도에 의해 알 수 있다. 이와 같이 본 발명은 비정질 규소박막의 증착 도중 간단히 증착변수를 적절히 바꿈으로 해서 이를 결정화 시켰을 때 입자의 크기가 증가되는 것이 특징이다.It can be seen from FIGS. 3 and 4 that the particle size of the polycrystalline silicon thin film prepared by the method of the present invention was increased compared to the particle size of the polycrystalline silicon thin film prepared by the conventional method. As described above, the present invention is characterized in that the particle size increases when the crystallization of the amorphous silicon thin film is performed by simply changing the deposition parameter appropriately.

본 발명은 종래의 방법에 비하여 비정질 규소박막의 증착시 증착 조건만을 변화시키는 것으로 매우 간단하면서도 추가 비용 증가가 없는 방법이다. 또한 기존의 방법과 병행하여 사용하여 경우 더욱 좋은 결과를 얻을 수 있는 방법이다.Compared to the conventional method, the present invention changes the deposition conditions only in the deposition of the amorphous silicon thin film, which is very simple and there is no additional cost increase. In addition, when used in parallel with the existing method is a way to obtain better results.

본 발명에 의한 다결정 규소박막은 액정 디스플레이, SRAM 등에 사용되는 TFT용 활성층, 태양전지 및 SOI 등에 사용될 수 있다.The polycrystalline silicon thin film according to the present invention can be used for an active layer for TFTs used in liquid crystal displays, SRAMs, etc., solar cells and SOI.

Claims (3)

이중층 구조의 비정질 규소박막을 고상결정화하여 입자크기를 조절함을 특징으로 하는 다결정 규소박막의 제조방법.A method for producing a polycrystalline silicon thin film, characterized in that the amorphous silicon thin film having a double layer structure is subjected to solid phase crystallization to control particle size. 제1항에 있어서, 비정질 규소박막 또는 미세결정질 규소박막의 증착 도중 층의 두께, 증착온도, RF 파우어, 가스의 유속, 가스의 농도, 가스의 성분, 증착 압력을 변화시켜 결정화함을 특징으로 하는 다결정 규소박막의 제조방법.The method according to claim 1, wherein the thickness of the layer, the deposition temperature, the RF power, the flow rate of the gas, the concentration of the gas, the composition of the gas, and the deposition pressure are crystallized during deposition of the amorphous silicon thin film or the microcrystalline silicon thin film. Method for producing polycrystalline silicon thin film. 제1항 또는 제2항에 있어서, 기판과 규소박막 사이의 계면에서의 핵생성 또는 규소박막 표면에서의 핵생성을 억제하는 층을 이용하여 입자 크기를 증가시킴을 특징으로 하는 다결정 규소박막의 제조방법.The polycrystalline silicon thin film according to claim 1 or 2, wherein the particle size is increased by using a layer for inhibiting nucleation at the interface between the substrate and the silicon thin film or nucleation at the surface of the silicon thin film. Way.
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