KR101073133B1 - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can improve the uniformity of the contact resistance at the bottom of the micro-opening part, which is a high step when forming a metal plug, and can prevent a leakage current. Forming an insulating film on the conductive film; Selectively etching the insulating film to form an open portion exposing the conductive film; Removing the etch residue and the native oxide layer on the bottom of the open portion; Alternately exposing the silicon-containing compound carried to H ₂ and Ar to form an amorphous silicon film along the profile of the open portion; Forming a titanium film and a metal nitride film on the amorphous silicon film; And depositing a metal film on the metal nitride film to fill the open part.

Ohmic layer, titanium (Ti), silicide, amorphous silicon film, buffer layer, contact, plug.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}             

1A to 1C are cross-sectional views illustrating a metal plug forming process according to US Pat. No. 6,255,209.

2A to 2D are cross-sectional views illustrating a metal plug forming process according to an embodiment of the present invention.

FIG. 3 is a graph showing surface roughness versus temperature of a wafer with respect to a temperature when a 100 nm Ti film is deposited by PECVD on a single crystal silicon substrate.

Figure 4 is a SEM photograph showing the comparison of the surface roughness according to the temperature corresponding to FIG.

FIG. 5 is a photograph showing a comparison of surface changes after deposition and heat treatment of a Ti film by a 50 kV PECVD method with or without an amorphous buffer film on a single crystal silicon substrate. FIG.

Figure 6 is a TEM photograph showing the difference between the silicide interface roughness / uniformity of the present invention and the prior art according to the deposition heat treatment of the Ti film by the 100CVD PECVD method on the lower silicon substrate.

* Explanation of symbols for the main parts of the drawings

200: silicon substrate 201: diffusion layer                 

202: insulating film 203: conductive film

204 spacer 205 interlayer insulating film

207a: metal silicide 208: Ti film

209: nitride film 210: metal film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine contact of a semiconductor device.

As ultra-high integration of semiconductor devices proceeds, design rules that are manufactured continue to decrease. Accordingly, in order to secure device characteristics and reliability by embedding or uniformly coating a semiconductor device component layer having a high stepped 0.5 μm size contact or a concave-convex shape with a large step height on the surface to secure device characteristics and reliability, Excellent step coverage is required.

In particular, contact with the silicon substrate having the highest resistance when wiring is formed through a contact in various semiconductor devices such as memory, logic, merged DRAM, or control circuit. Minimizing leakage current at the bottom and securing low and uniform contact resistance are essential elements in the fabrication of semiconductor devices with excellent characteristics.                         

Titanium (Ti) was deposited using a physical vapor deposition method as an ohmic layer for lowering the contact resistance during the deposition of metal wires connecting many functional devices through contacts.

However, as the miniaturization of a contact having a high step is accelerated, the step coverage at the bottom of the contact is poor, making it difficult to secure a low contact resistance.

In order to improve this, the Plasma Ehhanced Chemical Vapor Deposition (PECVD) method, which is currently being applied and evaluated, is used to remove impurities that degrade the reliability or increase the resistivity of metal wiring such as chlorine in the deposited thin film. Deposit at high temperature of 600 ° C. or higher to reduce.

Particularly, when titanium is deposited continuously after the removal of the natural oxide layer by etching with a high density plasma such as Ar / NF ₃ on the bottom of the silicon-exposed contact, the reaction proceeds to form titanium silicide such as TiSi ₂ . The barrier layer is then deposited and the contact open region is filled with a low resistivity metal, such as W, Al or Cu.

At this time, the formed silicide reacts rapidly on a single crystal silicon substrate, and the silicide interface irregularities become unevenly severe in the vertical and horizontal directions, thereby decreasing the depth of ion implanted implantation and the boundary between the contact region and the diffusion layer. Shorter distances may cause an increase in leakage current. In addition, in the part where the silicide thickness is excessively increased, plowing of boron (B) ions in the P + region injected into the diffusion layer occurs, causing a sharp increase in contact resistance unlike a state of a uniform contact bottom. Worsen uniformity.

In U.S. Patent No. 6,255,209, a technique is disclosed in which three reactive gases, Ti, Si precursor, and H ₂ are simultaneously introduced into a reaction chamber to form titanium silicide by CVD.

1A to 1C are cross-sectional views illustrating a metal plug forming process according to US Pat. No. 6,255,209, which is a prior art, with reference to this.

As shown in FIG. 1A, the diffusion layer 101 is formed by implanting impurity ions or the like on the silicon substrate 100, and then the insulating film 102 and the conductive film 103 are stacked and spacers 104 are disposed on the side surfaces thereof. A conductive pattern is formed.

Here, when reference numeral 102 is an insulating film, the conductive pattern includes a gate electrode, and in the case of a conductive film, the conductive pattern may include a metal wiring, a bit line, and the like, and the conductive film 103 may be a polysilicon film. have.

The interlayer insulating film 110 is formed on the entire surface where the conductive pattern and the active layer 101 are formed, and then the interlayer insulating film 110 is selectively etched to contact the active layer 101 or the conductive film 103. And an open portion 105 exposing the conductive film 103.

Subsequently, after the flexible etching, the Ti film 106 is deposited along the profile in which the open portion 105 is formed. At this time, the silicon substrate 100, which is a single crystal, and Ti react with each other to form silicide 107 on the surface of the active layer 101.                         

Subsequently, as shown in FIG. 1B, a metal nitride film 108 such as TiN is formed on the Ti film 106, and then a metal film 109 is deposited on the entire surface as shown in FIG. Landfill 105).

On the other hand, in this case, a sudden uneven reaction at the bottom of the contact generated during the deposition of titanium is prevented, but the reaction proceeds in the gas phase as the reactive SiH ₄ and the metal reactant gas and the reducing agent are simultaneously introduced into the reaction chamber to form fine particles. In addition, a large amount of particles fall on the substrate, causing bridging and poor openness, which is a major factor in yield reduction. Thus, minimizing particulate generation for mass production is a requirement for thin film deposition process technology that must be absolutely satisfied in the current trend of semiconductor device miniaturization being accelerated.

In the conventional silicide formation process, the silicide formation reaction is delayed at the arsenic-implanted portion of the diffusion layer in the polycrystalline silicon or single crystal substrate containing N + (As, arsenic) / P + (B, boron) and thus the contact resistance and silicide resistance are increased. Increases.

In order to prevent this problem, a method of improving the uniformity and silicide formation on N + / P + silicon by forming an amorphous layer by implanting arsenic on the front surface before deposition of titanium and then depositing titanium [I. Sakai, H. Kawaguchi, T. Harashima, L.E.G. Johnson and K. Okabe, "A new salicide process (PASET) for sub-falf micron CMOS" 1992 Symp. VLSI Technol. Dig. Tech. Papers, IEEE New York, p66, 1992.].                         

In this case, an ion implantation process that adds arsenic is added, resulting in a decrease in productivity, and when arsenic is injected into the front surface including the P + region in which boron is injected, it is electrically neutralized with boron, causing an increase in resistance of the diffusion layer. Is generated.

The present invention proposed to solve the problems of the prior art as described above, can provide a semiconductor device manufacturing method that can improve the uniformity of the contact resistance at the bottom of the micro-opening part of the high step when forming the metal plug and can prevent the leakage current It is for that purpose.

In order to achieve the above object, the present invention comprises the steps of forming an insulating film on a conductive film containing silicon; Selectively etching the insulating film to form an open portion exposing the conductive film; Removing the etch residue and the native oxide layer on the bottom of the open portion; Alternately exposing the silicon-containing compound carried to H ₂ and Ar to form an amorphous silicon film along the profile of the open portion; Forming a titanium film and a metal nitride film on the amorphous silicon film; And depositing a metal film on the metal nitride film to fill the open part.

In addition, to achieve the above object, the present invention comprises the steps of forming an insulating film on a conductive film containing silicon; Selectively etching the insulating film to form an open portion exposing the conductive film; Removing the etch residue and the native oxide layer on the bottom of the open portion; Alternating exposing the acetic containing compound carried to H ₂ and Ar to form an acetic hydrogen compound thin film along the profile of the open portion; Alternately exposing the silicon-containing compound to be transported to H ₂ and Ar to form an amorphous silicon film on the thin film of the hydrogen hydrogen compound; forming a titanium film and a metal nitride film on the amorphous silicon film; And depositing a metal film on the metal nitride film to fill the open part.

The present invention is a reaction chamber equipped with a high density plasma generator capable of straightness and soft etching, which has been developed and applied to remove a natural oxide film on the bottom of a high step contact on a stepped substrate. Remove the oxide film.

In order to improve the problems presented in the prior arts, the substrate is continuously transferred to the chemical vapor deposition chamber and kept below a certain temperature, and hydrogen and silicon compounds (SiH ₄ , Si ₂ H _6, etc.) are reacted step by step together with Ar, an inert carrier gas. A buffer film is deposited to maintain a low pressure by depositing an amorphous silicon layer having a uniform step coverage in the surface of the substrate and the contact to prevent the formation of titanium silicide that proceeds simultaneously as it is deposited at a high temperature. At this time, before the buffer layer is first consumed during silicide formation, before the deposition of the amorphous silicon layer, an asce hydride (AsH ₃ ) may be exposed to form an AsHx layer in order to further improve the uniformity when reacting with the lower single crystal silicon. Can be.

In the case of a single crystal substrate, an amorphous layer is formed as an atomic layer of several monolayers just below the surface by ion implantation for forming a diffusion layer, but since the other part maintains crystallinity, a large amount of silicon is supplied in a specific crystal direction so that uniformity However, the reason why the amorphous silicon layer functions as a buffer film is that the supply of silicon atoms necessary for silicide formation occurs uniformly in all directions, and when the reaction proceeds on the lower single crystal substrate, it is diffused from the buffer film and formed first. This is because silicon atoms in the silicide diffuse and participate in the reaction.

In addition, the contact resistance is stabilized low, the N + contact resistance can ensure a low contact resistance when a minimum reaction occurs at the Ti / Si interface. Therefore, the thickness of the buffer film is low and uniform when it is determined in consideration of the Ti thickness and temperature deposited thereon and the silicide thickness to be formed on the contact bottom of the P + region of the single crystal substrate under the buffer film, and minimizes leakage current. can do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

2A to 2D are cross-sectional views illustrating a metal plug forming process according to an embodiment of the present invention, with reference to this, a metal plug forming process of the present invention will be described.

As shown in FIG. 2A, the diffusion layer 201 is formed on the silicon substrate 200 by implanting impurity ions, and then the insulating film 202 and the conductive film 203 are stacked, and a spacer 204 is disposed on the side thereof. A conductive pattern is formed.

Here, when reference numeral 202 is an insulating film, the conductive pattern includes a gate electrode, and in the case of a conductive film, the conductive pattern may include metal wiring, a bit line, and the like, and the conductive film 203 may be a polysilicon film. have.

The interlayer insulating film 205 is formed on the entire surface where the conductive pattern and the active layer 201 are formed, and then the interlayer insulating film 205 is selectively etched for contact with the active layer 201 or the conductive film 203, thereby forming the active layer 201. And an open portion 206 exposing the conductive film 203.

Subsequently, after the flexible etching, an amorphous silicon film 207 is formed along the profile in which the open portion 206 is formed. The process of Figure 2a is described in more detail below.

A method for solving the problems of the prior arts appearing in a high stepped contact region having a diameter of 0.25 μm or less, and a photo and dry process for connecting various device parts by metal wiring on a silicon substrate on which a semiconductor device and step are formed. After forming the open portion 206 through the step, the wet portion, for example, H ₂ SO ₄ cleaning for 5 minutes, and the open portion 206 by the etching process using HF diluted to 200: 1 for 90 seconds. Natural oxide film and organic matter on the bottom are removed first.

Subsequently, in order to remove the natural oxide film formed on the front of the high step opening 206 on the substrate 200 on which the step is formed in one step by moving to an integrated device, an ICP (Inductively Coupled Plasma) Or using a mixed gas of Ar / XeFe ₂ (eg, at a rate of less than 50 mA / min) or fluorine compounds such as SF ₆ and NF ₃ in a reaction chamber equipped with a high density plasma generator such as ECR (Electron Cylcotron Resonance) To form a plasma to remove the native oxide film first.

At this time, in order to form an amorphous film necessary to form a uniform low-resistance titanium silicide at the bottom of the open portion, supplying only the fluorine compound is stopped and plasma is formed only with Ar (argon). Promoting linearity allows the silicon crystals on the bottom surface of the open portion to further form an amorphous layer by physical collisions of accelerated Ar ions.

However, since the thickness that can be formed on the bottom of the open portion by physical collision is tens of atomic layers or less, the applied voltage and time are appropriately adjusted or omitted so as to maintain high productivity.

The substrate 200 is continuously transferred to the chemical vapor deposition chamber in two steps without exposure to the atmosphere, and is maintained at a predetermined temperature (for example, 280 ° C to 480 ° C or 500 ° C or less), and hydrogen and an inert gas of 1 slm or less are used as a carrier gas. Using silicon compounds such as SiH ₄ or Si ₂ H ₆ , 5SCCM to 60SCCM, repeatedly turning on and off SiH ₄ to on and off of H ₂ stepping into the reaction chamber to maintain a low pressure of 10 Torr or less. The amorphous silicon film 207 having a uniform step coverage on the surface of the substrate 200 and the open portion 206 is deposited to form a buffer film that prevents the uneven formation of titanium silicide that proceeds simultaneously as it is deposited at a high temperature. .

At this time, the reason why the deposition temperature is limited to 500 ° C. or less is to prevent the deposition of polycrystalline silicon. Unlike the conventional CVD method, the injection of the reaction gases step by step is not performed in the gas phase due to the heat transferred from the bottom. This is to prevent the occurrence of fine particles.

The deposition process of the amorphous silicon film 207 that occurs on the substrate 200 is as in Scheme 1 below using SiH ₄ gas.

+ Gas phase reaction: SiH ₄ → SiH ₃ + 2H ₂ (g)

+ Substrate surface reaction: SiH ₄ & SiH ₃ + H ₂ (g) ↔ a-SiHx (s) + 2H ₂ (g)

Here, 'a' represents amorphous, 's' represents solid, and 'g' represents gas, that is, gas.

The deposition rate according to the exposure time t _on is changed from 16 ms / s (t _on = 0.2 seconds) to 7 ms / s (t _on = 0.5 seconds). Such long exposure may be caused by a magnetic etching phenomenon that reacts with the SiHx deposited by the adsorbed hydrogen and flows away, for example, by lowering the temperature from 500 ° C. to 400 ° C., thereby improving the deposition rate.

The reason for transporting the silicon-containing gas to argon, which is an inert gas, is to improve the step coverage by promoting the decomposition and surface movement of the silicon compound adsorbed on the gas phase and the substrate surface by colliding with the adsorbed silicon-containing gas.

Subsequently, as shown in FIG. 2B, the Ti film 208 is deposited on the amorphous silicon film 207 in a CVD chamber including PECVD, which is a method being applied and evaluated in a semiconductor device including an ultrafine open portion. 2C, the nitride film 209 is formed by NH ₃ plasma treatment.

At this time, CVD deposition conditions are using TiCl ₄ / H ₂ and NH ₃ as the source gas, the pressure of 1 Torr to 10 Torr, the temperature of 400 ℃ to 680 ℃ and the power of 100W to 600W.

In this case, in order to lower the specific resistance of the metal silicide 207a formed under the metal nitride film, a high temperature rapid thermal annealing (hereinafter referred to as RTA) is performed under an atmosphere of NH ₃ or N ₂ and a temperature of 800 ° C. to 900 ° C. Do it within seconds.

When RTA is performed prior to the deposition of the nitride film 208, the crystallization direction of the metal silicide 207a is changed from the C49 to the C54 metal silicide, and a partial coagulation occurs to deteriorate the surface roughness. When the silicide is formed at low temperature, unreacted metal such as Ti is removed by wet etching, followed by RTA.

On the other hand, when the metal nitride film is deposited by PVD or CVD, the heat treatment is performed to inhibit the cohesion and protruding onto the surface as the silicide is deformed during the RTA. After forming it thin below, RTA is advanced.

However, in the case of high temperature heat treatment of 800 ° C. or higher, silicides are formed on the bottom of the open part, so that defects such as cracks are generated in the barrier layer deposited thereon, which becomes a diffusion path during deposition of the plug material and reaches the lower substrate. Encroachment may occur. In this case, when the heat treatment is performed within 180 seconds at a temperature lower than a high temperature heat treatment in the vacuum chamber, for example, 600 ° C. to 750 ° C., the interdiffusion proceeds gradually while preventing the formation of a non-uniform layer caused by a sudden silicide reaction, thereby reducing contact resistance. Secure the characteristic.

Subsequently, as shown in FIG. 2D, the low resistivity metal film 210 is deposited by CVD to fill the open portion 206.

On the other hand, in another embodiment, half of the thickness of the amorphous buffer film to be deposited is deposited by Ti after the deposition by 1/2 of the PECVD method, and then repeated once to form the total deposition thickness on the substrate.

In this case, when the amorphous silicon film is additionally formed on the first deposited titanium film, the deposition temperature is 500 ° C. or lower, so that TiSix (x ≦ 2) having a uniform thickness due to mutual diffusion without sudden reaction between unreacted titanium and silicide at the bottom A silicide having a composition is formed. The secondary titanium film deposited thereon reacts with the TiSix underneath.

Thereafter, a metal nitride film is deposited and RTA is performed to uniformly form TiSi ₂ (Titanium disilicide) having a positive composition, thereby ensuring low resistance of the open resistance. Finally, the open portion is buried to carry out the planarization of the wiring.

In order to improve the uniformity when reacting with the single crystal silicon at the bottom when the silicide is formed, and then to deposit the amorphous silicon film for buffering to prevent a sudden reaction, it is acenic at the same temperature in the same reaction chamber. Exposure to the compounds (AsH ₃ and Ar carrier gas) can form an ascex (AsHx) layer. After sufficiently flowing nitrogen to remove residual AsH ₃ gas, the process proceeds from the same process from step 2 to form a silicide and a nitride film, and then fills the open part.

The surface roughness of silicide on silicon formed when deposited by PECVD is dependent on the total thickness of the silicide, which is directly affected by the titanium deposition thickness and deposition temperature.                     

CVD Ti deposition temperature Lower curtain Deposition time (seconds) Sheet resistance
Ω / □) average Sheet resistance
Ω / □) 1σ (%) Thickness average Thickness 1σ (%) Resistivity (
μΩ-cm) 630 ℃ Ox 13 267.3 1.1 33.9 2.4 90.7 630 ℃ Si 13 84.5 6.1 114.2 5.2 96.5 630 ℃ Ox 18.5 200.0 1.3 48.7 1.6 97.4 630 ℃ Si 18.5 63.1 5.0 149.6 3.8 94.3 630 ℃ Ox 24.3 167.9 1.6 62.6 0.8 105.1 630 ℃ Si 24.3 54.3 4.5 181.6 1.9 98.5 650 ℃ Ox 15.1 230.7 1.9 41.5 1.7 95.7 650 ℃ Si 15.1 63.9 4.9 148.2 1.7 94.7 670 ℃ Ox 10 384.5 2.2 26.4 1.8 101.7 670 ℃ Si 10 88.5 7.1 119.8 7.9 106.0 670 ℃ Ox 13 279.6 3.3 37.2 2.1 104.0 670 ℃ Si 13 66.1 5.5 159.4 6.4 105.3 670 ℃ Ox 16 237.9 2.7 44.3 2.7 105.4 670 ℃ Si 16 54.1 4.8 189.6 7.3 102.5 690 ℃ Ox 9 505.3 2.93 23.9 2.3 120.9 690 ℃ Si 9 90.5 6.89 115.8 4.7 104.8 690 ℃ Ox 11.5 348.8 1.67 32.5 3.8 113.3 690 ℃ Si 11.5 71.0 6.7 147.0 4.4 104.3

FIG. 3 is a graph illustrating surface roughness of a wafer at a center and an edge of a wafer when a Ti film of 100 Å is deposited by PECVD on a single crystal silicon substrate, and FIG. 4 is a surface roughness of a temperature corresponding to FIG. 3. It is a SEM photograph shown comparatively.

Table 1 and FIGS. 3 and 4 show changes in thickness, uniformity and surface roughness according to deposition temperature and underlying film type (silicon / oxide film).

Referring to Table 1, it can be seen that the thickness of the titanium silicide increases in proportion to the increase in the deposition time on the oxide film but increases in the deposition time and temperature on the silicon.

In addition, it can be seen in FIGS. 3 and 4 that the roughness of the silicide formed at the same time as the deposition temperature increases and rapidly becomes poor throughout the substrate.                     

FIG. 5 is a photograph showing a comparison of surface changes after deposition and heat treatment of a Ti film by a 50 kV PECVD method with or without an amorphous buffer film on a single crystal silicon substrate.

In order to improve this, the surface state obtained when the amorphous metal is deposited on the silicon substrate by about 30Å and the Ti film is deposited until RTA and when the prior art is applied is shown in FIG. 5.

Referring to FIG. 5, the surface roughness of the present invention is almost unchanged even after titanium deposition and RTA by PECVD, but it can be seen that in the conventional case, a large number of agglomerated shapes generated when RTA is performed without a metal nitride film on the upper surface.

FIG. 6 is a TEM photograph comparing the silicide interface roughness / uniformity difference between the present invention and the prior art according to the deposition heat treatment of a Ti film by a 100 Å PECVD method on a lower silicon substrate.

That is, Figure 6 is formed after the open portion on the silicon substrate with the step formed by applying the present invention and the prior art shown in Figures 1a to 1c and 2a to 2d to open the buried part of the bottom of the open portion The uniformity of the titanium silicide formed on the silicon substrate was observed.

Referring to FIG. 6, it can be seen that, as in the case of the prior art of FIG. 5, in which surface roughness defects occur, the thickness of the silicide under the open part is uneven and a thickness difference occurs depending on the position of the open part. However, in the case of applying the present invention, the thickness of the titanium silicide on the bottom of the open portion was uniformly formed to be 200 μs or less. At this time, if the thickness of the titanium silicide required to lower the contact resistance of the diffusion layer, for example, the P + region is 300 kPa or more, the thickness of the amorphous buffer film is reduced to, for example, 50 kPa, thereby increasing the silicide thickness in the P + region.

Therefore, while depositing a thin amorphous silicon buffer film by PECVD or CVD method, in order to lower the contact resistance at the bottom of the high stepped micro-opening part, the thickness of the titanium film in general and the subsequent heat treatment and the contact resistance in the P + diffusion region are reduced. According to the present invention which deposits considering the required silicide thickness, it is possible to improve contact resistance and prevent leakage current.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can improve the uniformity of the contact resistance at the bottom of the micro-opening portion having a high step and prevent leakage current, thereby improving the performance of the semiconductor device.

Claims (10)

Forming an insulating film on the conductive film containing silicon; Selectively etching the insulating film to form an open portion exposing the conductive film; Removing the etch residue and the native oxide layer on the bottom of the open portion; Repeatedly performing a first step of injecting a silicon-containing compound transported into Ar into the chamber and a second step of injecting H ₂ transported into Ar to form an amorphous silicon film along the profile of the open portion; Forming a titanium film and a metal nitride film on the amorphous silicon film; And Filling the open part by depositing a metal film on the metal nitride film Semiconductor device manufacturing method comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, In the step of removing the residue and the natural oxide film, A method of manufacturing a semiconductor device, comprising using a chemical wet etching method. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, In the step of removing the residue and the natural oxide film, A method of manufacturing a semiconductor device, comprising forming a plasma using a gas in which an inert gas and a fluorine-containing compound are mixed to use a physical and chemical etching method. Forming an insulating film on the conductive film containing silicon; Selectively etching the insulating film to form an open portion exposing the conductive film; Removing the etch residue and the native oxide layer on the bottom of the open portion; Alternating exposing the acetic containing compound carried to H ₂ and Ar to form an acetic hydrogen compound thin film along the profile of the open portion; Forming an amorphous silicon film on the thin film of the hydrogen hydrogen compound by alternately performing a first step of injecting a silicon-containing compound transported into Ar into a chamber and a second step of injecting H ₂ transported into Ar; Forming a titanium film and a metal nitride film on the amorphous silicon film; And Filling the open part by depositing a metal film on the metal nitride film Semiconductor device manufacturing method comprising a. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1 or 4. In the step of forming the titanium film and the metal nitride film, Forming the titanium film, and then repeatedly depositing the amorphous silicon film and the titanium film, forming the metal nitride film, and then performing rapid heat treatment. Claim 6 was abandoned when the registration fee was paid. The method according to claim 1 or 4, After forming the metal nitride film, The method of manufacturing a semiconductor device further comprising the step of rapid heat treatment or vacuum heat treatment. Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 1 or 4, In the step of forming the metal nitride film, the semiconductor device manufacturing method, characterized in that carried out at a temperature of 620 ℃ to 680 ℃. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein After forming the metal nitride film, A method of manufacturing a semiconductor device, further comprising the step of stopping the supply of the metal reactant source without moving the reaction chamber and performing heat treatment in an atmosphere of inert gas, ammonia or nitrogen gas. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, In the step of heat treatment, the semiconductor device manufacturing method characterized in that carried out within 300 seconds at a temperature of 620 ℃ to 680 ℃. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The conductive film containing silicon, A semiconductor device manufacturing method comprising an active region or a polysilicon film of a substrate doped with an impurity.

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