KR101491726B1 - Method of gap filling in a semiconductor device - Google Patents

Method of gap filling in a semiconductor device Download PDF

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KR101491726B1
KR101491726B1 KR20080098709A KR20080098709A KR101491726B1 KR 101491726 B1 KR101491726 B1 KR 101491726B1 KR 20080098709 A KR20080098709 A KR 20080098709A KR 20080098709 A KR20080098709 A KR 20080098709A KR 101491726 B1 KR101491726 B1 KR 101491726B1
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insulating film
gas
semiconductor substrate
gaps
sccm
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KR20080098709A
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Korean (ko)
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KR20100039654A (en
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유진혁
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주성엔지니어링(주)
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

Abstract

본 발명은 플라즈마 처리 장치에서 원자층 증착 공정과 고밀도 플라즈마 화학기상증착 공정을 수행하여 초미세선폭의 소자도 갭필할 수 있는 반도체 소자의 갭필(gap fill) 방법에 관한 것으로,The present invention relates to a gap fill method for a semiconductor device that can perform an atomic layer deposition process and a high-density plasma chemical vapor deposition process in a plasma processing apparatus so as to capture an ultra-fine line width element.

본 발명에 따른 반도체 소자의 갭필 방법은, 복수의 패턴들에 의해 복수의 갭이 형성된 반도체 기판이 제공되는 단계; 원자층 증착 공정을 수행하여 상기 반도체 기판 상부에 절연막을 증착하는 단계; 환원성 가스 분위기에서 고밀도 플라즈마 처리하여 상기 갭 상부에 증착된 절연막의 두께가 상기 갭 하부에 증착된 절연막의 두께보다 얇은 절연막 형상을 형성하는 단계; 상기 절연막 증착 단계와 절연막 형상 형성 단계를 적어도 1회 이상 반복하여 상기 복수의 갭을 갭필하는 것을 특징으로 한다.A method of gapping a semiconductor device according to the present invention includes: providing a semiconductor substrate having a plurality of gaps formed by a plurality of patterns; Depositing an insulating film on the semiconductor substrate by performing an atomic layer deposition process; Performing a high-density plasma treatment in a reducing gas atmosphere to form an insulating film shape having a thickness smaller than a thickness of the insulating film deposited on the lower portion of the gap; The insulating film deposition step and the insulating film shape forming step are repeated at least once to capture the plurality of gaps.

갭필, 보이드, HDPCVD, ALD Gapfil, Boyd, HDPCVD, ALD

Description

반도체 소자의 갭필 방법{Method of gap filling in a semiconductor device}BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

본 발명은 반도체 소자의 갭필 방법에 관한 것으로, 보다 상세하게는 플라즈마 처리 장치에서 원자층 증착 공정(ALD 공정)과 플라즈마 처리 공정을 수행하여 초미세선폭의 소자도 갭필이 가능하도록 하는 반도체 소자의 갭필(gap fill) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of gapping a semiconductor device, and more particularly, to a method of forming a gapfill of a semiconductor device capable of performing an atomic layer deposition process (ALD process) and a plasma process process in a plasma processing apparatus, (gap fill) method.

반도체 소자의 집적도가 향상됨에 따라 반도체 소자의 구성 요소들의 선폭과 간격이 점차 미세해지고 있다. 예를 들어 반도체 소자를 구성하는 금속 배선의 선폭과 간격이 점차 미세해지고 있으며, 소자 분리막 또한 폭 및 간격이 점차 미세해지고 있다. 따라서, 소자 분리막의 경우 종래의 LOCOS(LOCal Oxidation Silicon) 공정 대신에 반도체 기판에 좁고 깊은 트렌치(trench)를 형성한 후 이를 절연 물질로 갭필(gap fill)하는 STI(Shallow Trench Isolation) 기술이 주로 사용되고 있다.As the degree of integration of semiconductor elements is improved, the line widths and spacing of the elements of the semiconductor elements are becoming finer. For example, the line width and spacing of the metal wiring constituting the semiconductor element are becoming finer and the width and the interval of the element separating film are gradually becoming finer. Therefore, instead of the conventional LOCOS (LOCal Oxidation Silicon) process, an STI (Shallow Trench Isolation) technique in which a narrow and deep trench is formed in a semiconductor substrate and a gap fill is performed using an insulating material is mainly used for the device isolation film have.

소자 분리막을 형성하기 위한 트렌치 또는 금속 배선 사이 등의 갭필 공정은 트렌치의 바닥면에서부터 순차적으로 절연막이 증착되어 트렌치가 완전히 갭필되어야 한다. 그러나, 트렌치의 바닥면 뿐만 아니라 입구나 측벽에도 동시에 절연막이 증착됨으로써 발생하는 오버행(overhang) 현상 때문에 트렌치가 완전히 갭필되기 이전에 트렌치 상부가 막혀 트렌치 내부에 보이드(void)가 발생된다. 이러한 보이드는 트렌치의 종횡비(aspect ratio)가 커질수록 빈번하게 발생되고, 또한 보이드는 소자의 특성을 저하시키는 원인이 된다. 따라서, 트렌치 갭필 공정에서는 보이드의 발생을 억제하는 것이 중요한 공정 목표 중의 하나라고 할 수 있다.A gapfil process such as a trench or a metal interconnection line for forming an element isolation film requires an insulating film to be sequentially deposited from the bottom surface of the trench so that the trench is completely covered. However, due to an overhang phenomenon caused by the deposition of the insulating film at the inlet and the sidewall as well as the bottom surface of the trench, voids are formed inside the trench due to clogging of the trench before the trench is completely capped. These voids occur more frequently as the aspect ratio of the trench becomes larger, and voids cause degradation of the characteristics of the device. Therefore, it can be said that suppressing the generation of voids in the trench-gapfil process is one of the important process targets.

갭필 공정은 일종의 증착 공정이기 때문에 화학기상증착(Chemical Vapor Deposition: 이하, "CVD"라 함) 방법을 주로 이용하는데, 반도체 소자의 집적도가 높아지고 트렌치의 종횡비가 커짐에 따라 일반적인 CVD 방법을 이용하는 데는 한계가 있다. 따라서, 최근에는 고밀도 플라즈마(High Density Plasma; HDP)를 이용하는 HDPCVD 방법(High Density Plasma Chemical Vapor Deposition: 이하, "HDPCVD"라 함)으로 트렌치를 갭필하고 있으며, 특히 저압 분위기에서 고밀도 플라즈마를 발생시키는 것이 갭필 공정의 핵심 요소로 알려져 있다.Since the gapfil process is a kind of deposition process, chemical vapor deposition (hereinafter referred to as "CVD") is mainly used. As the degree of integration of semiconductor devices increases and the aspect ratio of the trench increases, . Therefore, in recent years, trenches have been gap-filled with HDPCVD (High Density Plasma Chemical Vapor Deposition) (hereinafter referred to as HDPCVD) using a high density plasma (HDP) It is known as a key element of the gapfil process.

그러나, HDPCVD 방법 역시 반도체 소자의 고집적화에 따라 갭필 능력의 한계가 야기되었다. 즉, 트렌치의 폭이 좁아지면서(예를 들면, 60㎚ 이하) HDPCVD 방법을 이용하여 트렌치 갭필 공정을 진행하여도 트렌치 입구에 오버행이 발생되고, 그로 인해 트렌치 내부에 보이드가 발생된다.However, the HDPCVD method also has a limitation in the ability of the gap fill function due to the high integration of semiconductor devices. That is, even if the trench gapfil process is performed using the HDPCVD method while the width of the trench is narrow (for example, 60 nm or less), overhang occurs at the trench entrance, thereby causing voids in the trench.

상기 문제를 극복하기 위해 HDPCVD 장비를 이용하여 증착과 식각을 반복하는 DED(Dep/Etch/Dep)공정이 제안되었다. 상기 DED 공정은 HDPCVD 방법에서 발생된 오버행을 식각하고 다시 HDPCVD 방법으로 증착하는 공정이다. DED 공정을 효과적으로 수행하기 위해서는 증착 균일성(Deposition Uniformity)과 에칭 균일성(Etching Uniformity)를 모두 만족하여야 한다. 특히, 에칭 균일성이 좋지 않으면 개구부 크기(Open Size)가 서로 달라져서 어떤 부분은 갭필을 만족하고 다른 어떤 부분은 갭필이 충족되지 않는 문제점이 있다. 또한, 갭필할 공간이 더욱 작아지면 3단계의 DED 공정으로는 불가능한 경우가 많아서 5단계 이상이 필요한 경우가 많다. 이는 처리량(throughput)에 막대한 영향을 주고 공정 튜닝(Tuning)도 패턴 프로파일에 따라 시행착오를 많이 거쳐야 하는 문제점이 있다. 또한, 갭필할 공간이 작아질수록 에칭 타임이 많이 줄어들고, 이로 인해서 원하는 프로파일을 얻을 수 없는 경우가 발생하는 문제점이 있다.In order to overcome this problem, a DED (Dep / Etch / Dep) process in which deposition and etching are repeated using HDPCVD equipment has been proposed. The DED process is a process of etching the overhang generated in the HDPCVD process and again depositing the HDPCVD process. In order to effectively perform the DED process, both deposition uniformity and etching uniformity must be satisfied. Particularly, when the etching uniformity is poor, the opening size is different from each other, so that some portions satisfy the gap fill and some portions do not satisfy the gap fill. In addition, if the space to be captured becomes smaller, it is often impossible to perform the DED process in the three-step process, so that the process needs to be performed in five or more steps. This has a significant effect on throughput and requires a lot of trial and error depending on the pattern profile of the process tuning. Also, as the space to be capped becomes smaller, the etching time is greatly reduced, and a desired profile can not be obtained.

상기한 바와 같은 문제점을 해결하기 위해, 플라즈마 처리 장치에서 원자층 증착 공정과 플라즈마 처리 공정을 수행하여 초미세선폭의 소자도 갭필 가능한 반도체 소자의 갭필 방법을 제공한다.In order to solve the above-described problems, a method of tapping a semiconductor device capable of capturing an ultra-fine line width by performing an atomic layer deposition process and a plasma processing process in a plasma processing apparatus is provided.

상기한 바와 같은 과제를 해결하기 위한 본 발명에 따른 반도체 소자의 갭필 방법은,According to an aspect of the present invention,

복수의 패턴들에 의해 복수의 갭이 형성된 반도체 기판이 제공되는 단계; 원자층 증착 공정을 수행하여 상기 반도체 기판 상부에 절연막을 증착하는 단계; 환원성 가스 분위기에서 고밀도 플라즈마 처리하여 상기 갭 상부에 증착된 절연막의 두께가 상기 갭 하부에 증착된 절연막의 두께보다 얇게 되도록 처리하는 단계를 포함한다.Providing a semiconductor substrate having a plurality of gaps formed by a plurality of patterns; Depositing an insulating film on the semiconductor substrate by performing an atomic layer deposition process; Density plasma processing in a reducing gas atmosphere so that the thickness of the insulating film deposited on the gap is thinner than the thickness of the insulating film deposited on the bottom of the gap.

상기 패턴들은 소자 분리막을 형성하기 위해 반도체 기판 상에 형성된 트렌치 패턴, 트랜지스터의 게이트 패턴 및 금속 배선 사이의 패턴 중 적어도 어느 하나를 포함한다.The patterns include at least one of a trench pattern formed on a semiconductor substrate to form an element isolation film, a gate pattern of the transistor, and a pattern between the metal wirings.

또한, 상기 원자층 증착 공정은, 공정 챔버에 제1 반응기체와 촉매를 공급하는 과정; 상기 반도체 기판 상에 흡착되지 못한 제1 반응기체를 제거하는 과정; 상 기 공정 챔버에 제2 반응기체와 촉매를 공급하는 과정; 및, 상기 반도체 기판 상에 흡착되지 못한 제2 반응기체를 제거하는 과정을 포함한다.The atomic layer deposition process may include: supplying a first reaction gas and a catalyst to the process chamber; Removing the first reaction gas that is not adsorbed on the semiconductor substrate; Supplying a second reaction gas and a catalyst to the process chamber; And removing the second reaction gas that is not adsorbed on the semiconductor substrate.

여기서, 상기 제1 반응기체는 상기 제1 반응기체는 SinX2n, SinOn-1X2n+2, 그리고 SinX2n+2(2≤n≤25이고, X는 F, Cl, Br, 또는 I)중에서 선택된 어느 하나 또는 이들의 혼합기체인 것이 바람직하고, 상기 제2 반응기체는 산소(O), 수소(H)를 포함하는 화합물인 것이 바람직하다. 또한, 상기 촉매는 피리딘(Pyridine) 계열의 화합물인 것이 바람직하다.Wherein the first reactant gas comprises Si n X 2n , Si n O n-1 X 2n + 2 , and Si n X 2n + 2 where 2 ? N? 25 and X is F, Cl , Br, or I), or a mixture thereof, and the second reaction gas is preferably a compound containing oxygen (O) and hydrogen (H). In addition, the catalyst is preferably a pyridine-based compound.

상기 환원성 가스는 H2, N2, NH3 중 어느 하나인 것이 바람직하다.It is preferable that the reducing gas is any one of H 2 , N 2 , and NH 3 .

또한, 상기 환원성 가스의 가스 유량은 100sccm 내지 1000sccm이며, 플라즈마 발생 장치의 소스 파워는 2kW 내지 5kW인 것이 바람직하다.It is preferable that the gas flow rate of the reducing gas is 100 sccm to 1000 sccm, and the source power of the plasma generator is 2 kW to 5 kW.

또한, 상기 고밀도 플라즈마 처리는 100sccm 내지 1000sccm의 가스 유량, 1mTorr 내지 100mTorr의 압력에서 수행되는 것이 바람직하다.The high-density plasma treatment is preferably performed at a gas flow rate of 100 sccm to 1000 sccm, and a pressure of 1 mTorr to 100 mTorr.

또한, 상기 절연막 증착 단계와 절연막 처리 단계를 적어도 2회 이상 반복하는 것이 바람직하다.It is preferable that the insulating film deposition step and the insulating film treatment step are repeated at least twice.

또한, 상기 복수의 갭을 갭필한 후, 상기 반도체 기판에 고밀도 화학기상증착 공정을 수행하는 단계를 더 포함하는 것이 바람직하다.Preferably, the method further includes performing a high-density chemical vapor deposition process on the semiconductor substrate after capturing the plurality of gaps.

본 발명은 ALD 절연막을 소정 두께 형성하고 환원성 가스 분위기에서 플라즈 마 처리하는 과정을 수행하여, 보이드 없이 미세 패턴 사이를 균일하게 갭필할 수 있다. 따라서, 보이드 등의 결함없이 미세 패턴 사이를 갭필할 수 있게 되어 소자의 특성을 향상시킬 수 있으며, 공정 시간 및 비용을 줄여 생산성을 향상시킬 수 있는 효과가 있다.In the present invention, a process of forming an ALD insulating film to a predetermined thickness and performing a plasma treatment in a reducing gas atmosphere may be performed to uniformly fill the fine patterns without voids. Therefore, it is possible to capture the fine patterns without defects such as voids, thereby improving the characteristics of the device, reducing the processing time and cost, and improving the productivity.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면에서 여러 층 및 각 영역을 명확하게 표현하기 위하여 두께를 확대하여 표현하였으며 도면상에서 동일 부호는 동일한 요소를 지칭하도록 하였다. 또한, 층, 막, 영역, 판 등의 부분이 다른 부분 “상부에” 또는 “위에” 있다고 표현되는 경우는 각 부분이 다른 부분의 “바로 상부” 또는 “바로 위에” 있는 경우뿐만 아니라 각 부분과 다른 부분의 사이에 또 다른 부분이 있는 경우도 포함한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of other various forms of implementation, and that these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know completely. In the drawings, the thickness is enlarged to clearly illustrate the various layers and regions, and the same reference numerals denote the same elements in the drawings. Also, where a section such as a layer, film, region, plate, or the like is referred to as being "on top" or "on" another section, not only when each section is "directly above" And includes another portion between the other portions.

도 1은 본 발명에 따른 반도체 소자의 갭필 방법에 이용되는 HDPCVD 장치의 단면 개략도로서, 유도 결합형 플라즈마(Inductively Coupled Plasma: 이하, "ICP"라 함) 방식의 HDPCVD 장치(100)를 나타낸 것이다.FIG. 1 is a schematic cross-sectional view of an HDPCVD apparatus used in a method of gapping a semiconductor device according to the present invention, and shows an HDPCVD apparatus 100 of an inductively coupled plasma (hereinafter referred to as "ICP") scheme.

본 발명에 이용되는 ICP 방식의 HDPCVD 장치는 기판 안치대(120) 및 인젝터 (130)가 설치된 챔버(110), 소오스 RF 전원(161) 및 제 1 정합기(162)를 포함하는 제 1 전원 공급부(160) 및 바이어스 RF 전원(171) 및 제 2 정합기(172)를 포함하는 제 2 전원 공급부(170)를 포함한다.The HDP CVD apparatus of the ICP type used in the present invention is provided with a substrate power supply 120 and a first power supply unit 130 including a chamber 110 in which an injector 130 is installed, a source RF power supply 161, And a second power supply 170 including a first RF power source 171 and a second matching device 172.

반응 영역을 형성하는 챔버(110)는 내부에 기판(200)을 안치하는 기판 안치대(120)가 설치되며, 기판 안치대(120)의 상부로 소오스 물질을 분사하는 가스 공급 수단(130)이 설치된다.The chamber 110 forming the reaction region includes a substrate placing table 120 for holding a substrate 200 therein and a gas supplying means 130 for spraying a source material onto the substrate placing table 120 Respectively.

기판 안치대(120)에는 기판(200)을 냉각시키기 위한 냉각수가 흐르는 냉각수 유로(미도시)가 더 설치될 수 있다. 그리고, 기판(200)과 기판 안치대(120)의 열전달 효율을 향상시키기 위하여 기판(200)의 후면과 기판 안치대(120)의 상부 표면에 헬륨 가스 등을 흘릴 수 있다. 이때, 기판(200)이 기판 안치대(120)로부터 이탈되지 않도록 기판(200)을 잡아주기 위해서 정전기력을 이용하는데, 기판 안치대(120) 내부에 DC 전극을 설치하여 DC 전력을 인가함으로써 기판(200)이 정전기력에 의해 기판 안치대(120)로부터 이탈되지 않도록 한다.A cooling water channel (not shown) through which cooling water for cooling the substrate 200 flows may be further provided on the substrate table 120. In order to improve the heat transfer efficiency between the substrate 200 and the substrate table 120, helium gas or the like may be supplied to the rear surface of the substrate 200 and the upper surface of the substrate table 120. At this time, an electrostatic force is used to hold the substrate 200 so that the substrate 200 is not separated from the substrate platform 120. A DC electrode is installed inside the substrate bench 120, 200 are prevented from being separated from the substrate carrying platform 120 by an electrostatic force.

가스 공급 수단(130)은 챔버(110) 하단에서 상측 방향으로 연장되고, 그 분사구가 기판(200) 상측에 마련된 형상으로 제작된다. 즉, 도면에 도시된 바와 같이 대략 '7'자 형상으로 제작된다. 물론 이에 한정되지 않고, 가스 공급 수단(130)은 복수의 인젝터로 제작될 수 있다. 예를 들어 중심에 위치하는 제 1 인젝터부와 제 1 인젝터부 외측에 마련된 제 2 인젝터부를 구비한다. 이때, 제 1 인젝터부는 봉 형상으로 제작될 수 있고, 샤워헤드 형태로 제작될 수도 있다. 그리고, 제 2 인젝터부는 제 1 인젝터부의 측면에 링 형상으로 제작되는 것이 바람직하다. 제 1 및 제 2 인젝터부를 통해 챔버(110) 내측에 공정 가스를 분사한다. 또한, 제 1 및 제 2 인젝터부는 각기 서로 다른 가스를 분사할 수도 있다. 그리고, 도시되지 않았지만, 가스 공급 수단(130)은 공정 가스가 저장된 탱크와 가스를 챔버(110) 내부로 공급하는 가스 공급부를 구비한다. 그리고, 가스 공급 수단(130)은 챔버(110)와 일체로 제작될 수도 있다. 그리고, 가스 공급 수단(130)은 복수의 부재로 제작되어 각각 서로 다른 가스를 챔버(110)의 반응 공간에 분사할 수도 있다.The gas supply unit 130 extends upward from the lower end of the chamber 110 and has a jet port formed on the substrate 200. That is, as shown in the figure, it is formed in a substantially '7' shape. Of course, the gas supply means 130 may be formed of a plurality of injectors. For example, a first injector portion located at the center and a second injector portion provided outside the first injector portion. At this time, the first injector unit may be formed into a rod shape or a showerhead shape. The second injector portion is preferably formed in a ring shape on the side surface of the first injector portion. The process gas is injected into the chamber 110 through the first and second injector portions. Further, the first and second injector portions may inject different gases. Although not shown, the gas supply means 130 includes a tank for storing the process gas and a gas supply portion for supplying the gas into the chamber 110. The gas supply means 130 may be integrally formed with the chamber 110. The gas supply unit 130 may be formed of a plurality of members and may inject different gases into the reaction space of the chamber 110.

챔버(110)의 상면에는 RF 자기장이 챔버(110) 내부로 효과적으로 전달될 수 있도록 절연 물질이 설치되는데, 절연 재질의 돔(dome)(140)이 설치될 수 있다.An insulating material is installed on the upper surface of the chamber 110 so that an RF magnetic field can be effectively transferred to the inside of the chamber 110. A dome 140 made of an insulating material may be provided.

절연 재질의 돔(140) 상부에는 안테나(150)가 설치되고, 안테나(150)에는 플라즈마를 생성하기 위한 고주파를 공급하는 제 1 전원 공급부(160)가 연결된다. 제 1 전원 공급부(160)는 소오스 RF 전원(161) 및 소오스 RF 전원(161)과 안테나(150)의 사이에 설치되어 임피던스를 정합시키는 제 1 정합기(162)를 포함한다. 또한, 안테나(150)는 나선형으로 감긴 하나의 코일을 이용할 수 있고, 서로 다른 직경을 가지고 동일 평면상에 동심원으로 배치되며 소오스 RF 전원(161)에 대하여 병렬로 연결되는 다수의 코일을 이용할 수도 있다.An antenna 150 is provided on the dome 140 and an antenna 150 is connected to a first power supply unit 160 for supplying a high frequency power for generating plasma. The first power supply unit 160 includes a first matching unit 162 disposed between the source RF power source 161 and the source RF power source 161 and the antenna 150 to match the impedances. In addition, the antenna 150 may use one coil wound in a spiral shape, and a plurality of coils may be used which are connected in parallel to the source RF power source 161, which are concentrically arranged on the same plane with different diameters .

기판 안치대(120)에는 이온을 가속시키기 위한 고주파를 공급하는 제 2 전원 공급부(170)가 설치된다. 제 2 전원 공급부(170)은 바이어스 RF 전원(171) 및 바이어스 RF 전원(171)과 기판 안치대(120) 사이에 설치되어 임피던스를 정합시키는 제 2 정합기(172)를 포함한다. The substrate table 120 is provided with a second power supply unit 170 for supplying a high frequency for accelerating ions. The second power supply unit 170 includes a bias RF power supply 171 and a second matching unit 172 installed between the bias RF power supply 171 and the substrate stand 120 to match the impedances.

한편, 챔버(110)의 하부에는 잔류 물질을 배기하는 배기구(미도시)가 더 설 치된다. 또한, 도 3에 도시된 바와 같이, 상기 돔(140)과 상기 챔버(110)의 측벽 사이에 산소 등의 가스를 공급할 수 있는 적어도 하나 이상의 가스링(190)이 더 설치될 수도 있다. 상기 가스링은 원자층 증착 공정(ALD)을 수행하기 위한 반응기체들이 공급될 수 있도록 한다. 물론, 상기 반응기체들은 가스 공급 수단(130)을 통해 공급될 수도 있다.On the other hand, an exhaust port (not shown) for exhausting the residual material is further provided in the lower portion of the chamber 110. 3, at least one gas ring 190 may be further provided between the dome 140 and the side wall of the chamber 110 to supply a gas such as oxygen. The gas ring makes it possible to supply reactive gases for performing the atomic layer deposition process (ALD). Of course, the reactive gases may be supplied through the gas supply means 130.

상기와 같이 구성된 HDPCVD 장치(100)는 가스 공급 수단(130)을 통해 예를들어 실란(SiH4), 산소(O2) 등의 소오스 물질 또는 식각 가스를 챔버(110) 내부로 분사하고, 소오스 RF 전원(161)을 인가하면, 안테나(150)에 의하여 챔버(110) 내부에 발생된 유도 전기장이 전자를 가속시키고, 가속된 전자가 중성기체와 충돌함으로써 이온, 활성종 및 전자의 혼합체인 플라즈마가 발생한다.The HDPCVD apparatus 100 configured as described above injects a source material such as silane (SiH 4 ) or oxygen (O 2 ) or etch gas into the chamber 110 through the gas supply means 130, When the RF power source 161 is applied, an induction electric field generated in the chamber 110 by the antenna 150 accelerates electrons, and accelerated electrons collide with the neutral gas, thereby generating a plasma, which is a mixture of ions, Lt; / RTI >

플라즈마가 발생되면, 플라즈마와 기판(200) 사이에 전위차가 발생되는데, 이를 플라즈마의 쉬스(sheath) 영역이라 한다. 쉬스 영역의 전위차에 의하여 이온이 기판(200)을 향하여 가속되어 기판(200)의 트렌치에 절연막, 예를들어 실리콘 산화막이 증착된다. 또한, 식각 가스를 유입하고 플라즈마를 발생시킨 후 기판(200)에 바이어스 RF 전원(171)을 인가하면 이온화된 식각 가스의 가속도가 증가하여 이온이 기판(200)에 입사하여 이미 기판(200)에 증착된 절연막을 식각하게 된다. 이러한 과정을 반복하여 기판(200) 상에 박막이 형성되며, 절연막 증착시 RF 바이어스 전원(171)을 인가하여 식각 비율을 조절할 수도 있다.When a plasma is generated, a potential difference is generated between the plasma and the substrate 200, which is called a sheath region of the plasma. Ions are accelerated toward the substrate 200 by the potential difference of the sheath region, and an insulating film, for example, a silicon oxide film is deposited on the trench of the substrate 200. When the bias RF power supply 171 is applied to the substrate 200 after the etching gas is introduced and the plasma is generated, the acceleration of the ionized etching gas is increased so that the ions are incident on the substrate 200, And the deposited insulating film is etched. A thin film is formed on the substrate 200 by repeating this process, and the etching rate can be controlled by applying an RF bias power source 171 when depositing the insulating film.

또한, 상기 ICP 뿐만 아니라 용량 결합형 플라즈마(Capacitively Coupled Plasma; CCP), 마이크로파를 이용하는 전자 사이클로트론 공진(Electron Cyclotron Resonance; ECR) 플라즈마, 헬리콘(Helicon)파를 이용하는 헬리콘 플라즈마 등 다양한 고밀도 플라즈마를 이용할 수 있다.In addition to the ICP, various high-density plasmas such as capacitively coupled plasma (CCP), electron cyclotron resonance (ECR) plasma using a microwave, and Helicon plasma using a Helicon wave can be used .

도 2a 내지 도 2d는 전술한 HDPCVD 장치를 사용하는 본 발명에 따른 반도체 소자의 갭필 방법을 도시한 공정도이고, 도 3은 본 발명에 따른 반도체 소자의 갭필 방법에 사용되는 또 다른 HDPCVD 장치의 단면 개략도, 도 4는 본 발명에 따른 반도체 소자의 갭필 방법을 도시한 순서도이다. 이하, 도 2a 내지 도 2d 및 도 3을 함께 설명한다.FIGS. 2A to 2D are process charts showing a method of gliding a semiconductor device according to the present invention using the HDPCVD apparatus described above, and FIG. 3 is a schematic cross-sectional view of another HDPCVD apparatus used in a method of glitching a semiconductor device according to the present invention , And FIG. 4 is a flowchart showing a method of capturing a semiconductor device according to the present invention. Hereinafter, Figs. 2A to 2D and Fig. 3 will be described together.

먼저, 도 2a를 참조하면, 상기 HDPCVD 장치의 공정 챔버에 복수의 패턴들(P)에 의해 복수의 갭(G)이 형성된 반도체 기판(210)을 제공한다.(S10) 이때, 상기 패턴들(P)은 소자 분리막을 형성하기 위해 반도체 기판 상에 형성된 트렌치 패턴, 트랜지스터의 게이트 패턴 및 금속 배선 사이의 패턴 중 적어도 어느 하나이다. 물론 상기의 패턴 이외의 패턴일 수도 있다. 또한, 공정 챔버에 반도체 기판(210)을 제공할 때, 상기 반도체 기판(210)을 미리 예열한다.(S11)2A, a semiconductor substrate 210 having a plurality of gaps G formed by a plurality of patterns P in a process chamber of the HDPCVD apparatus is provided. (S10) At this time, P is at least one of a trench pattern formed on a semiconductor substrate to form an element isolation film, a gate pattern of a transistor, and a pattern between metal wirings. Of course, it may be a pattern other than the above pattern. In addition, when the semiconductor substrate 210 is provided in the process chamber, the semiconductor substrate 210 is preheated in advance (S11)

그 다음, 도 2b를 참조하면, 상기 HDPCVD 장치로 원자층 증착 공정(ALD)을 수행하여 상기 반도체 기판(210) 상부에 절연막(220)을 증착한다.Referring to FIG. 2B, an ALD process is performed on the HDPCVD apparatus to deposit an insulating layer 220 on the semiconductor substrate 210.

상기 반도체 기판(210) 위에 절연막(220)을 증착하기 위해, 먼저 공정 챔버에 제1 반응기체와 촉매를 공급하여 제1 반응물을 형성한다.(S21) 여기서, 상기 제 1 반응기체는 SinX2n, SinOn-1X2n+2, 그리고 SinX2n+2(2≤n≤25이고, X는 F, Cl, Br, 또는 I)중 어느 하나 또는 이들의 혼합기체인 것이 바람직하다. 그 다음, 상기 반도체 기판 상에 흡착되지 못한 제1 반응기체를 퍼지가스를 이용하여 제거한다.(S22) 그 다음, 상기 공정 챔버에 제2 반응기체와 촉매를 공급하여 반도체 기판 상에 제2 반응물을 형성하여 이산화실리콘 박막을 성장시킨다.(S23) 여기서, 상기 제2 반응기체는 예를 들면 H2O, 또는 H2O2와 같은 산소(O), 수소(H)를 포함하는 화합물인 것이 바람직하다. 또한, 여기서 상기 제1 및 제2 반응기체와의 반응에 사용되는 촉매는 피리딘(Pyridine) 계열의 화합물인 것이 바람직하다. 그 다음, 상기 반도체 기판 상에 흡착되지 못한 제2 반응기체를 퍼지가스를 이용하여 제거함으로써 절연막(220)을 증착을 위한 한 주기의 과정이 완료된다.(S24) 이때, 상기 증착된 절연막(220)의 두께가 원하는 두께에 이르지 못한 경우, 원하는 두께에 이를 때까지 상기의 과정을 반복한다.(S30) 이때, 상기 제1, 제2 반응기체는 상기 가스 공급 수단(130)(도 1 참조)을 통해 공급될 수 있거나, 상기 가스링(190)(도 3 참조)을 통해 공급될 수 있다.In order to deposit the insulating layer 220 on the semiconductor substrate 210, a first reactant and a catalyst are supplied to the process chamber to form a first reactant (S21). Here, the first reactant gas includes Si n X 2 n , Si n O n-1 X 2n + 2 , and Si n X 2n + 2 ( 2 ? N? 25 and X is F, Cl, Br or I) . Next, the first reaction gas which is not adsorbed on the semiconductor substrate is removed by using a purge gas. (S22) Next, a second reaction gas and a catalyst are supplied to the process chamber, to form a grown silicon dioxide thin film. (S23) the second reaction gas, for example, be a compound containing oxygen (O), hydrogen (H), such as H 2 O, or H 2 O 2 desirable. The catalyst used for the reaction with the first and second reaction gases is preferably a pyridine-based catalyst. Then, the second reaction gas that is not adsorbed on the semiconductor substrate is removed by using a purge gas, so that the process of one cycle for depositing the insulating film 220 is completed. (S24) At this time, the deposited insulating film 220 (S30), the first and second reaction gases are supplied to the gas supply means 130 (see FIG. 1) Or may be supplied through the gas ring 190 (see FIG. 3).

상기와 같이 절연막(220)이 원하는 두께에 이른 경우, 절연막 증착 과정을 중단하고, 환원성 가스를 공급하여 공정 챔버 내에 환원성 가스 분위기를 조성한 후 플라즈마 처리한다.(S40) 이때, 상기 환원성 가스는 H2, N2, NH3 중 어느 하나인 것이 바람직하다. 또한, 상기 환원성 가스의 가스 유량은 100sccm 내지 1000sccm인 것이 바람직하다. 이는 환원성 가스가 소스 파워(source power)에 의해 분해되어 절연막 형성에 필요한 충분한 량의 개수를 만들어 주기에 적정한 수치이다.If early in thickness the insulating film 220 is desired as described above, stops the insulating film deposition process and the plasma processing after joseonghan a reducing gas atmosphere in the feed to the process chamber, a reducing gas. (S40) At this time, the reductive gas is H 2 , N 2 , and NH 3 . It is preferable that the gas flow rate of the reducing gas is 100 sccm to 1000 sccm. This is a suitable value to make the reducing gas decompose by the source power to make a sufficient number of necessary for forming the insulating film.

상기와 같은 환원성 가스 분위기에서 고밀도 플라즈마 처리하면, 상기 갭(G) 상부(도 2c의 'A'부분) 주변의 절연막은 환원성 가스와 화학 반응하여 제거되어 두께가 얇아진다. 반면에, 상기 갭 하부로 갈수록 환원성 가스와 접촉하는 면적이 줄어 들게 되므로, 도 2c의 'A' 부분 보다는 화학 반응이 잘 일어나지 않게 된다. 그 결과, 상기 갭 상부에 증착된 절연막의 두께가 상기 갭 하부에 증착된 절연막의 두께보다 얇은 절연막 형상(221)이 형성된다. 이로 인해 상기 절연막 형상(221)의 프로파일(profile)은 갭필에 유리한 상광하협의 구조가 된다.(도 2c, 2d 참조)When the high density plasma treatment is performed in the reducing gas atmosphere as described above, the insulating film around the upper part of the gap G ('A' part in FIG. 2C) is chemically reacted with the reducing gas to be removed and thinned. On the other hand, since the area of contact with the reducing gas decreases toward the bottom of the gap, the chemical reaction does not occur more easily than the portion 'A' in FIG. 2C. As a result, an insulating film shape 221 in which the thickness of the insulating film deposited on the gap is thinner than the thickness of the insulating film deposited on the lower portion of the gap is formed. Thus, the profile of the insulating film shape 221 becomes a structure of phase-weakly narrowing which is advantageous for tapping (see FIGS. 2C and 2D).

이때, 상기 환원성 가스의 가스 유량은 100sccm 내지 1000sccm이며, 플라즈마 발생 장치의 소스 파워는 2kW 내지 5kW인 것이 바람직하다. 또한, 상기 고밀도 플라즈마 처리는 100sccm 내지 1000sccm의 가스 유량, 1mTorr 내지 100mTorr의 압력에서 수행되는 것이 바람직하다.At this time, the gas flow rate of the reducing gas is 100 sccm to 1000 sccm, and the source power of the plasma generator is preferably 2 kW to 5 kW. The high-density plasma treatment is preferably performed at a gas flow rate of 100 sccm to 1000 sccm, and a pressure of 1 mTorr to 100 mTorr.

만약, 상기 플라즈마 처리 후에 절연막 형상(221)의 두께가 원하는 두께에 이르지 못한 경우, 원하는 두께에 이를 때까지 상기 S21 단계부터 S40 단계를 반복한다. 즉, 상기 절연막 형상(221) 위에 상기 절연막 증착 단계와 절연막 형상 형성 단계를 적어도 1회 이상 반복하여 또 다른 절연막 형상(222)을 형성한다. 이러한 절연막 형상 형성 단계를 상기 복수의 갭(G)에 오버행이 생기지 않을 정도까지 반복한다.(S50)If the thickness of the insulating film shape 221 does not reach the desired thickness after the plasma treatment, steps S21 to S40 are repeated until the desired thickness is reached. That is, the insulating film shape 221 and the insulating film shape forming step are repeated at least once to form another insulating film shape 222. This insulating film shape forming step is repeated until there is no overhang in the plurality of gaps G. (S50)

이 후에, 동일한 HDPCVD 장치 내에서, 오버행이 생기지 않을 정도의 높이까지 갭이 갭필된 반도체 기판 위에 고밀도 플라즈마 화학기상증착법으로 절연막(미 도시)을 증착하여, 여분의 갭과 상기 반도체 기판 전면을 증착한다.(S60)Thereafter, in the same HDPCVD apparatus, an insulating film (not shown) is deposited by a high-density plasma chemical vapor deposition method on a semiconductor substrate which has been gapped to a height at which no overhang occurs, thereby depositing an extra gap and the entire surface of the semiconductor substrate . (S60)

그 다음, 상기 반도체 기판을 꺼내어 통상의 과정을 거쳐 반도체 소자를 제조한다.(S70)Then, the semiconductor substrate is taken out and a semiconductor device is manufactured through a normal process (S70)

이상에서 본 발명의 설명의 편리를 위해 일부 공정들에 대한 설명이 생략되었지만, 생략된 공정들은 일반적으로 널리 알려진 공지 기술로서, 본 발명의 사상을 크게 저해하지는 않을 것이다.Although the descriptions of some processes have been omitted for the sake of convenience of description of the present invention, the omitted processes are generally well known and will not significantly hinder the idea of the present invention.

도 1은 본 발명에 따른 반도체 소자의 갭필 방법에 사용되는 HDPCVD 장치의 단면 개략도,1 is a schematic cross-sectional view of an HDPCVD apparatus used in a method of glitching semiconductor devices according to the present invention,

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 갭필 방법을 도시한 공정도,FIGS. 2A to 2D are process charts showing a method of glitching a semiconductor device according to the present invention,

도 3은 본 발명에 따른 반도체 소자의 갭필 방법에 사용되는 또 다른 HDPCVD 장치의 단면 개략도,3 is a cross-sectional schematic view of another HDPCVD apparatus used in a method of glitching semiconductor devices according to the present invention,

도 4는 본 발명에 따른 반도체 소자의 갭필 방법을 도시한 순서도이다.4 is a flowchart showing a method of capturing a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명>Description of the Related Art

P : 패턴 G : 갭P: pattern G: gap

210 : 반도체 기판 220 : 절연막210: semiconductor substrate 220: insulating film

221, 222 : 절연막 형상221, 222: insulating film shape

Claims (11)

복수의 패턴들에 의해 복수의 갭이 형성된 반도체 기판이 제공되는 단계;Providing a semiconductor substrate having a plurality of gaps formed by a plurality of patterns; 원자층 증착 공정을 수행하여 상기 반도체 기판 상부에 절연막을 증착하여 상기 복수의 갭의 적어도 일부 두께를 매립하는 단계;Performing an atomic layer deposition process to deposit an insulating film on the semiconductor substrate to fill at least a part of the thickness of the plurality of gaps; H2, N2, NH3 중 어느 하나의 환원성 가스를 주입하는 단계; 및Injecting a reducing gas selected from the group consisting of H 2 , N 2 , and NH 3 ; And 상기 환원성 가스 분위기에서 고밀도 플라즈마 처리하여 상기 갭 상부에 증착된 절연막의 두께가 상기 갭 하부에 증착된 절연막의 두께보다 얇게 되도록 처리하는 단계를 포함하는 반도체 소자의 갭필 방법.And performing a high-density plasma treatment in the reducing gas atmosphere so that the thickness of the insulating film deposited on the gap becomes thinner than the thickness of the insulating film deposited on the bottom of the gap. 청구항 1에 있어서,The method according to claim 1, 상기 패턴들은 소자 분리막을 형성하기 위해 반도체 기판 상에 형성된 트렌치 패턴, 트랜지스터의 게이트 패턴 및 금속 배선 사이의 패턴 중 적어도 어느 하나를 포함하는 반도체 소자의 갭필 방법.Wherein the patterns include at least one of a trench pattern formed on a semiconductor substrate to form an element isolation film, a gate pattern of the transistor, and a pattern between the metal wirings. 청구항 1에 있어서,The method according to claim 1, 상기 원자층 증착 공정은,In the atomic layer deposition process, 공정 챔버에 제1 반응기체와 촉매를 공급하는 과정;Supplying a first reaction gas and a catalyst to the process chamber; 상기 반도체 기판 상에 흡착되지 못한 제1 반응기체를 제거하는 과정;Removing the first reaction gas that is not adsorbed on the semiconductor substrate; 상기 공정 챔버에 제2 반응기체와 촉매를 공급하는 과정; 및,Supplying a second reaction gas and a catalyst to the process chamber; And 상기 반도체 기판 상에 흡착되지 못한 제2 반응기체를 제거하는 과정And removing the second reactive gas that is not adsorbed on the semiconductor substrate 을 포함하는 반도체 소자의 갭필 방법.The method comprising the steps of: 청구항 3에 있어서,The method of claim 3, 상기 제1 반응기체는 SinX2n, SinOn-1X2n+2, 그리고 SinX2n+2(2≤n≤25이고, X는 F, Cl, Br, 또는 I)중에서 선택된 어느 하나 또는 이들의 혼합기체인 반도체 소자의 갭필 방법.Wherein the first reactive gas is selected from Si n X 2n , Si n O n-1 X 2n + 2 , and Si n X 2n + 2 where 2 ? N? 25 and X is F, Cl, Br, A method of gauging a semiconductor device, which is either one or a mixture thereof. 청구항 3에 있어서,The method of claim 3, 상기 제2 반응기체는 산소(O), 수소(H)를 포함하는 화합물인 반도체 소자의 갭필 방법.Wherein the second reactive gas is a compound containing oxygen (O) and hydrogen (H). 청구항 3에 있어서,The method of claim 3, 상기 촉매는 피리딘(Pyridine) 계열의 화합물인 반도체 소자의 갭필 방법.Wherein the catalyst is a pyridine based compound. 삭제delete 청구항 1에 있어서,The method according to claim 1, 상기 환원성 가스의 가스 유량은 100sccm 내지 1000sccm이며, 플라즈마 발생 장치의 소스 파워는 2kW 내지 5kW인 반도체 소자의 갭필 방법.Wherein the gas flow rate of the reducing gas is 100 sccm to 1000 sccm, and the source power of the plasma generator is 2 kW to 5 kW. 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 has been abandoned due to the setting registration fee. 청구항 1에 있어서,The method according to claim 1, 상기 고밀도 플라즈마 처리는 100sccm 내지 1000sccm의 가스 유량, 1mTorr 내지 100mTorr의 압력에서 수행되는 반도체 소자의 갭필 방법.Wherein the high density plasma treatment is performed at a gas flow rate of 100 sccm to 1000 sccm and a pressure of 1 mTorr to 100 mTorr. 청구항 1 내지 청구항 6, 청구항 8 및 청구항 9 중 어느 한 항에 있어서,The method according to any one of claims 1 to 6, 8, and 9, 상기 절연막 증착 단계, 환원성 가스 공급 단계 및 플라즈마 처리 단계를 적어도 2회 이상 반복하여 상기 복수의 갭을 갭필하는 반도체 소자의 갭필 방법.Wherein the step of depositing the insulating film, the step of supplying the reducing gas, and the step of plasma processing are repeated at least twice to capture the plurality of gaps. 청구항 11은(는) 설정등록료 납부시 포기되었습니다.Claim 11 has been abandoned due to the set registration fee. 청구항 10에 있어서,The method of claim 10, 상기 복수의 갭을 갭필한 후, 상기 반도체 기판에 고밀도 화학기상증착 공정을 수행하는 단계를 더 포함하는 반도체 소자의 갭필 방법.And performing a high density chemical vapor deposition process on the semiconductor substrate after capturing the plurality of gaps.
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