CN117672961A - Method for forming semiconductor device - Google Patents
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- CN117672961A CN117672961A CN202211037868.XA CN202211037868A CN117672961A CN 117672961 A CN117672961 A CN 117672961A CN 202211037868 A CN202211037868 A CN 202211037868A CN 117672961 A CN117672961 A CN 117672961A
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- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000010438 heat treatment Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 13
- 238000005498 polishing Methods 0.000 claims description 10
- 239000007788 liquid Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000007517 polishing process Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 239000012530 fluid Substances 0.000 claims description 3
- 239000003112 inhibitor Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000003749 cleanliness Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 239000003223 protective agent Substances 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate, and forming an initial connection layer on the substrate; flattening the initial connection layer and forming a connection layer on the substrate; carrying out heat treatment on the surface of the connecting layer; the residues on the surface of the connecting layer can be removed by carrying out heat treatment on the surface of the connecting layer; the surface cleanliness of the connecting layer is improved, so that an upper conductive layer is formed on the connecting layer subsequently, the upper conductive layer is guaranteed to have a good forming surface in the forming process, the connecting quality between the upper conductive layer and the connecting layer is improved, the protruding or uneven phenomenon of the upper conductive layer in the forming process is reduced, the forming quality of the upper conductive layer is improved, and the performance of a semiconductor device finally formed is guaranteed.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor device.
Background
As integrated circuits move to very large scale integrated circuits, the density of circuits within the integrated circuits increases and the number of devices included therein increases, which results in the inability of the wafer surface to provide sufficient area to make the desired interconnections.
In order to meet the requirements of the interconnection lines after the device is scaled down, the design of two or more layers of multi-layer metal interconnection lines is a common method for very large scale integrated circuit technology. At present, the conduction between the metal layer and the substrate is realized through a contact hole structure.
The contact hole structure is formed to form metal contact in the active region, and is generally formed by forming a contact hole in a dielectric layer of the active region, filling a connecting layer in the contact hole, and realizing the connection relationship between the upper and lower metal layers of the contact hole by using the connecting layer.
At present, residues exist on the surface of the connection layer due to the chemical agent used in the process of forming the connection layer, and the residues affect the quality of the material layer formed on the surface of the connection layer, thereby resulting in poor performance of the finally formed semiconductor device.
Disclosure of Invention
The invention solves the problem of providing a method for forming a semiconductor device to improve the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, and forming an initial connection layer on the substrate; flattening the initial connection layer and forming a connection layer on the substrate; and carrying out heat treatment on the surface of the connecting layer.
Optionally, the gas used for the heat treatment comprises nitrogen and/or hydrogen.
Alternatively, the temperature of the heat treatment is in the range of 200 ℃ to 400 ℃.
Alternatively, the heat treatment time is 1min to 10min.
Optionally, the material of the connection layer is cobalt, tungsten or copper.
Optionally, the step of forming an initial connection layer on the substrate includes: forming a dielectric layer on a substrate; etching the dielectric layer to form a contact hole in the dielectric layer, wherein the bottom of the contact hole exposes the surface of the conductive layer on the substrate; an initial connection layer is formed in the contact hole and on the dielectric layer.
Optionally, planarizing the initial connection layer to form a connection layer on the substrate, including: and flattening the initial connection layer until the surface of the dielectric layer is exposed, and forming the connection layer in the contact hole.
Optionally, after the heat treatment, the method further comprises cleaning the surface of the connection layer.
Optionally, the process of planarizing the initial connection layer is a chemical mechanical polishing process.
Optionally, the process parameters of the chemical mechanical polishing process include that the polishing liquid is a polishing liquid containing silicon dioxide particles and a metal corrosion inhibitor; grinding time is 1min to 3min; the flow rate of the grinding fluid is 200ml/min to 500ml/min.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the structure, after flattening an initial connecting layer, forming the connecting layer on a substrate, wherein residues are formed on the surface of the connecting layer; the residues on the surface of the connecting layer can be removed by carrying out heat treatment on the surface of the connecting layer; and the surface cleanliness of the connecting layer is improved. Therefore, the upper conductive layer is formed on the connecting layer subsequently, the upper conductive layer is guaranteed to have a good forming surface in the forming process, the connection quality between the upper conductive layer and the connecting layer is improved, the protruding or uneven phenomenon of the upper conductive layer in the forming process is reduced, the forming quality of the upper conductive layer is improved, and the performance of a finally formed semiconductor device is guaranteed.
Drawings
Fig. 1 to 2 are schematic views showing a structure of a forming process of a semiconductor device;
fig. 3 to 6 are schematic views illustrating a formation process of a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background art, when a material layer is formed on a connection layer after a connection layer is formed in a contact hole structure, the formation quality of the material layer is affected, resulting in poor quality of a semiconductor device finally formed, and specific processes refer to fig. 1 to 2.
Referring to fig. 1, a dielectric layer 100 is provided, and a contact hole structure (not labeled in the figure) is provided in the dielectric layer 100; the contact hole structure is filled with the initial connection layer 101.
Further, referring to fig. 2, the initial connection layer 101 is planarized, and a connection layer 102 is formed in the contact hole structure, wherein a top surface of the connection layer 102 is flush with a top surface of the dielectric layer 100.
However, the method of planarizing the initial connection layer 101 is a chemical mechanical polishing method, and a protecting agent is added into the polishing liquid to protect the connection layer during the planarization process, so as to reduce the damage of the connection layer. However, this protective agent may undergo a chelating reaction with the tie layer, thereby generating residues 103 on the surface of the tie layer. Such residues 103 are difficult to clean completely during the subsequent cleaning process, so that when the upper material layer is formed on the connection layer 102, the upper material layer cannot be well formed on the connection layer 102 due to the existence of the residues, which results in abnormal growth of the upper material layer, such as protrusion or non-uniformity of the upper material layer, which results in poor formation quality of the upper material layer, thereby resulting in poor performance of the finally formed semiconductor device.
On the basis, the invention provides a method for forming a semiconductor device, which comprises the steps of flattening an initial connecting layer, forming a connecting layer on a substrate, and forming residues on the surface of the connecting layer; the residues on the surface of the connecting layer can be removed by carrying out heat treatment on the surface of the connecting layer; and the surface cleanliness of the connecting layer is improved. Therefore, the upper conductive layer is formed on the connecting layer subsequently, the upper conductive layer is guaranteed to have a good forming surface in the forming process, the connection quality between the upper conductive layer and the connecting layer is improved, the protruding or uneven phenomenon of the upper conductive layer in the forming process is reduced, the forming quality of the upper conductive layer is improved, and the performance of a finally formed semiconductor device is guaranteed.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 6 are schematic views illustrating a formation process of a semiconductor device according to an embodiment of the present invention.
First, referring to fig. 3, a substrate 200 is provided.
In this embodiment, the base 200 includes a substrate (labeled in the figure), a fin (labeled in the figure) on the substrate, and a gate structure (labeled in the figure) on the substrate, the gate structure crossing the fin.
In other embodiments, the base 200 includes a substrate (labeled in the figures) and a gate structure (labeled in the figures) located on the substrate.
In this embodiment, the substrate 200 has a conductive layer 201 thereon.
The conductive layer 201 may be a source-drain doped layer or an interconnect metal layer.
In this embodiment, the substrate is made of a semiconductor material such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, gallium arsenide, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
With continued reference to fig. 3, a dielectric layer 202 is formed on a substrate 200.
The material of the dielectric layer 202 may be one or more of silicon carbide, silicon oxide, silicon nitride, and the like.
In this embodiment, the material of the dielectric layer 202 is silicon oxide.
In this embodiment, the process of forming the dielectric layer 202 is a chemical vapor deposition process. In other embodiments, physical vapor deposition or atomic layer vapor deposition may also be used to form dielectric layer 202.
In this embodiment, the dielectric layer 202 is formed by chemical vapor deposition, and the process parameters of the chemical vapor deposition include the gases including oxygen and ammonia (NH) 3 ) And N (SiH) 3 ) 3 The flow rate of the gas and the oxygen is 20sccm to 10000sccm, and the ammonia (NH) 3 ) The flow rate of the gas is 20sccm to 10000sccm, and N (SiH) 3 ) 3 The flow rate of the gas is 20 sccm-10000 sccm, the pressure of the chamber is 0.01-10 Torr, and the temperature is 30-90 ℃.
With continued reference to fig. 3, the dielectric layer 202 is etched, and a contact hole 203 is formed in the dielectric layer 202, and the bottom of the contact hole 203 exposes the surface of the conductive layer 201 on the substrate 200.
In the present embodiment, the process of forming the contact hole 203 is a dry etching process. In other embodiments, the process of forming the contact hole 203 is a wet etching process, a dry etching process, or a combination of a wet and dry etching process.
In the present embodiment, the reason why the contact hole 203 is formed by dry etching is that the dry etching has a strong etching directivity, and the etching rate of the dry etching process in the longitudinal direction is greater than that in the transverse direction, so that it can be ensured that the surrounding devices are not damaged in the process of forming the contact hole 203.
In this embodiment, specific parameters of the dry etching process include: the gas used comprises CF 4 Gas, CH 3 F gas and O 2 ，CF 4 The flow rate of the gas is 5 sccm-100 sccm, CH 3 The flow rate of F gas is 8 sccm-50 sccm, O 2 The flow of the liquid is 10 sccm-100 sccm, the pressure of the chamber is 10 mtorr-2000 mtorr, the radio frequency power is 50W-300W, the bias voltage is 30V-100V, and the time is 4 seconds-50 seconds.
Referring to fig. 4, an initial connection layer 204 is formed on a substrate 200.
In this embodiment, an initial connection layer 204 is formed within the contact hole 203 and on the dielectric layer 202.
In the present embodiment, the initial connection layer 204 is formed by forming a metal seed layer (not shown) of the initial connection layer on the sidewall of the contact hole 203; and depositing a metal layer on the metal seed layer of the initial connection layer, thereby forming the initial connection layer.
In this embodiment, the process parameters of forming the metal seed layer of the initial connection layer include: with the organic source being CCTBA, the reactant gas includes hydrogen (H 2 ) And argon (Ar), wherein hydrogen (H 2 ) The flow rate of the gas is 1000-8000 sccm, and the flow rate of the argon (Ar) is 10-500 sccm; the source radio frequency power is 100-2000W, the temperature is 100-400 ℃, and the pressure is 10-40 Torr.
In this embodiment, after the metal seed layer is formed, the electroless plating is used to deposit the metal layer to form the initial connection layer 204. Since the electroless plating process is essentially performed by connecting the wafer to the cathode and placing it in an acidic solution containing the metal ions to be deposited, cobalt to be deposited is also placed in the solution, so that current flows from the cobalt electrode of the anode to the wafer of the cathode, the ionized ions nucleate on the metal seed layer, and finally the initial connection layer 204 is formed.
Further, referring to fig. 5, the initial connection layer 204 is planarized, and a connection layer 205 is formed on the substrate 200.
In this embodiment, the material of the connection layer 205 is cobalt.
In other embodiments, the material of the connection layer 205 may also be titanium.
In this embodiment, the initial connection layer 204 is planarized until the surface of the dielectric layer 202 is exposed, and a connection layer 205 is formed in the contact hole 203.
In this embodiment, the process of planarizing the initial connection layer 204 is a chemical mechanical polishing process.
In this embodiment, the process parameters of the chemical mechanical polishing process include that the polishing liquid is a polishing liquid containing silica particles and a metal corrosion inhibitor; grinding time is 1min to 3min; the flow rate of the grinding fluid is 200 ml/min-500 ml/min.
In this embodiment, in the process of flattening the initial connection layer 204, a protective agent is added into the polishing solution to initially connect the layer 204, so as to reduce the damage of the initial connection layer 204, thereby forming a connection layer 205 with good quality; however, due to the addition of the protecting agent, the protecting agent may react with the material of the initial connection layer in a chelating manner during the polishing process, so that an organic residue 206 remains on the surface of the formed connection layer 205 after chemical polishing, and thus the organic residue 206 is difficult to clean completely during the cleaning process, which results in poor surface formation quality of the connection layer 205, and when the upper conductive layer is formed on the connection layer, the upper conductive layer cannot be well formed on the connection layer 205, so that abnormal growth of the upper conductive layer occurs, such as protrusion or non-uniformity of the upper conductive layer, which results in poor quality of the final formed upper conductive layer and affects the performance of the formed semiconductor device.
Referring to fig. 6, the surface of the connection layer 205 is heat treated.
In this embodiment, the gas used for the heat treatment includes one or a combination of nitrogen and hydrogen.
In this embodiment, the temperature range of the heat treatment is 200 ℃ to 400 ℃; when the temperature of the heat treatment is less than 200 ℃, the temperature is too low to reach the volatilization point of the organic residues 206, and the organic residues 206 are difficult to clean; when the temperature of the heat treatment is higher than 400 ℃, the metal diffusion phenomenon can occur and the electrical property of the semiconductor device is affected.
In this embodiment, the time of the heat treatment is 1min to 10min; when the heat treatment time is less than 1min, the heat treatment time is too short, which is not beneficial to cleaning the organic residues; when the heat treatment time is longer than 10min, the metal electrical property is unstable.
In this embodiment, in the process of performing heat treatment on the connection layer 205, the heat treatment temperature and the heat treatment time are combined, so that the formation quality of the connection layer 205 after heat treatment is well controlled, and the surface quality of the formed connection layer 205 can be ensured without affecting the formation quality of the connection layer 205; and meanwhile, the reasonable heat treatment temperature control and the heat treatment time control ensure that the heat treatment can not cause heat accumulation of the semiconductor device, avoid the influence of electron mobility, threshold voltage and the like of the semiconductor device, and ensure the service performance of the semiconductor device.
In this embodiment, during the heat treatment, the organic residue 206 is evaporated by heat and removed from the surface of the connection layer 205, thereby improving the surface cleanliness of the connection layer 205. Therefore, the upper conductive layer is formed on the connecting layer subsequently, the upper conductive layer is guaranteed to have a good forming surface in the forming process, the connection quality between the upper conductive layer and the connecting layer is improved, the protruding or uneven phenomenon of the upper conductive layer in the forming process is reduced, the forming quality of the upper conductive layer is improved, and the performance of a finally formed semiconductor device is guaranteed.
In this embodiment, after the heat treatment, the surface of the connection layer is further cleaned.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising the steps of:
providing a substrate, and forming an initial connection layer on the substrate;
flattening the initial connection layer and forming a connection layer on the substrate;
and carrying out heat treatment on the surface of the connecting layer.
2. The method for forming a semiconductor device according to claim 1, wherein the gas used for the heat treatment includes nitrogen and/or hydrogen.
3. The method for forming a semiconductor device according to claim 1, wherein a temperature of the heat treatment is in a range of 200 ℃ to 400 ℃.
4. The method for forming a semiconductor device according to claim 1, wherein the time of the heat treatment is 1min to 10min.
5. The method of forming a semiconductor device according to claim 1, wherein a material of the connection layer is cobalt, tungsten, or copper.
6. The method of forming a semiconductor device according to claim 1, wherein the step of forming an initial connection layer on the substrate comprises: forming a dielectric layer on the substrate; etching the dielectric layer, forming a contact hole in the dielectric layer, and exposing the surface of the conductive layer on the substrate at the bottom of the contact hole; and forming the initial connection layer in the contact hole and on the dielectric layer.
7. The method of forming a semiconductor device of claim 6, wherein planarizing the initial connection layer, forming the connection layer on the substrate, comprises: and flattening the initial connection layer until the surface of the dielectric layer is exposed, and forming the connection layer in the contact hole.
8. The method for forming a semiconductor device according to claim 1, further comprising, after performing the heat treatment: and cleaning the surface of the connection layer after heat treatment.
9. The method of claim 1, wherein the process of planarizing the initial contact layer is a chemical mechanical polishing process.
10. The method of forming a semiconductor device according to claim 9, wherein the process parameters of the chemical mechanical polishing process include that the polishing liquid is a polishing liquid containing silica particles and a metal corrosion inhibitor; grinding time is 1min to 3min; the flow rate of the grinding fluid is 200ml/min to 500ml/min.
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|---|---|---|---|
| CN202211037868.XA CN117672961A (en) | 2022-08-26 | 2022-08-26 | Method for forming semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211037868.XA CN117672961A (en) | 2022-08-26 | 2022-08-26 | Method for forming semiconductor device |
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| CN117672961A true CN117672961A (en) | 2024-03-08 |
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| CN202211037868.XA Pending CN117672961A (en) | 2022-08-26 | 2022-08-26 | Method for forming semiconductor device |
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