NL8001026A - DIGITAL SIGNAL RECEIVER FOR RECEIVING PCM SHOWS. - Google Patents

Description

i

Digital signal receiver for receiving PCM tones.

The invention generally relates to tone signal receivers and more particularly to a digitally arranged receiver for converting pulse code modulated (PCM) tone signals into a signal expression compatible with a controller in a telephone switching center.

Telephone signal receivers for receiving multi-frequency subscriber loop signaling or multi-frequency (MF) long-distance signaling have evolved from analog in digital circuits as exemplified in U.S. Pat. No. 3,537,001, and U.S. Pat. No. 3,790,720 . However, these receivers are intended to receive analog signals and cannot be directly adapted to receive digital signals. Accordingly, in a time division multiplex (TDM) pulse code modulation (PCM) telephone system, a digital-analog converter is used to convert PCM samples from a selected TDM channel into an analog signal. The signal receiver then detects the appropriate signals and converts the signals into a code compatible with the operation of an associated TDM switching center.

The use of digital signal processing devices for processing digital signals without first converting the digital signals to analog form is discussed by S.L. Freeny, in a publication entitled "Special Purpose Hardware for Digital Filtering" in the proceedings of the IEEE, vol. 63, 25 pp. 633-648, published April 1975, and by J. Allen, in a publication entitled "Computer Architecture for Signal Processing" in the proceedings of the IEEE, vol. 63, pp. 624-632, published in April 1975. Although it may seem attractive to directly process PCM signals digitally without first converting the PCM samples to 800 1 0 26 2 into analog signals, such proposals have historically been cost related not competitive in telephony.

There are two types of telephony signaling that use a frequency combination, under the trade name DIGITONE or TCXJCHTONE loop signaling and R1 or R2 long-distance signaling.

The main distinction between the two is that the DIGITONE or TOUCHTONE form consists of two tones belonging to high and low frequency bands respectively. Thus, it is advantageous to use zero-crossing techniques for tone detection following filter separation of the received signal into two frequency bands. This approach does not apply to R1 or R2 signaling where a combination of any two from a number of prescribed tones is valid. US Pat. No. 4,076,965 demonstrates the complexity and scope of mixed digital and analog circuits required by a flexible analog MF signal receiver suitable for use with single frequency and multi-frequency signal forms.

Therefore, it is clear that the implementation of a pure digital MF receiver to receive and distinguish between a number of different PCM encoded tone signals requires a very flexible design, suggesting the use of a digital processor. However, in any practical design, the cost of provisioning such a receiver must be favorable compared to the cost of existing analog receivers in PCM systems. It has hitherto been found that recently proposed PCM signal receivers configured using digital microprocessor systems operate too slowly to economically match the real time requirements of telephone signals.

According to the invention, a significant improvement in the operational speed of a signal receiver is achieved by performing a simple but highly repetitive signal processing in a specialized digital circuit where a more complex but less repetitive 80 0 1 0 26> 4 3 processing is appropriately performed by a microprocessor. According to one embodiment of the invention, the real time required to receive signals is sufficiently reduced to allow the signal receiver to divide its time between a number of communication channels.

The signal receiver according to the invention includes means for receiving PCM signal samples from a TDM channel selected by a controller in an associated TDM switching center and a digital filter means for generating 10 binary signal representations of filter functions performed on the received signal samples each corresponding to a signal amplitude of a selected frequency in the received signal samples.

A converting means generates information signals indicating the signaling and compatible with the signal form of the controller 15 due to the signal amplitude values of the binary signal representations.

The digital filter performs filter functions over a number of specific predetermined frequencies and is equipped with a circuit containing wired logic to determine each filter function. The wired logic is advantageously provided in the form of a dead memory (ROM). The digital filter can operate at a faster rate than required to receive> sgn channel from a PCM sample and can therefore be advantageously shared across channels. The inherent speed of the filter is further enhanced by arranging the ROM to be used in a parallel / series construction so that more than two channels of PCM samples can be received in the available real time.

The converter essentially includes a microprocessor 30 which is operated according to logic instructions in combination with various timing and control signals generated in the signal receiver. The converter receives the output signals from the filter and converts these signals into information signals indicative of the signals and compatible with the signal form of the controller.

800 1 0 26 4

In one device, the speed of the signal receiver operation is further increased by providing alternative methods. At the start of signaling, the processor determines the validity of the initial signaling by performing a first set of processing functions with signals from the digital filter. Continuing signaling from the beginning, the processor performs a different set of functions that take less time than the first set of functions to only verify the continuity of the signaling.

The invention will be elucidated with reference to the drawing.

Fig. 1 is a block diagram of a digital signal receiver according to the invention in which the receiver is connected to a telephone switching center.

FIG. 2 is a block diagram of control sequence and timing chain used in the signal receiver of FIG. 1.

Fig. 3 is a block diagram of a digital filter and input buffer register used in the signal receiver 20 of FIG. 1.

Fig. 4 is a block diagram of a converter circuit used in the signal receiver of FIG. 1.

Fig. 5 is a timing chart indicating some selected operations of the signal receiver of FIGS. 1, 2, 3 and 4.

FIG. 6 is a flow chart of the functions of the signal converting circuit of FIG. 4.

The construction and operation of the embodiment will be briefly described with reference to Figure 1 followed by a more detailed description with respect to the remainder of the figures. Details pertaining to the power supply for operating the exemplary embodiment are not described or shown since the provisions of appropriate power supplies and power connections are well known to those of ordinary skill in electronic engineering.

Also, the routing of clock signals that is typically needed 800 1 0 26> * 5 to operate various types of circuitry "readily available" such as flip-flops, registers, etc. is not shown or described except for areas where such a description relates to special timing signals or otherwise illustrates the explanation of the exemplary embodiment.

In some areas of the exemplary embodiment, ROMs that are typically integrated circuits with interchangeable melt cartridges are described as a feature for various functions. This type of ROM is unique in that its integrated circuit construction is essentially that of a large number of individual wired logic networks, each of which can be selectively connected to a number of output terminals in response to a respective unique address signal. The exemplary embodiment may also be arranged by substituting alternate memory devices for one or more of the ROMs. Examples of some suitable alternative memory devices are the RAM, the PROM, and the EPROM. However, this and other alternative memory devices are more expensive, more volatile and therefore less reliable than the ROMs.

The digital switching center of Fig. 1 is in practice connected to different digital or analog trunk lines or some combination thereof. It can also be connected to various telephone subscriber loops. However, these are not indicated as they are not important for the description of a 25 PCM MP signal receiver in a digital telephone system. The digital switching center 1a operates in a format containing 32 10-bit bytes per frame, the frame repetition frequency being about kHz. A PCM mf receiver 1b is connected to the digital switching center 1a to receive signals from the trunk-30 lines through the center 1a. 32 PCM channels are connected to the digital switching center 1a through a series of PCM signal trunk line 2 to input buffer registers 30 in the receiver 1b. Clock signals corresponding to the bit rate of the PCM signals on the trunk line 2 are connected from the digital switching center 1a to a control sequence and timing circuit 10 in the receiver 1b via an 800 1 0 26 6 clock signal line 3. A write register bus 4 is connected from the digital switching center 1a to the input buffer registers 30 and with the control sequence and timing circuit 10. The write register bus 4 carries signals from a controller in the digital switching center 1a to cause selected channels from the 32 channels of PCM samples to be registered in selected input buffer registers 30. The control sequence 4. and timing circuit 10 generates read signals on a read register bus 27a which causes the PCM samples recorded in series in the buffer registers 30 to be selectively transferred in parallel to a digital filter 30a through lines 30b. After the contents of one of the buffer registers 30 are transferred to the digital filter 30a, a signal is generated on an appropriate line from a clean register bus 28a through the control sequence and the timing circuit 10 to cause the buffer register to be cleaned. The digital filter 30a provides output signals representing received signal power from each selected channel sample and also signals representing filter function components corresponding to 6 multi-frequency tone signal bands. These output signals occur in series / 20 parallel form on lines 43, 44a and 45a, and are indicated by signs, even and odd, respectively. These leads transport the output of the digital filter system to a signal converting circuit 50. Both the digital filtering system 30a and the signal converting circuit 50 are controlled and controlled by signals generated in the control sequence and timing circuit 10. Control and timing signals are conveyed via a control bus 20 and a time control bus 29, respectively. These buses are connected from the control sequence and timing circuit 10 to the digital filter 30a and the signal converting circuit 50. The signal converting circuit 50 periodically receives the output of the digital filter 30a and generates binary signal codes compatible with the operation of the controller. represent the switching center and the signal state of each of the four selected from the 32 channels.

Each binary signal code contains information in a form as indicated, for example, in Table A.

800 1 0 26, * t 7

TABLE A

Function Signal Status Error Status Number / error code_

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ^ Valid

signal 1 Y 0 Y x X X X

Pause 0 000 0000

Spectral

error 1 Y 1 Y 0 Z Z Z

10 ^ 61 error 1 Y1Y xxxx

In the table, xxxx indicates the 4-bit code vein a digit, ZZZ the 3-bit code of a spectral error and YY a 2-bit code of signal energy range.

The digital switching center 1a addresses the signal converting circuit 50 via a select bus 82 connected therebetween to indicate that signal information is needed and from which of the four channels it is required. The signal converting circuit 50 addresses the address on the selector bus 82 by sending a binary code, in accordance with the format in Table A, during the state of the selected channel, through an output information bus 83 to the digital switching center 1a.

In Figure 2, the control sequence and time control circuit includes a counter 11 with a clock input ck connected to the clock signal line 3 referred to in the description of Figure 1. The counter 11 also includes a load input LD and outputs 00 through Q8 and an output Q14. A signal which is synchronized with the frame rate of the digital switching center 1a is applied to the load input LD via a line 19a to synchronize the counter 11 upon power-up. The outputs Q0-Q8 contain the origin of the lines 0 to 8 in the control bus 20. The output Q14 is connected to an input D1 of a two-bit register 12. The counter 11 may be constructed of "readily" obtainable components consisting of a 10 dividing circuit 35 followed by 3 dividing circuits by 16. In such a device 80 0 1 0 26 8 only the load input LD of the 10 dividing circuit is actively connected to the line 19a so that when a load signal is indicated only the 10 dividing circuit is set to 0. The two-bit register 12 may consist of two D-type 5 flip-flop circuits connected as shown in Fig. 2. The outputs Q1 and Q2 of the register chain 12 are connected to an AND gate 13, the output of which origin of a reset line 13a. The register 12, in combination with the AND gate 13, generates a reset signal every 8 milliseconds on the reset line 13a in response to signals from the Q5 and Q14 outputs of the counter 11. In the control bus 20, lines 7 and 8 are connected to respective inputs A0 and A1 of decoders 27 and 28. Each decoder 27 and 28 includes outputs 20 through Q3. The outputs of the decoder 27 contain the origin of the lines 0 to 3 of the read register bus 27a and the outputs of the decoder 28 contain the origin of the lines 0 to 3 of the clean register bus 28a. The connection of these buses and the control bus 20 will become apparent with reference to FIG.

3 and 4.

The trigger pulse multivibrator circuits 91-94 each include an input connected to one of lines 0-3 in the write register bus 4, respectively. Each of the multivibrator chains 91-94 also includes an output connected to an input of a OR gate 95, an output of which is connected to a synchronization line 96.

The rest of the control sequence and timing circuits in FIG. 2 relate to the generation of timing signals on leads that fall within the general designation of timing signal lines 29 in FIG. 1. A ROM 14 includes address inputs 30 A0 through A6 connected to lines 0 to 6 respectively in control bus 20 and an address input A7 connected to the reset line 13a. The ROM 14 also contains information outputs DO through D7, the information output DO containing the origin of a line 9 in the control bus 20. An 8-bit register 15 contains the inputs DO 35 and D6 connected to the outputs D1 and D3 of the ROM 14. The inputs 30 0 1 0 26 9

D1, d2, d3 and D7 of the register 15 are connected to the outputs Q01, Q2 and Q6 respectively of the register 15. The output Q1 contains the origin of a load line 21 and the output Q6 contains the origin of a load register clock line 24. The outputs QO and Q1 of the register 15 are connected to inputs of a NOR gate 37, the output of which contains the origin of a stop line 27a. The output Q3 of the register 15 contains the origin of a clean accumulator register line 22. An output Q7 of the register 15 is connected to an input of an OR gate 17, of which 10 another input is connected to receive the clock signals from the line 3 The output of the OR gate 17 is connected to enable an AND input of the decoding circuit 28. An 8 bit register 16 contains inputs D1 and D2 connected to the outputs D5 and D6 of the ROM 14 respectively. The inputs D6 and D7 of the register 16 are connected to the synchronization line 96 and an output Q6 of the register 16, respectively. . An output Q1 of a register 15 contains the origin of a load register line 23.

The output Q2 of the register 16 is connected to an input D4 of the same register. The corresponding output Q4 is connected to an input D5. The output Q2 also contains the origin of an integration output register line 25 and an output Q5 of the register 16 contains the origin of a direct RAM access line 26. The output Q-6 is also connected to an input of an OR gate 19 and an output Q7 of the register 16 is also connected to an input of the OR gate 19 via a inverter 18. The output of the OR gate 19 is connected to the load input LD of the counter 11 via the line 19a.

The operation of the control sequence and timing circuit will now be described in connection with FIG. 2 and the timing chart of FIG. 5. All time scales and waveforms of FIG. 5 are shown in time.

At the top of Fig. 5, 64 frames of TDM channels are shown occupying a period of about 8 milliseconds. The time scale is plotted to show a reset waveform on line 35 13a coinciding with the 64 frame. A single frame 80 0 1 0 26 10 is shown to span a period of approximately 125 microseconds and contains 32 channels, 0-31. The time scale has been re-plotted to show channels of PCM bytes each 10 bit periods 0- Have 9. Each bit period is approximately 390 nanoseconds and corresponds to the period of the clock signals on the clock signal line 3. The remaining waveforms in Figure 2 are indicated with respect to the second expansion of the time scale and the PCM bit periods with the shortest time difference is half of a bit period. The waveforms are so marked that their appearance and location in the other 10 figures speak for themselves.

The counter 11 in Fig. 2 counts clock signals occurring on a line 3, the result of which is a binary number sequence occurring on lines 0 through 8 of the control bus 20. In one example, the clock signals on the line 3 a 15 pulse repetition frequency of 2.56 MHz. The counter 11 is synchronized with the PCM channel timing by a reset signal which occurs on line 19a causing the portion of the counter 11 dividing by 10 to be loaded with all zeros. The reset signal occurs due to a write signal occurring on a line 20 in the write register bus 4. The associated multivibrator circuit 91-94 responds to the write signal to cause the D6 input of the register 16 to be determined via the OR gate 95 and the synchronization line 96. Corresponding output Q6 is then also determined thereby ensuring that the reset signal appears on line 19a through the OR gate 19. When Q6 is determined, output Q7 is determined and the reset signal is terminated thereby. via the inverter 18 and the OR gate 19. Reset signals having a pulse width of about 125 microseconds and a cycle period of about 8 milliseconds-30 seconds occur on the reset line 13a. The reset signals on line 13a are due to the clock signals on line 3 divided by 10 x 2 * 1 and recorded in register 12, the outputs of which are AND-processed by AND gate 13. The HOM 14 is addressed by the counter 11 and contains a logic as needed to drive the registers 15 and 16 together with associated gates to generate the timing signals indicated in the timing chart of FIG. 5. .

In FIG. 3, the input buffer registers 30 of FIG. 1 are provided by 8 bit serial / parallel registers 31-34. each 5 register 31-34 contains three control inputs; a turn-on input EN connected to a respective line in the write register bus 4, a selection input SEL connected to a respective line in the read register bus 27a and a clean input CL connected to a respective line in the clean register bus 28a. Each 10 register 31-34 also includes a series input SI connected to the series PCM signal trunk line 2 and an 8 line parallel output PO connected to lines 0 through 7 of the parallel PCM output bus 30b.

In operation, write signals are received from the digital switching center 1a via the write register bus 4.

A write signal occurring on a line in the write register bus 4 causes associated input buffer register 31-34 to load a PCM sample in series from the trunk 2. Within the next 8 m.seconds, a read signal is generated by the decoder 27 and occurs on a corresponding line of the bus 27a which causes the contents of the input buffer register to occur via the parallel output PO on the bus 30b. Immediately thereafter, a clean signal occurs on the corresponding line of the clean register bus 28a ensuring that the register is cleaned to all zeros. In the event that no subsequent write signal has been directed to the input buffer register for some time, cleaning the register will cause the subsequent circuit to receive repeated false indications from PCM samples.

In the digital filter, an 8-bit buffer register 35 is connected between the parallel PCM bus 30b and a linear / quadratic dead memory 36. Eight information inputs D0 through D7 of the register 35 are connected to the parallel PCM bus 30b and a clock input CK is connected to the load register clock lead 24. Eight outputs 00 through Q7 of register 35 are connected to eight corresponding address inputs A0 through A7 of the BOM 36.

80 0 1 0 26 12

An address input A8 of the ROM 36 is connected to the line 4 of the control bus 20. The output of the ROM 36 is connected to parallel inputs of even and odd information shift registers 38 and 39 such that the even register 38 only receives output bits with 5 an even numbered meaning and the odd register 39 receives only output bits with odd numbered meaning. The load line 21 is connected to the load inputs LD of the shift registers 38 and 39. Each shift register 38 and 39 also includes a series output SO connected to a corresponding series input S1, and a hold input H connected to the stop line. 37a.

The ROM 36 is used to plot each sample of the PCM signal on its linear representation and to provide an approximation of the power of each sample. Thus, the ROM 36 contains linear representations and corresponding approximate linear quadratic representations of 256 8-bit PCM words used for transmission in the digital switching center. PCM Information from registers 31-34 is selectively applied through register 35 to address inputs A0 through A7 of ROM 36. During each application of a PCM word, the signal applied to address input A8 causes ROM 36 to be is addressed in its approximate linear quadratic memory portion and then in its linear memory portion. The even and odd bits of the approximate quadratic word and the linear word that occur at the output of the ROM 36 are each loaded into the parallel inputs 25 of the shift registers 38 and 39, respectively, under the control of the load signal on the load register line 23.

A filter ROM 40 contains address inputs A0 to A9 and information outputs D0 to D15 connected to an accumulator containing a 16 bit adder 41 and a 16 bit register 42. The 16 30 bit register 42 contains a clean input connected to the clean accumulator register line 22. The address inputs A0 and A1 of the ROM 40 are connected to the serial outputs SO of the even and odd shift registers 38 and 39 via the lines 38a and 39a, respectively. Eight bit even and odd shift registers 44 and 45 contain parallel inputs 35 to receive even bits 0-12 and also bit 15 and odd 800 1 0 26 13 bits 1-11 and bit 15, respectively, from the output of adder 41, Serial outputs SO of the even shift register 44 and the odd shift register 45 are connected to even and odd lines 44a and 45a, respectively, and to series inputs S1 of 312 bit even and 5 odd information shift registers 46 and 47, respectively. Each of the shift registers 44 and 45 includes a load input LD connected to the load line 21 and a series information input SI connected in common to an output AI of the last stage of the odd shift register 45. The output AI is also the origin of the 10. character line 43, serial outputs SO of the shift registers 46 and 47 are connected to the address inputs A2 and A3 of the ROM 40 and to the serial inputs S1 of the 320 bit series even and odd information shift registers 48 and 49, respectively. The shift register 48 contains a serial output SO connected to the address input A4 of the ROM 40 and the shift register 49 contains a serial output SO connected to the address input A5 of the ROM 40. The remaining address inputs A6-A9 of the ROM 40 are connected to lines 4, 5, 6 and 9 of control bus 20.

The filter ROM 40 contains information in memory locations accessible by binary addresses. The filter ROM 40 in combination with associated circuitry allows the digital filter system to addressably adopt the characteristics of six narrow band filters and an all-pass filter through which the approximately linear quadratic output of the ROM 36 is transmitted by the digital filter. Each narrowband passband filter corresponds to one of the six RM signal frequencies. The use of the all-pervious filter characteristic is easy as it provides a route through which the approximate linear quadratic output of the ROM 36 is input by the digital filter system. This output could be fed directly to the signal converting circuit in Figure 4 but with the greater cost of at least one additional buffer chain and approximate timing lines.

In operation, the approximate linear quadratic value and then the linear value of a PCM sample 35 are recorded in sequence in the odd and even registers 38 and 39.

800 1 0 26 14

Registers 38 and 39 serially shift the recorded bits through lines 38a and 39a to address inputs A0 and A1 of filter ROM 40. The information is also re-circulated through registers 38 and 39 through respective series inputs S1. Thus, with each occurrence of an address on the control bus 20, the information bits of the ROM 36 are serially presented to the filter ROM 40 in pairs, running from the least significant bits to the most significant bits. Since the least significant bit of the address on the control bus occurs at 1/10 the speed of the 10 system clock signals on line 3, the recirculation function of shift registers 38 and 39 is stopped for two of every ten clock signals by a stop signal on the stop line 37a. Each linear value is presented by the registers 38 and 39 to the ROM 40, seven times as described above, each time in the presence of a different out of seven filter function addresses of the control bus 20. Each time an approximate square value in the When registers 38 and 39 are loaded, it is presented once in the presence of the all-permeable filter function address.

The filter ROM 40 generates reading signals at the outputs D0-D15 with every occurrence of the clock signal. The reading signals are collected over a period of 8 cycles of the clock signal by the adder 41 and the register 42. Since the space in the collector is limited, the connection between the output of the register 42 and the input of the adder 41 is arranged to shift the recorded information two places in the direction of lesser significance with each addition, thus dropping the two least significant bits. The address on the control bus 20 contains a signal on the ninth line which is determined when the eighth or last sample occurs at the inputs A0-A5 of the filter ROM 40. This causes a "complement of two" reading to the outputs D0-D15 of the filter ROM 40, which causes a subtract in the accumulator. At the end of each accumulation, shift registers 35, 44 and 45 are loaded with the accumulated result, which has the two 800 1 0 26 * * 15 complement binary signal form. The wired information in the filter ROM 40 and the circuit, if so constructed, provides an output which is a 1/4 representation of filtered amplitude or power value, as appropriate. Since the information has the complement two binary form, it is multiplied by 4 to generate the desired filter function value by loading the accumulated sign bit 15 of the accumulated value into the first stage of each shift register 44 and 45. The drawing bit 15 is also loaded to the last stage of the shift register 45, ignoring the bits 10, 13 and 14 of the adder 41. The accumulator register 42 is then set to all zeros by a signal on the clean accumulator register line 22. Simultaneously with the sample exit from the shift registers 38 and 39, information bits from the registers 44 and 45 are accepted at the serial inputs S1. 15 of the shift registers 46 and 47, respectively. Meanwhile, the sign bit 15 is continuously charged at the series inputs S1 of registers 44 and 45 via the sign line 43.

The 312 bit shift registers 46 and 47 are continuously operated at the system clock rate to record the information bits on the lines 44a and 45a. In ten clock periods, the first eight bits recorded are information and the last two bits registered are irrelevant. It should also be noted that the control bus carries 10 addresses per sample. Thus, the combined length of shift registers 44 and 46, and 45 and 25 and 47 is such that the result of the previously filtered sample of a given channel is synchronized with the present sample of the given channel. of the 320 bit shift registers 48 and 49, synchronously, the previous preceding filtered sample of the given channel. Addressing the filter ROM 40, in combination with the information content of the filter ROM 40, provides the desired filtering effect for 6 frequencies and for energy. Since the eighth address on the control bus is not effectively used in this embodiment, the wired information in the filter ROM 40 corresponding to this filter function is arranged to be wholly zeros.

80 0 1 0 26 16

In Fig. 4, the binary signals on the even line 44a and the sign line 43 are received bit by bit by the signal converting circuit through an exclusive OR gate 52. Similarly, the binary signals on the odd line 45a and also on the 5 line are Receive 45 bit by bit via another exclusive OR gate 53. The output of the exclusive OR gates 52 and 53 are connected to the inputs A1 and A2 of a two bit adder 51. The reset line 13a is connected via a reverser 57 to inputs of AND gates 54 and 55 and with the clean input CL of 10 a flip-flop 56. An output of the fljp-flop 56 is connected to a carrier input C of the adder 51. The outputs of the AND gates 54 and 55 are connected to inputs B1 and B2 of the adder 51. The adder 51 includes outputs S1 and S2 connected to series inputs S1 of two 320 bit even and odd shift registers 60 and 61, respectively. The serial outputs S0 of the shift registers 60 and 61 are connected to the serial inputs S1 of two 4 bit shift registers 64 and 65 respectively and to inputs of the AND gates 54 and 55 respectively. Parallel outputs of the shift registers 64 and 65 are connected to inputs of an 8 bit buffer 20 register 66, the outputs of which are connected to an information bus 81. The shift register 66 also includes a clock input CK connected to the integrator output register line 25 and an enable input EN connected. with the reset line 13a.

A processor 70, a ROM 71 and a RAM 72 are connected to each other via an information bus 81 and an address bus 80.

From the processor 70, an input connected to the reset line 13a is a write RAM output connected to an input of an OR gate 77. Output of the OR gate is connected to a write enable input of the RAM 72. A group of addressable output registers 30 meters 85 is connected between the information bus 81 and the output information bus 83. A decoder 73 has inputs connected to the five main lines in the address bus 80, an output connected via a ROM selection line 74 to the ROM 71, an output connected connected via a RAM selection line 75 to the RAM 72 and an output to a write enable input W1 of the registers 80 0 1 0 26 17 85. The write address inputs W1 and W2 of the registers 85 are connected to two lines of the address bus 80 The registers 85 also include read address inputs R1 and R2 and a read enable input RE all connected to the select bus 82. A direct memory access address register 67 is connected between the best control bus 20 and address bus 80. Register 67 includes a clock input CK connected to line 25 and a turn-on input EN connected to a reset acknowledgment output 70a of processor 70.

In operation, the output of the digital filter 30a is supplied to the signal converting circuit 50 through the even line 44a and the odd line 45a, with two information bits continuously present at one time with the sign bit on the sign line 43 for 10 clock periods. The even and odd information bits are made OR exclusively with the sign bit through the respective ports 52 and 53 and then applied to the inputs M and A2 of the adder 51. The adder 51, ports 54 and 55, the flip-flop 56 and registers 60 and 61 in combination perform a separate and distinct integration of the absolute value of each filter function output for each of the TDM channels received over a time period of 8 milliseconds. The output signals of adder 51 are delayed at inputs B1 and B2 by the 320 bit even and odd shift registers 60 and 61. A carrier signal at the overcurrent output 53 of adder 51 is delayed for one clock period by the flip-flop 56 and then applied to the slow input C of the adder 51. By these measures, the corresponding filter function outputs for corresponding channel samples are synchronized and accumulated over an 8 millisecond period as determined by the reset signal on line 13a. The reset signal is determined during one period of the frame rate, about 125 microseconds. Determining the reset signal blocks AND gates 54 and 55 and clears flip-flop 56 to initiate a new accumulation period. During the reset signal, the information resulting from the previous integrations is also shifted from the shift registers 60 and 61 through the 80 0 1 0 26 18 shift registers 64 and 65 and is registered in parallel in the register 66. The processor 70 is turned off by reset signal during the duration of the 125-second period so that under the control of a clock signal on line 25, the information received by the register 66 is compiled in parallel bytes and applied to the information bus 81. At the same time, the register 67 carries the signals on the control bus to the address bus 80. Thus, from the signal on the KAM line 26, the RAM 72 is caused to record all integration accumulated in the just completed information period at address locations determined by the signals on the control bus and in an address area as determined by the permanent signal input connections 67a on the buffer register 67. Aa At the end of the 125 microseconds determination period of the reset signal, all signal information is loaded into RAM 72. The processor 70 resumes operation with the associated circuitry to convert the signals into codes compatible with the digital switching center as indicated, for example, in Table A.

To facilitate this function, the processor 70 is directed into operation to perform the functions of the flow chart in Fig. 6 with an appropriate sequence of instruction codes stored in the form of an address accessible logic in the ROM 71 It is not the intention to discuss the detailed operation of a processor as it is known to those skilled in the art of electronic processor applications to specify an appropriate sequence of instruction codes suitable for the arrangement of the functions indicated in the flow chart of Fig. 6 and Table A. It should be considered that any given processor is limited by its range of functions and the speed at which it is able to operate. Of course, each selected processor in combination with a specific set of instruction codes must be fast enough to process the results of each filter function within the period between determinations of the reset signal. In the exemplary embodiment, a well-known microprocessor, type 8085, operated with a period time of 1.3 800 1 0 26 19 microseconds and this was satisfactory when logical instructions for applying the functions of the flow chart in Fig. 6 were used. .

In converting the signals, the actual time available for processing can be increased by subjecting MP signals to a rigorous validity test only at the beginning while running MP signals are subjected to a continuity check that requires less real time for editing the validity test. This method is particularly useful in a signal receiver which is adapted to receive loop signals since the manual keying of signals often extends over a time greater than that which is essential.

Thus, the outputs of a number of digital filters adapted to the loop signal shape can be converted by a single processor. These two methods are indicated in the flow chart of Figure 6 in which two alternative routes are available to process the instantaneous results of an 8 millisecond period each. The functions required to determine the validity of the initial 20 MP signals of a digit are indicated on the left side of the power card. On the right side of the flow chart, the functions are indicated for determining the continuous MP signaling of a number.

At the beginning of an 8 millisecond period, the operation of the signal conversion chain begins. The three largest filter-25 function amplitudes collected in the RAM 72 are first identified. When two of the three identified signals are above a predetermined amplitude and there was signaling in the previous two 8 milliseconds period, the signal being digit is decoded. If it is the same as the corresponding channel-30 digit decoded in the previous 8 milliseconds period, it is loaded into an appropriate output register 85. However, if the digit is a third occurrence of a digit that is different, the decoded digit is indicated as an error.

Again at the beginning of an 8 milliseconds 35 period, when there are no two amplitudes in the RAM 72 that are 800 1 0 26 20 above a predetermined threshold and this was the case in the previous 8 milliseconds period, a pause indication is loaded in the appropriate output registers 85.

In the case where there are two amplitudes above the 5 threshold but there was a prior pause, the amplitudes are subjected to the validity test which includes a series of checks to see if they meet the requirements for MF signaling. The amplitudes are compared for unbalance, typically referred to as twist of greater than about 7 db. When more than 7 db twist 10 is present, the signal is determined as not valid. In the case of an acceptable twist, the smallest of the three amplitudes is compared to the middle amplitude for a twist greater than about 12 db. If less than a 12 db twist is present, the signaling is considered invalid. When this unbalance is acceptably large, the largest amplitude is compared to the approximate energy value of the sample period to determine whether the largest MF signaling component is at least about 20 db above other signals and is considered to be noise occurring in the sample period. When two amplitudes 20 representing a valid signaling are found from the above functions, the digit they represent is decoded. When the previous 8 milliseconds period was paused, the decoded digit is loaded into the appropriate output register 85.

In one embodiment, the filter ROM 40 in the digital filter 30a contains addressable logic as indicated in the following tables. The addressable logic provides six narrow band filter functions and an all-permeable filter function. The six narrow band filter functions each have a pass band corresponding to one of six tones with frequencies of 700 Hz, 900 Hz, 1100 30 Hz, 1300 Hz, 1500 Hz and 1700 Hz respectively. These are the standard tone frequencies of the North American MF signal form. The designation in the tables refers to the ROM 40 supplied by four ROM devices (0-3) each contributing to four of the sixteen output ports of the ROM 40 and the respective 35 address ports of which are jointly connected.

80 0 1 0 26 21

Each of the tables is in hexadecimal notation with the minor bits of the addresses extending across the top of the table and the major bits of the addresses extending along the left side of the table 5 while the addressable logic is the body of the table contains, e

Addressable logic table for ROM 40-0

ADDR 00 01 02 03 04 05 06 07 08 09 0A OB OC OD OE OF

000: 0123012301230123 010: 0123012301230123 10020: 0123012301230123 030: 0123012301230123 040: 0000111133334555 050: FFFF00002 2 224444 060: EEEEFFFF111 13333 15070: DDDDEEEE00002222 080: 0000111122334444 090: FFFF000022223333 OAO: EEEEFFFF1 1 1 12222 0B0: DDDDEEEE000011 11 20 0C0: 0000111122223333 ODO : FFFF00001 1 1 12222 0E0: EEEEFFFF000011 12 OFO: DDDDEEEEFFFF001 1 100: 0000111122223333 25 110: FFFF00001 1 1 12222 120: E EEEFFFF000011 1 1

130: DDDDEEEEFFFFOOOO

140: 0000000011112222 150: FFFFFFFFOOOO 1 1 1 1 30 160: EEEEEEEFFF. FF0000

170: DDDDDDEEEEEEFFFF

180: 00000000001111J1 190: FFPFFFFFF0000000

1A0: EEEEEEEEFFFFFFFF

35 lBO: DDDDDDDDEEEEEEEE

80 0 1 0 26 22

ICO: OOOOOOOOOOOOOOOO

IDO: OOOOOOOOOOOOOOOO

1E0: OOOOOOOOOOOOOOOO

IPO: OOOOOOOOOOOOOOOO

5 200: 01EF01EF01EF01EF

210: O 1EF0 1EF0 1EF0 1EF

220: 01EF01EF01EF01EF

230: 01EF01EF01EF01EF

240: OOFFl 1 1 1CCCCEEEE

10 250: FFEFOOOOBBBBDDDD

260 11113333EEEE0000

270: 00002222DDDDFFFF

280 OOFF 1 1 1 1DDCDEEEE

290: FFEFOOOOCCCCDDDD

15 2A0: 11 1 13333EEEE0000

2B0: 00002222DEDDFFFF

2C0: OOFFl 1 1 1DDDDEEEE

2D0: FFEFOOOOCCCCDDDD

2E0: 111 13333FFFFOOOO

20 2F0: 00002222EE EEFFFF

300: OFF 100DEDDEFEE

310: FFEFOOFODDCCEEDD

320: 111 12222FFFF0000

330: 0000121 1EEEEFFFF

25 340: OOFFOOOOEEEEFFFF

350: FFEFFFFFDDDDEEEE

360: 1111222200001111 370: 0000 1 1 1 1FFFF0000

380: OOFFOOOOFFEFFFFF 30 390: FFEEFFFFEEEEEEEE

3A0: 1111222201001111 3B0: 0100111100FF0000

3C0: OOOOOOOOOOOOOOOO

3D0: OOOOOOOOOOOOOOOO

35 3E0: OOOOOOOOOOOOOOOO

3F0: OOOOOOOOOOOOOOOO

80 0 1 0 26 23

Addressable logic table for ROM 40—1

ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D OE OF

000: 0000000000000000 010: 0000000000000000 5 020: 000000000000000000 030: 00000000000 0 0000 040: 0001ABBB5566F001 050: 01 11BBCC566701 1 1 060: 1122CCCD67771122 10 070: 2233CDDE77888823 080: 00118998900

0A0: 122399AB1 122899A

OBO: 2 3 3 4AABB 1 2 3 39AAB

15 0C0: 00124456899ACDDE

0D0: 0123556799ABDEEF

0E0: 12335678AABCEEF0 0P0: 23446788BBCDFF01 100: 0012011201220123 20 110: 01231123122 31233 120: 1234223423342344 130: 2345234534453455 140: 0012BCDE789A3456 150; 0123CDEF89AB4567 25 160: 1234DEF09ABC5678 170; 2345EF01ABCD6789 180: 0123789AE F015678 190: 012389ABF0126789

1A0: 12349ABC0123789A

30 1B0: 2345ABCD123489AB

ICO: 0000000000000000 1D0: 0000000000000000 1E0: 0000000000000000 1F0: 0000000000000000 35200: 0000000000000000 800 1 0 26 24 210: 0000000000000000 220: 0000000000000000 230: 0000000000000000 240: 00FFAB9AAB9A5 544 5250: 01F0BBAABBAB6655 260: EEDE998899883433 270: FFEE9A99AA994534 280: 0OEF786701F08877 290: 01F0897712019988 10 2A0: EEDD5645EFDE6756 2B0: FFEE6756F0EF7866

2C0: 00EF44237866BCAB

2D0: 01F055348977CDBC

2Ê0: EECD23 015645AA89

2F0: FFDE33126756AB9A

300: 00EF01EFF0DEF0EE

310: Ο 1 F Ο 1 1F001EF01FF

320: EECDEFCDDECCDECD

330: FFDEFODEEFDDEFDE

20340: 00EFBCAA89674523 350: 01F0CDBB9A785534 360: EFCD9A8967452 301370: FFDEAB9A785634 12380: 01EF785612F08967 25390: 01EF896723019A78 3A0: EFCD5634F0DE6745 3B0: F0DE674501EF7856 3C0: 3D0 0000000000000000: 0000000000000000 30 3E0: 3F0 0000000000000000: 0000000000000000 0 1 0 35 80 26 25

Addressable logic table for ROM 40-2.

ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B OC OD OE OF

000: 0000000000000000 010: 0000000000000000 5 020: 0000000000000000 030: 0000000000000000 040: 06C3906D3906D3A0

050: C29F6C29F6C3906C

060: 8F5C28F5C29F5C29 10 070: 4B18E5B28E5B28F5

080: 092BA3C54D6FF81A

090: D 6 F 8 8 1A32B4DD6F8 0A0: B 4 D 6 6 F 8 1092BB4D6 0B0: 92B44D6FE70981A3 15 0C0: 0B612D8450B672D9 0D0: E9401C723E9561C7 0E0 iD83EFA512D94: 34DFA661DFA61

110: EB852FB852FC962F

120: DA741DA741EB841E

130: C952FC9630C9630D

140: OECBDCA9BA8 79865 150: FDCADBA8B9768754 25 160: ECB9CA97A8758653 170: DBA8B98697647542

180: 000033337777BBBB

190: f F F F 3 3 337777AAAA

1A0: FFFF33 336667AAAA 30 1B0: FFFF23336666AAAA

ICO: 0000000000000000 1D0: 0000000000000000 lEO: 0000000000000000 1F0: 0000000000000000 35 200: 0000000000000000 80 0 1 0 26 26 210: 0000000000000000 220: 0000000000000000 230: 0000000000000000

240: 063990C3C3P66C9F

250: C2F56C9F8FB2295C

260: 7DA0174A3A7DD407 270: 3A6DD306063990D3

280: 09E7A38 1B4925E3C

290: D6B4816F92703C1A

2A0: 4D2BE7C5F8D69270

2B0: 2B09C5A3D6B4 7 05E

2C0: 0B942DC7B64FD872 2D0: E '9 8 3 1CA5943EC750 2E0: 3EC750FAE9720BA5 15 2F0: 1CB64FD8C761FA83

300: 0C63309695FCC92F

310: EB512F8574EAB81E

320: 2F8562C9B8 1EFB52 330: 1E7441B7A70DDA40 20 340: 0E31DC0F42752053 350: FD20DB0E31641F42 360: 1043FE2154873265 370: 0F32ED1053862 154

380: 000033338888CCCC

390: FFFF33338888CCCC

3A0: 000044449999CCCC

3B0: 000033338888CCCC

3C0: 0000000000000000 3D0: 0000000000000000 30 3E0: 0000000000000000 3F0: 0000000000000000 35 80 0 1 0 26 27

Addressable logic table for ROM 40-3.

ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D OE OF

000: 0000000000000000 010: 0000000000000000 5 020: 0000 000000000000 030: 0000000000000000 040: 07E5C3A18F6D4B29

050: 5D4B18F6D4B2907E

060: A2906E5C2907E5C3 10 070: F7E5B3A17E5C3A18 080: 00007777EEEE5555 090: EFFF5555CCCC3333 0A0: CDDD3444AAAAl 1 1 1 0B0: 0BBl2228888FFFF 15 0C0: 02588AD002588

110: CA7541ECC9644 1EC

120: 86310EB985200DA8 130: 42FDCA7542FDC964 140: 07F7F6E6E5D5D4C4 150: 2A2A191907F7F6E6 25 160: 4C4C3B3B2A2A1808

170: 6E6E5D5D4C4C3B3B

180: 0001BBBC66671112

190: CDDE7889222 3DDDE

1A0: 899A3445EFF09AAB

30 1B0: 4556F001ABBC5667 ICO: 000000000000000000 1D0: 0000000000000000 1E0: 0000000000000000 1F0: 0000000000000000 35 200: 000000000000 0 000 80 0 1 O Ζΰ 28 210: 0000000000000000 220: 0000000000000000 230: 0000000000

240: 0729C3D480A14C6D

5 250: 5D7E1829D5F691B2 260: 6D7E293AE607A1B2 270: B2C37E8F3B5CF7 18 280: 0000776623229A99 290: EFEE554401007877

2A0: 4433BBAA6766DDCC

2B0: 2 2 1 1 99884 5 44 BCBB

2C0: 02BE8A2503BE8B36

2D0: 8B3602AD8B3603BE

2E0: 02AD8A2503BE8A25

2F0: 8A2502AD8B3603BE

300: 0D6385DA0E6386EB

310: CA2F4 1A6CA2F42A7 320: 85DA0D5286EB0D52

330: 4 196C91E42A7 CA2F

340: 0719F6F72A3B192A

350: 2A3B192A4C5D3B4C

360: C3C4B2B3E5E6D4D5 370: E5E6D4D50819F6F7 380: 0000BBAAABAA5655 25 390: CDCC787767661211

3A0: 887733222211DDCC

3B0: 4433FFEEEEEE9988 3C0: 0000000000000000 3D0: 0000000000000000 30 3E0: 0000000000000000 3F0: 0000000000000000

In a different embodiment of the tone signal receiver designed to receive PCM loop signal tones, it is necessary that the addressable logic in the ROM 40 provide seven filter functions for frequencies different from the above given frequencies with the addressable logic different.

80 0 1 0 26

Claims (13)

1. Signal receiver for receiving pulse code modulated (PCM) tone signals, characterized in that it comprises a receiving circuit (30) for receiving PCM signals from a selected signal, a circuit (10) for generating sets control signals, each control signal of the set corresponding to a predetermined filter function in the signal receiver, a digital filter circuit (30a) containing a converter (36) for converting each of the received PCM signals into a corresponding linear binary signal with a plurality of bits, the digital filter circuit addressing the control signals and the linear binary signals for performing a number of band-pass functions with the linear binary signals as directed by the control signals and generating filter signals corresponding to the signal amplitudes of the linear binary signals with frequencies corresponding to those frequencies determined by the respective bandpass filter functions, a translation circuit (50) that addresses the control signals and the filter signals for detecting the presence of PCM tone signals 20 and translates the signals into information signals having a predetermined signal code form. The signal receiver of claim 1, wherein the translation chain is characterized by a circuit (51-65) for integrating the filter signals over a predetermined time period to derive an integrated binary signal corresponding to an amplitude value for a sequence from each of the filter functions, a temporary memory device (72) for temporarily collecting the integrated binary signals, a memory device (71) with stored logic instructions at address-accessible locations, a processor (70) connected to the temporarily stored integrated binary signals and the stored logic instructions, wherein the processor can operate according to the stored logic instructions for identifying the largest two of the temporarily stored integrated binary signals and comparing the identified signals, the one with the other, 800 1 0 26 to determine the amount of twist between them. 3. Signal receiver according to claim 2, characterized in that the converter also operates to convert the received PCM signals into an energy signal 1 corresponding to an approximate square value of the corresponding linear binary signal and in which the processor can operate according to the stored logic instructions for comparing the power signal with any of the identified signals to determine a signal to noise ratio by an amount acceptable for 10 valid (MP) multi-frequency signaling. 4. Signal receiver according to claim 1, characterized in that the converter also works to convert the received PCM signals into power binary signals, each corresponding to an approximate square value of a corresponding linear binary signal and wherein the translation chain is a chain ( 51-65) for individually integrating the filter signals corresponding to each filter function and to the power signals over a predetermined period of time, to derive an integrated binary signal corresponding to a sequence of each of the filter-20 functions and the binary power signals, a temporary memory device (72) for temporarily storing the integrated binary signals, a memory device (71) with stored logic instructions in address accessible places, a processor (70) connected to the temporarily stored signals and read the stored logical instructions, whereby the processor can operate according to o Saved logic instructions for identifying the largest three of the stored integrated signals, comparing the largest two of the identified signals for a twist amount acceptably small for valid signaling, comparing the second largest identified signal with the smaller an identified signal having a difference amount that is acceptably large for a valid signaling and wherein one of the largest identified signals is compared to the binary power signals for a signal-to-noise ratio that is acceptably large for a valid signaling. 80 0 1 0 26 Signal receiver according to claim 1, characterized in that the digital filter circuit comprises a memory device (40) with bytes of information bits stored in address-accessible locations therein, address ports (A) and information ports (D), wherein a number of the address ports is connected to receive a portion of each of the control signals, the memory device for representing the selected bytes in the information ports due to the signal states of the address ports, an accumulator circuit (41, 42) connected to the information ports accumulating the information bytes over a predetermined time interval to generate one of the amplitude signals, an input circuit (38, 39, 46, 47, 48, 49) connected to receive the bits of linear binary signals from the converter and to receive the amplitude signals, input means for synchronously supplying the address ports with the instantaneous linear binary signal, with the other corresponding previous amplitude signal and with the corresponding preceding previous amplitude signal, each of the signals thus being supplied in a series / parallel bit form. 6. Signal receiver according to claim 1, characterized in that the digital filter circuit comprises a memory device (40) with bytes of information bits stored in address-accessible places, Information ports (D) and a number of first (A0, A1) , second (A2, A3), third (A4, A5) and control (A6-A9) address ports, the control address ports being connected to receive the control signals and the information bits arranged to facilitate the filter functions as selected by the control signals, the memory for presenting selected bytes of information bits at the information ports due to the signal states of the address ports, first input circuits (38, 39) connected between the converter device and the first address types to sequentially order the bits of each linear binary signal to be arranged in parallel groupings of at least two at the first address ports with each occurrence of one of the control signals, an accumulator (41, 42) connected to the information ports 35 for accumulating the bytes during the duration of each individual 80 0 1 0 26 control signal to generate a corresponding amplitude signal, output circuits (44, 45) connected between the accumulator circuit and the translation circuit to sequentially output bits of each amplitude signal in the parallel groupings, second input-5 circuits (46, 47) connected between the output chains and the second address ports to delay the arrival of the parallel groupings of each amplitude signal in the second address ports over a predetermined period of time to synchronize each amplitude signal with an adjacent corresponding linear binary signal and the occurrence of the corresponding filter function, third input circuits (48, 49) connected to the third address ports for delaying the arrival of the parallel groupings of each amplitude signal at the third ad responds over a predetermined amount of time to synchronize each amplitude signal with an adjacent adjacent linear binary signal and the occurrence of the corresponding filter function, the amplitude signals being generated in sequence. Signal receiver according to claim 1, characterized in that the translation chain comprises a processor (70) and a device (71) for causing the processor to determine the validity of the preliminary PCM MP signals by outputting a sequence process functions that require a first finite time period and to cause the processor to determine the continuity of continuing PCM MP signals through another set of process functions that require a smaller time period than the first time period. 8. Multi-frequency signal receiver for receiving a translating PCM MP signal in a signal code form compatible with a controller in a tdm switching center, characterized in that the signal receiver comprises a control sequence and a timing circuit (10). , connected to be synchronized with the TDM switching center, for generating a set of control signals on a repeating basis, a time division filter circuit (30a) that responds to the control signals, for performing a number of predetermined passband filter functions 35 with a series of PCM signals received from the TDM switch 800 1 0 26 control panel and to generate therefrom a corresponding series of amplitude signals with respect to each of the filter functions, a signal translation circuit (50) which is responsive to the control signals and the amplitude signals for determining the presence of a valid alert, whereby this valid alert is translated ld is used in information signals having a predetermined signal code form. 9. A method of translating PCM MP signaling into a signal code form compatible with a controller in a TDM switching center, wherein (a) PCM receiving signals are selected by the TDM switching center, (b) each of the received PCM signals are converted into a corresponding multi-bit linear binary signal, characterized in that (c) at least one set of control signals is generated with each frame occurrence in the PCM signal format; (d) a number of bandpass filter-15 functions are performed with the linear binary signals as directed by the control signals and generating amplitude signals consisting of signal bits and corresponding to the signal amplitude of the linear binary signals with frequencies corresponding to those frequencies determined by the respective passband filter function; (e) detecting the presence of multifrequency signals from the amplitude signals and translating the multifrequency signaling according to the control signals into information signals in the signal form. The method of claim 9, wherein the step 25 (d) is performed in a digital filter containing a memory (40) with bytes of information bits collected at address-accessible locations, characterized in that the step (d) further characterized in that (f) causes the memory to read the bytes as selected by address signals applied thereto, the address signals consisting of signal bits and containing a portion of each of the control signals, (g) the bytes accumulated from the memory over a predetermined period of time to generate one of the amplitude signals, (h) a slice of each one of the address signals is generated from a moment Λ of the 35 linear binary signals, the corresponding previous amplitude 800 1 0 26 signal and the corresponding previous preceding amplitude signal, (i) applying this part in series / parallel form in groups of at least six bits each to the g memory for the predetermined time period. Method according to claim 9, characterized in that the step (e) consists of the steps of determining whether the signaling is preliminary or continuous and in the first case a series of process functions are performed to determine the validity of the signaling and wherein in the second case, a different set of process functions are performed to determine the continuity of the signals present with respect to the immediately preceding signals. 12, Device substantially as described in the description and / or shown in the drawing. 13. Method substantially as described in the description and / or shown in the drawing. 20 800 1 0 26 —μ— B. V. - \ \: -3S— 13JÜN19S0 _______________I Improvement of errata in the description pertaining to patent application No. 80-01026 Ned. proposed by Applicant dd. J g jyjjj jggg On page 9 line 17, "15" should be changed to "16". On page 10 line 16, "2" should be changed to "5". On page 17 line 23, "53" should be changed to "S3". In FIG. 1, the numeral 27a is applied to the read register bus running from block 10 to block 30 adjacent to read register bus 28a. In Fig. 2, the input of the counter 11 connected to a line 19a must be indicated by LD. In Fig. 4, in block 66EK, replace with CK. Furthermore, the output register connected to the selection bus 82 must be provided with the reference number 85. The line connected between the input EN of the block 67 and the block 70 must be provided with the reference number 70a. In Fig. 6 the different blocks are provided with a functional description. jjf / RR 800 1 0 26