SE452388B - SIGNAL RECEIVER AND SET FOR RECEIPT OF SCULD CODE MODULATED, PCM, TONE SIGNALS - Google Patents

Description

-I> (f: CN OO In telephone technology there are two types of signaling that use frequency combination: DIGIIONE-x or 'IUCHIWE-x loop signaling (x mark) and R1 or RZ trunk signaling. The main difference between the two is that DIGITONE or TOUCHTONE format consists of two tones belonging to high and low frequency bands, respectively, and it is therefore advantageous to use 0-pass technology for tone detection after filter separation of the received signal in two frequency bands. or R2 signaling, whereby a combination of two of a plurality of prescribed tones is valid The U.S. Patent 4,076,965 illustrates the complexity and size of mixed digital and analog circuits required in a flexible analog multifrequency signaling receiver suitable for use. for single-frequency and multi-frequency signaling formats.

It is thus clear that the realization of a completely digital multifrequency receiver for reception and distinction between a number of different PCM tone signals requires a very flexible construction, suitably using a digital bar.

In practice, however, the cost of providing such a receiver must be advantageous in comparing the cost of existing analogue notchs in PCM systems. Recently proposed PCM signaling receivers to achieve through the use of digital microprocessor systems have so far been found to work too slowly to be electrically adapted to the real-time requirements set for telephone signaling.

With the application of the present invention, a significant improvement of the refractive speed of a signaling receiver is obtained by performing simple but highly repetitive signal processing in specialized digital circuits, hereinafter complex but less repetitive processing is suitably repeated by a zero processor. In one embodiment of the invention, the real time required for signal reception is reduced sufficiently to allow the signal receiver to time be divided between a plurality of grain imaging carcasses.

The particular characteristics of a receiver and a method according to the invention appear from the claims.

The signaling receiver according to the present invention comprises means for receiving PCM signal samples from a 452 388 TDM channel selected by a control device in an associated TDM switch equipment and a digital filter means for generating binary signal representations of the filter functions performed with respect to the received signal samples, which each corresponds to a signal amplitude of a selected frequency of the received signal samples. A translator generates data signals indicating the signaling and compatible with the signal format of the controller depending on the signal amplitude values of the binary signal representations.

The digital filter means perform filter functions for a plurality of specific, predetermined frequencies and are provided by means of circuits which comprise fixed logic for defining each filter function. The fixed logic is suitably executed in the form of a read-only memory, RON. The digital filter can operate at a higher speed than that required for receiving a channel with PCM samples and can thus advantageously be divided between several channels. The built-in speed of the filter is further improved by arranging said ROM for use in parallel / series configuration, so that in the available real time more than two channels with PCM samples can be received. The translator device essentially comprises a microprocessor, which is operated in accordance with logical instructions in combination with various time and control signals generated in the signal receiver. Said translator means receives the output signals from the filter and translates these signals into data signals indicative of the signaling and compatible with the signal format of the control device. in one embodiment, the speed of the function of the signal receiver is further improved by the provision of alternative mode of operation. At the beginning of the signaling, the processor determines the validity of the initial signaling by performing a first series of processing functions regarding signals from the digital filter means. Regarding the continuation of the signaling, the processor performs another series of functions, which is less time consuming than the first series of functions, in order to substantially verify the continuity of the signaling.

An exemplary embodiment of the invention will be described in more detail below with reference to the drawings.

Fig. 1 is a block diagram of a digital signaling receiver in accordance with the invention, which receiver is connected to a telephone switching equipment.

Fig. 2 is a block diagram of a sequence and timing circuit used in the signaling receiver of Fig. 1.

Fig. 3 is a block diagram of a digital filter and an input buffer register used in the signaling receiver of Fig. 1.

Fig. 4 is a block diagram of a translation circuit used in the signaling receiver of Fig. 1.

Fig. 5 is a timing diagram illustrating some selected functions of the signaling receiver of Figs. 1, 2, 3 and 4.

Fig. 6 is a flow chart of the functions of the signaling translation circuit of Fig. 4, The structure and operation of the exemplary embodiment will be briefly described with reference to Fig. 1, followed by a more detailed description with reference to the remaining drawings. Details regarding the supply for operation of the device are described and not shown, as the arrangement of suitable power supplies and power connections is well within the knowledge area of a person skilled in the art in this area. Furthermore, the distribution of clock signals which is usually required for operation of different types of storage circuits, such as flip-flops, registers, etc., is not shown or described, except in cases where such a description relates to special time signals or otherwise facilitates explanation and understanding. then of the exemplary embodiment.

In some parts of the illustrated embodiment, it is stated that read-only memories, ROMs, usually integrated circuits with combustible current bridges, are used to provide various functions.

This type of ROM is unique in that its integrated circuit structure is substantially the same as for a large number of individual logic circuits, each of which is selectively connectable to a plurality of terminals in response to an associated unique address signal. The exemplary embodiment can also be achieved by the use of alternative memory devices instead of one or more of said ROMs. Examples of some suitable alternative memory devices are: direct access memory, RAM, reprogrammable read only memory, PROM, and electronically reprogrammable read only memory. EPROM. However, these and other alternative memory devices tend to be more expensive and carry a greater risk of information being lost and are thus less reliable than ROMs.

The digital switching equipment according to Figure 1 is in practice connected to different digital or analog trunk lines or a combination of such. It can also be connected to different telephone subscriber loops. However, these are not shown, as they are not relevant for the description of a pulse code modulated, PCM, multifrequency, MF, signaling receiver in a digital telephone system. The digital switching equipment 1a operates in a format comprising 32 10-bit bytes per frame, the frame repetition frequency being about 8 kñz. A PCM MF receiver 1b is connected to the digital switching equipment 1a for receiving signaling from the trunk lines via the switch 1a. 32 PCM channels are connected from the switch device 1 via a PCM series signal trunk 2 to an input buffer register 30 in the receiver 1b.

Clock signals corresponding to the bit rate of the PCM signals on the trunk line 2 are connected from the digital switching equipment 1a to a sequence and timing circuit 10 in the receiver 1b via a clock signal line 3. A bus 4 for writing the registers is connected from the switch 1a to the input buffer registers 30 and to the circuit 10. The bus 4 transmits signals from a control device in the switch 1a to cause selected of the 32 channels of PCM signals to be stored in selected registers of the input buffer registers 30.

The circuit 10 generates read signals on a bus 27a for reading the registers, which cause the PCM samples, which have been stored in serial form in the buffer registers 30, to be selectively transmitted in parallel form to a digital filter 30a via lines 452 388 30b. After the contents of one of the buffer registers 30 have been transferred to the digital filter 30a, a signal is generated on an associated one of the lines of a bus 28a for emptying the register by means of the circuit 10 to cause the buffer register to be emptied. The digital filter 30a emits outputs representing received signal power of each selected channel sample and also signals representing filter function components corresponding to sec multi frequency tone signal bands. These output signals appear in series / parallel format on lines 43, 44a and 45a, representing characters and even and odd respectively. These lines transmit the output signal from the digital filter system to a signaling translation circuit 50. Both the digital filter system 30a and the signaling translation circuit 50 are controlled and synchronized by signals generated in the circuit 10. Control and timing signals are transmitted via a control bus 20 and a time bus 29, respectively. buses are connected from the circuit 10 to the digital filter 30a and the signaling translation circuit 50. The circuit 50 periodically receives the output signal from the digital filter 30a and generates binary signal codes compatible with the operation of the control device in the switching equipment and representing the signaling state of each one of the selected four of the 32 channels.

Each binary signal code includes information in a format as illustrated, for example, in Table A.

Table A Function Signal-1 Status- Error- Status- Sign / Error code bit 7 bit 6 bit 5 bit 4 Bit 3 Bit 2 Bit l§Bit 0 iciltig 1 Y 0 Y x x x x Signal; aus' o o o o o o o o o I I B spectral error 1 y 1 Y o z z z irride error 1 Y 1 Y x x x In the table, XXXX denotes the 4-bit code for a digit, the 3-bit ZZZ code for a spectral error and the YY code 452 388 for 2 bits for a signal power range.

The digital switching equipment 1a addresses the signaling translator circuit 50 via a selector bus 82 connected therebetween, to indicate that signaling information is required and from which of the four channels it is required.

The circuit 50 responds to the address of the selector bus 82 by transmitting a binary code in accordance with the format in Table A regarding the state of the selected channel, via an output data bus 83 to the digital switching equipment 1a.

With reference to Figure 2, the sequence and timing circuit comprises a counter 11 with a clock input CK connected to the clock signal line 3, which is described in connection with Figure 1. The counter 11 also comprises a storage input LD and outputs Q0-Q8 and an output Q14. A signal synchronized with the frame rate of the digital switching equipment 1a is applied to the storage input LD via a line 19a to synchronize the counter l1 at start-up. The outputs Q0-Q8 form the first part of the lines 0-8 in the control bus 20.

The output Q14 is connected to the input D1 of a 2-bit register 12. The counter 11 may be constructed of storage components and comprise a circuit for division with 10 followed by three circuits for division with 16. In such an arrangement only the storage input LD of the circuit for division with 10 actively connected to the line 19a, so that when a storage signal occurs only the circuit for division with 10 is set to 0. The register 12 of 2 bits can consist of two D-type flip-flops connected as shown in figure 2 Outputs Q1 and Ö1 of the register circuit 12 are connected to an AND gate 13, the output of which forms the beginning of a reset line 13a.

The register 12 in combination with the AND gate 13 generates a reset signal every 8 msec on the reset line 13a, in response to signals from the Q5 and Q14 outputs of the counter 11. In the control bus 20, the lines 7 and S are connected to inputs A0 and A1, respectively, of decoders 27 and 28.

Each decoder 27 and 28 includes outputs QO-Q3. The outputs of the decoder 27 form the beginning of lines 0-3 of the read bus 27a and the outputs of the decoder 28 form the beginning of lines 0-3 of the clearing bus 28a. The connection -nwuacnnncmnm-ulnm-u-.f fl- - - ----- ° "*" "" "" "" "452 388 of these buses and the control bus 20 will be shown with reference to Figures 3 and 4. each and one of a number of monostable flip-flops 91-94 comprises an input connected to one of the lines 0-3 in the write bus 4. Each of the flip-flops 91-94 also comprises an output connected to an input of an OR gate 94, which has an output connected to a synchronizing line 96. The remainder of the sequence and timing circuit in Figure 2 relates to the generation of time signals on lines, which falls within the general construction of time signal lines 29 in Figure 1. read memory, ROM, 14 comprises address input; AO-A6 connected to lines 0-6 in the control bus 20 and an address input A7 connected to the reset line 13. A. The ROM 14 also comprises data outputs DO-D7, of which the data output DO forms the beginning of a line 9 in the control bus 20. An 8-bit register 15 includes inputs DO-D6 connected to outputs D1-D3 of the ROM 14. Inputs D1, D2, D3 and D7 of the register 15 are connected to outputs Q0, Q1, Q2 and Q6, respectively, of the register 15. The output Q1 forms the beginning of a storage line 21 and the output Q6 form the beginning of a clock line 24 for storing registers. The outputs Q0 and Q1 of the register 15 are connected to inputs of a NOR gate 37, the output of which forms the beginning of a stop line 37a. The output Q3 of the register 15 forms the beginning of a line 22 for emptying the accumulator register. The output Q7 of the register 15 is connected to an input of an OR gate 17 to which another input is connected to receive clock signals from the line 3. The output of the OR gate 17 is connected to an activation input EN of the decoder circuit 28. An S- bit register 16 comprises inputs D1 and D2 connected to the output D5 and D6 of the read-only memory 14. The inputs D6 and D7 of the register 16 are connected to the synchronization line 96 and to an output Q6 of the register 16, respectively.

An output Q1 of the register 15 forms the beginning of a line 23 for storing the register. The output Q2 of the register 16 is connected to an input D4 of the same register. The corresponding 452 388 output Q4 is connected to an input D5. Output Q2 also forms the beginning of an integrator output register line 25 and an output QS of register 16 forms the beginning of a direct memory access line 26. Output Q6 is also connected to an input of an OR gate 19 and an output Q7 of register 16 is also connected to an input of the OR gate 19 via an inverter l8. The output from the OR gate 19 is connected via the line 19a to the storage input LD of the counter 11.

The operation of the sequence and timing circuit will now be described with reference to Figure 2 and the timing diagram of Figure 5. The entire time scales and waveforms of Figure 5 are shown in time relationship. Figure 5 shows 64 frames of TDM channels occupying a period of approx. 8 msec. The time scale is expanded to show a reset waveform on line 13a coinciding with the 64th frame. A single frame is shown spanning over a period of about 125 microseconds. and includes 32 channels O-31. The time scale is again expanded to display channels with PCM bytes, each comprising 10 bit periods 0-9. Each bit period is about 390 nsec and corresponds to the period of the clock signals on the clock signal line 3. The remaining waveforms in Figure 5 are shown relative to the second expansion of the time scale and the PCM bit periods, the shortest time distinction being half the bit period. The waveforms have been given such designations that their behavior and position in other figures become self-evident.

The counter 11 in Figure 2 counts clock signals appearing on line 3, the result of which is a binary speech sequence appearing on lines O-8 in control bus 20. In one example, the clock signals on line 3 have a pulse repetition frequency of 2.56 MHz. The counter 11 is synchronized with the PCM channel by means of a reset signal appearing on the line 19a, which causes the part of the counter 11 relating to division to be stored with only zeros. The reset signal appears in response to a write signal appearing on a line in the write bus 4. The associated monostable flip-flop 91-94 responds to the write signal and causes the D6 input 452 h of the register 16 to be exposed via the OR gate 95 and the synchronization line 96. The corresponding output Q6 is then also issued, which causes the reset signal to appear on the line 19a via the OR gate 19.

When Q6 is issued, which causes the output Q7 to be issued, the reset signal is terminated via the inverter 18 and the OR gate 19. Reset signals with a pulse width of 125 microseconds. and a cycle period of about 8 msec occurs on the reset line 13a. The reset signals on line 13a are the result of the clock signals on line 3 being divided by l0x211 and registered in register l2, the outputs of which undergo AND operation in AND gate 13. ROM 14 is addressed by the counter l1 and includes the logic required to operate the registers 15 and 16 together with associated gates for generating the timing signals illustrated in the diagram in Figure 5.

With reference to Figure 3, the input buffer registers 30, which are mentioned in connection with Figure 1, are provided by 8-bit serial / parallel registers 31-34. Each of the registers 31-34 comprises three control inputs, an activation input EN connected to an associated line in the write bus 4, a selector input SEL connected to an associated line in the read bus 27a, and an emptying input CL connected to a respective line in the discharge bus 28. Each of the registers 31-34 also comprises a series input S1 connected to the PCM series signal trunk 2 and an 8-line parallel output PO connected to lines 0-7 in the parallel PCM output bus 30b.

In operation, write signals are received from the digital switching equipment 1a via the write bus 4. A write signal appearing on a line in the bus 4 causes the associated input buffer register 3l-34 to store a PCM sample in series from the trunk line 2. Within the following 8 msec a read signal is generated by the decoder 27 and it appears on a corresponding line of the bus 27a, which causes the contents of the input buffer register to appear via the parallel output P0 of the bus 30b. immediately thereafter, an emptying signal appears on the corresponding line of the bus 28a for emptying the register, so that it comprises only ones. In the event that no write signal is applied to the input buffer register for a certain time, emptying the register prevents the following circuits from receiving repeated false indications of PCM samples.

In the digital filter, an 8-bit buffer register 35 is connected between the parallel PCM bus 30b and a linear square read memory 36. Eight data inputs DO-D7 of the register 35 are connected to the parallel PCH bus 30b and a clock input CK is connected to the clock line 24 of the storage register. Eight outputs Q0-Q7 of register 35 are connected to eight corresponding address inputs A0-A7 of read memory 36. An address input A8 of read memory 36 is connected to line 4 of control bus 20. The output of read memory 36 is connected to parallel inputs of smooth and odd data shift registers 38 and 39, so that the even register 38 only receives output bits with evenly numbered significance and the odd register 39 only receives output bits with odd numbered significance. The storage line 21 is connected to the storage input LD of the shift registers 38 and 39.

Each shift register 38 and 39 also comprises a series output SO connected to a corresponding series input S1 and a holding input H connected to the stop line 37a.

The read-only memory 36 is used to expand each sample of the PCM signal to its linear representation and to provide an approximation of the power of each sample.

Accordingly, the read-only memory 36 contains linear representations and corresponding approximate linear square representations of 256, 8-bit PCM words, which are used for transmission in the digital switching equipment. PCM data from registers 31-34 is selectively applied via the register 35 to the address inputs A0-A7 of the read-only memory 36. At each application of a PCM word, the signal applied to the address input A8 causes the read-only memory 36 to be addressed in its approximately linear square memory portion. and then in its linear memory part. The even and odd bits of the approximate square word and the linear word appearing at the output of the read-only memory 36 are each stored in the parallel inputs of the shift registers 38 and 39, respectively, under the control of the storage signal on the line 23.

A read only memory 40 in the filter comprises address inputs A0-A9 and data outputs DO-D15 connected to an accumulator _ with a 16 bit adder 41 and a 16 bit register 42.

The register 42 comprises a clarification input connected to the line 22 for clarifying or emptying the accumulator register. The address inputs A0-A1 of the read only memory 40 are connected to the series outputs S0 of the even and odd shift registers 38 and 39 via lines 38a and 39a, respectively. Eight bit smooth and odd shift registers 44 and 45 include parallel inputs for receiving even bits 0-12 and also bit 15 and odd bits 1-11 and bit 15, respectively, from the output of the adder 41. The serial outputs SO of the smooth shift register 44 and the odd shift registers 45 are connected to smooth and odd lines 44a and 45a, respectively, and to serial inputs S1 of 312-bit smooth and odd data shift registers 46 and 47, respectively. Each of the shift registers 44 and 45 comprises a storage input LD connected to the storage line 21. and a serial data input S1 connected in common to an output A1 from the last stage of the odd shift register 45. The output A1 also forms the beginning of the character line 43. Series outputs SO of the shift registers 46 and 47 are connected to the address inputs A2 and A3 of the read-only memory 40. and to serial inputs S1 of two 320-bit smooth and odd serial data shift registers 48 and 49, respectively. The shift register 48 includes a serial output SO connected to address the input A4 of the read-only memory 40 and the shift register 49 comprise a series output SO connected to the address input A5 of the read-only memory 40.

The remaining address inputs A6-A9 of the read only memory 40 are connected to the lines 4, 5, 6 and 9 of the control bus 20.

The read-only memory 40 contains data in memory positions accessible by means of binary addresses. The read-only memory 40 in combination with associated circuits causes the digital filter system to addressably address the characteristics of six narrow band filters and an all-pass filter through which the approximately linear square output of the read-only memory 36 is transmitted through the digital filter. Each narrow filter passband corresponds to one of the six multi-frequency signaling frequencies. The utilization of the all-pass filter characteristic is suitable, as it provides a routine by means of which the approximately linear square output from the read-only memory 36 'is passed through the digital filter system. This output can be routed directly to the signaling translator circuit in Figure 4, but to the greater cost of at least one additional buffer circuit and associated timing lines.

In operation, the approximate linear square value and then the linear value of a PCM sample are sequentially recorded in the even and odd registers 38 and 39. These serially shift the recorded bits via lines 38a and 39a to address inputs A0 and A1 of the read-only memory 40. data is also recirculated through registers 38 and 39 via respective serial inputs Sl. Thus, in connection with each occurrence of an address on the control bus 20, the data bits from the read only memory 36 will be presented in series for the read only memory 40 in pairs from the least significant bits to the most significant bits. When the least significant bit of the address on the control bus occurs at 1/10 of the speed of the system clock signal on line 3, the recirculation function of shift shifts 38 and 39 for 2 out of 10 clock signals is stopped by a stop signal on stop line 37a. Each linear value is presented by registers 38 and 39 for the read only memory 40 times as described above, each time in the presence of another of seven filter function addresses from the control bus 20. Each time an approximate quadratic value is stored in registers 38 and 39 it is presented directly in presence of the all-pass filter function address.

The read-only memory 40 generates read-out signals at the outputs DO-D15 at each occurrence of the clock signal. The signals are accumulated over a period of 8 cycles for the clock signal by means of the adder 41 and the register 42. When the space in the accumulator is limited, the connection between the output of the register 42 and the input of the adder 41 is arranged to shift recorded data two positions in the direction of smaller significance at each addition, thus excluding the two least significant bits. The address of the control bus 20 comprises a signal on the 9th line which is issued at the time of the 8th or last sample which appears at the inputs A0-A5 of the read-only memory 40. This means that a 2-complement is read out at the outputs D0-D15 of read-only memory 40, which provides a subtraction operation in the accumulator. at the end of each accumulation, the shift registers 44 and 45 are stored with the accumulated result being in binary 2-complement signal form. The fixed programmed data in the read-only memory 40 and the circuits so designed provide an output signal corresponding to a quarter representation of the filtered amplitude or power weight in different cases. When said data is in binary 2 complement form, it is multiplied by four to generate the required filter function value by storing the character bit 15 of the accumulated value in the first step of each shift resistors 44 and 45. The character bit 15 is also stored at the last the step in the shift register 45, ignoring the bits 13 and 14 from the adder 45. The accumulator register 42 is then set to only zeros by means of a signal on the discharge line 22. Simultaneously with the output of the sample from the shift registers 38 and 39, data bits are received from the registers 44 and 45 at the series inputs S1 of the shift registers 46 and 47, respectively. the character bit 15 is stored continuously at the serial inputs S1 of the registers 44 and 45 via the character line 43.

The 312-bit shift registers 46 and 47 operate continuously at the system clock frequency to register the data bits on lines 44a and 45a. During 10 clock periods, the first 8 bits recorded data and the last two bits recorded are insignificant. It should also be noted that the control bus transmits 10 addresses per sample. Thus, the combined length of the shift registers 44 and 46 and 45 and 47 is such that the result of previous filtered samples from a given channel is synchronized with the current sample for the given signal. Likewise, the output from the shift registers 48 and 49 of 320 bits synchronously provides the previously filtered sample for the given_channel. The addressing of the read-only memory 40 in combination with the data content of the read-only memory provides the required filter function for six frequencies and for power.

Since the 8th address of the control bus is not used efficiently in this embodiment, the fixed data in the read-only memory 40 corresponding to this filter function is arranged to contain only zeros.

With reference to Figure 4, the binary signals on the smooth line 44a and the character line 43 are received bit by bit by the signaling translation circuit via an exclusive OR gate 52. Similarly, the binary signals on the odd line 45a and also the character line 43 are received bit by bit. bit via another exclusive OR gate 53. The outputs of gates 52 and 53 are connected to the inputs A1 and A2 of a 2-bit adder 51. The reset line 13a is connected via an inverter 57 to inputs of AND gates 54 and 55 and to the clearance input CL of a flip-flop 56. An output of the flip-flop 56 is connected to a transfer input C of the adder 51. The outputs of the AND gates 54 and 55 are connected to inputs B1 and B2 of the adder 51. The adder 51 comprises outputs S1 and S2 connected to serial inputs S1 of two even and odd shift registers 60 and 61, respectively, of 320 bits each. Serial outputs S0 of the shift registers 60 and 61 are connected to serial inputs S1 of two shift registers 64 and 65, respectively, of 4 bits and to inputs of the AND gates 54 and 55, respectively. Parallel outputs of the shift registers 64 and 65 are connected to inputs of an 8-bit buffer register 66, the outputs of which are connected to a data bus 81. The shift register 66 also comprises a clock input CK connected to the integrator output register line 25 and an activation input EN connected to the reset line 13a.

A processor 70, a read only memory 71 and a direct access memory 72 are connected via the data bus 81 and an address bus 80. The processor 70 has an input connected to the reset line 13a and an output for writing the direct access memory connected to an input of an OR gate 77. The output of the OR gate 77 is connected to a write enable input of the direct access memory 72. A group of addressable output registers 85 are connected between the data bus 81 and the output data bus 83. A decoder 73 comprises inputs connected to the five most the significant lines in the address bus 80, an output connected via a selector line 74 for the read-only memory to the read-only memory 71, an output connected via a selector line 75 for the direct access memory to the direct access memory 72 and an output connected to a write enable input WE of the registers 85 Address write inputs W1 and W2 of registers 85 are connected to two lines in the address bus 80. Registers 85 also include address read inputs R1 and R2 and a read enable input RE, all connected to the selector 82. An address register 67 for the direct access memory is connected between the control bus 20 and the address bus 80. The register 67 comprises a clock input CK connected to the line 25 and an activation input EN connected to a reset acknowledgment output 70a of the processor 70.

In operation, the output of the digital filter 30a is applied to the signaling translator circuit 50 via the smooth line 44a and the odd line 45a with two data bits at a time, with the character bit continuously present on the character line 43 for the duration of 10 clock cycles. The smooth and odd data bits are subjected to an exclusive OR function with the character bit in gates 52 and 53, respectively, and then applied to inputs A1 and A2 of adder 51. Adder 51, gates 54 and 55, flip-flop 56 and registers 60 and 61 perform in combination a separate and distinct integration of the absolute value of the output of each filter function for each of the received TDM channels over a time period of 8 msec.

The output signals from the adder 51 are delayed from appearing at the inputs B1 and B2 by the smooth and odd shift registers i.: Ch 61 of 320 bits. A transmission signal occurring at the path SR of the adder 51 is delayed one clock period by the flip-flop 56 and is then applied to the transmission input C of the adderaxun 51. In this way, the corresponding filter function outputs are synchronized for the corresponding channel samples and accumulate. a period of 8 msec, as determined by the recovery signal on line 13a. The reset signal is secured for a period of the frame rate, about 125 microseconds.

Securing the reset signal inhibits AND gates 54 and 55 and clears flip-flop 56, thereby initiating a new accumulation period. Also during the reset signal, the data obtained during the most recent integrations is shifted out of the shift registers 60 and 61 via the shift registers 64 and 65 and is registered in parallel in the register 66.

The processor 70 is blocked by the reset signal for a period corresponding to 125 microseconds, so that under the control of the clock signal data received by the register 65 is compiled in parallel bytes on the line 25 and fed to the data bus 81. At the same time the register 67 transmits the signals on the control bus to the address bus 80. in response to the signal on the access line 26 to the direct access memory, the direct access memory 72 is caused to store all data accumulated during the just completed integration period at address positions determined by the signals on the control bus and within an address range determined by permanent signal input connections 67a of the buffer register 67. the exhibition period of 125 microseconds. for the reset signal, all signaling information has been stored in the direct access memory 72. The processor 70 resumes the function with associated circuits for translating the signaling to codes compatible with the digital switching equipment, as illustrated, for example, in Table A.

To facilitate this function, the processor 70 is controlled in its function for performing the functions according to the flow chart in Figure 6 by means of a suitable sequence of instruction codes, which is provided in the form of addressable logic in the read-only memory 71. The intention is not to discuss in detail the function of the processor, as is well known to those skilled in the art, which may specify an appropriate sequence of instruction codes suitable for performing the functions illustrated in the flow chart of Figure 6 and Table A. However, it should be noted that each special processor is limited to its range of operation and the speed at which it can operate. Of course, each selected processor in combination with a special set of instruction codes must be fast enough to process the results of each filter function within the period between issuing the reset signal. In the exemplary embodiment, there was a well-known microprocessor, type 8085, which operates with a cycle time of 1.3 microseconds. satisfactory, as it worked with logical instructions for implementing the functions according to the flow chart in Figure 6.

When translating the signaling, the available real-time for the treatment can be extended by only subjecting initialized multifrequency signaling to a rigorous validity test, while ongoing signaling is only subjected to a continuity check, which requires less real-time processing than the rigorous test. This method is particularly useful with a signaling receiver arranged to receive loop signaling, as the manual output of the signaling usually extends over a time in excess of the essential one.

Consequently, the outputs of a plurality of digital filters adapted to the loop signaling format can be translated by a single processor.

These two modes of operation are illustrated in the flow chart according to Figure 6, in which two alternative paths are available for processing current results during each period of 8 msec. To the left of the flowchart are shown the functions required to determine the validity of the first multifrequency signaling of a digit. To the right of the flow chart, the functions for determining ongoing multifrequency signaling of a digit are illustrated.

At the beginning of a period of 8 msec, the function of the signal translation circuit 50 is started. The three largest filter function amplitudes stored in the direct access memory 72 are first identified. If two of the three identified signals are above a predetermined amplitude and there was signaling during the two immediately preceding periods of 8 msec, the signaling digit is decoded. If this is the same as the corresponding channel digit decoded during the previous period of 8 msec, it is stored in a suitable output register 85. However, if the digit represents the third occurrence of 452 388 19 ° a digit that differs, the decoded digit is designated as an error .

At the beginning of a period of 8 msec, if there are not two amplitudes in the direct access memory 72, which are higher than a predetermined threshold value, and this was the case in the previous period of 8 msec, a pause indication is stored in the associated output register 85.

If there are two amplitudes that exceed the threshold value but there has been a previous pause, the amplitudes are subjected to validity tests, which include a series of tests to see if they meet the requirements for multi-frequency signaling. The amplitudes are compared with respect to imbalance, commonly referred to as twist, which exceeds 7 dB. If such a twist exceeding 7 dB occurs, the signal is considered invalid. In the case of acceptable twist, the smallest of the three amplitudes is compared with the average amplitude for checking said twist exceeds 12 dB. If it is less than 12 dB, the signaling is considered invalid. If this imbalance is acceptably large, the largest amplitude is compared with the approximate power value of the sample period to determine if the largest multifrequency signaling component is at least 20 dB over other signals considered to be noise and occurring during the sample period. If the functions mentioned above are obtained from two amplitudes representing valid signaling, the number they represent is decoded. If the previous period of 8 msec was indicated as a pause, the decoded digit is stored in the associated output register 85.

In one embodiment, the read only memory 40 in the digital filter 30a includes addressable logic, as set forth in the following tables. The addressable logic provides six narrow bandpass filter functions and an all-pass filter function. The six narrow band filter functions each have a passband corresponding to one of six tones with frequencies of 700 Hz, 900 Hz, ll00 Uz, 1300 Hz, 1500 Hz and 1700 Hz, respectively. These are the standard tone frequencies used in the multi-frequency signaling format in North America. The tables assume that the read-only memory 40 has been provided by means of four read-only memory devices 0-3, each contributing with four of the 16 output ports of the read-only memory 40 and with their respective address ports 452 388 20 interconnected. Each of the tables is given in hexadecimal notation with the less significant bits of the addresses extending over the top of the table, the more significant bits of the addresses extending over the left side of the table and the addressable logic forming the main part of the table. 452 388 21 2 03 ou os os 07 oa 09 01 oa oc on o o o ADD2 OO 01 0 000: 010; 020. 030: OUO: 050: Addressable logic table for ROM 40-O 1.7_U 1.9.1 3 Z.¿ 1.3.¿ 1.0_¿ 1 0 F 1 0 F P_0y0.0 0.rvF FFD 0 FEDO 32u3213211321021OF1OFEOOOOEEEEEDOPvHDO 1 1 1 B n, 0 FED nv0 0 0 0 0 E n, 0 F 0 PMD ODLFFYCEEDDCnL OEEEECBEDCCV .. 1O221O21oDA21ODL1oO-.IEAUOFEAUOOO111 .lO2210210F21OF1OwF fi LAVnIPLnLOOO DAExIOFDL1OFP ~ 1OPAEÛVAFEAUFEDOOOÛ øIE1OPAE1OFE1OFEOFEEOFn- »DUOOÛ FP ~ ~ 10FDL1OV4F 1OFV.OFEÜOT.EDOOOÛ11J.IQI1O PnL- [OFB-. lo fi vnn-uwloFDLOFEDOFSLDOOO »LDOTLBDOPInLHUAUFrLDOOOO-» LPVLDAP ED 0 FED 0 F BEV. «LDJE1OVAE1 ÉDÛFEDÜFPHÛÜFÉÜÛFÉDÛFEDÛÛÛ1111ÛFÛÛÛÛ1.1. ; u: ~ .u .Q n .n .a. a u »ou .n -. .s .o 0.0 0.0v0.0.0 0.0 0 3 0 0.U, U 0 O 0 Û O 0 0.0 0 0.0 OO 0 0.0.0 0.0 0 0 O Av7.R ~ 9 Ä EC DL F 0 1 7.3 U § .b_l 5 0.0 PCD É F 0 1 2 ~ $ Ub 5./.U 9 A Û O 0.0. 0 0 O. O 1 1 1 1 1 1 1 1 1 1.1 1 1 1 1 1 7 ~ 7.7 ~ 7_7.7_7.2 ^ ¿2 2 F P 2; 0: 200: 250: 350: 360; 452 388 22 370: 380: E 1 0 0.0 0 0 PN1 0 0. 0 O 21100000 P.1 O n.O 0 0 P_0 F 0. 0_O v ~ O F 0.0 0 O 5100000 P ~ 0 n.n.O 0 O? .2 1.0. O 0 F_¿ 1.0. O 0 P.2 1.0.0 O 0 F.¿ 1.O.O_0 O P_1 0.0 0.0 0 E4IOOOOO: 11110000 F 1 Û 0.0 0 0 Addressable logic table for ROM 40-l ADDR OO 01 02 03 OH 05 06 07 08 09 OA OB OC OD DE OF 0000112389 0000012288 000001-1278 OO00PAO1267 0000677801. 0000667801 00005677FO OOOOSSÅU7VLO 0 0 0.0 BCDE 0 .; OOÛOBCCDBQJ OOOOBBCDBQJ 0 0 0 0 Å_B C C_I Ü 0000112317 .. 0000012311 .. Û0ÜÛÛ1 | 12Û1 Oooooonlw / .OO .. .. .. .. .. .. .. _. .. .. .. 0000000000 Ü.l.l3üsfh_louüa 0000000000 EVAO1I3 ~ J DEDLOZaJ D E E F 1.? C Û E F O Å B C D 2 9ÅBC2 0191M81: BQJIABO 67882 56781 U5671.

USCJÖO 11 alu UCJÖ7BOJ8QÅFDOAUOO u. 3 55678789A000O h fi u5676789000O 2311- “5656 1 2 120: Slnßcnalz HM U. 130: 9 Å B C 0 1 nbgln fi urlo _lBn7 | nP. ~ R.

E ~ EO1ÅB DEFOQ / Å CDEPADUQ ..

BCDQVM7B 23hw533 780000 äJUOOOO 230000 4120000 0110000 ~ yooooo DDCOOOO ÅBÜÛÜO 9240000 U 5.0 0 0 O .luzah fl zzah fl ooøo Û.l231 | .1 0011200 1U0: 150: 160: 170: 180: 190: 230000 10000 150: ? 0: OOOOÜ.

OOAUOÜ. 00005 00005 OOOOIM 00009 00008 0000 0000 0000 OÛOO 0000 0000 0000 2UO: 5 5 rO (D I fl 337 58 0090 009? DUO / Cousin) .- Å »Å B 250: 9:50 897 896 9158 0 290: 452 388 23 EP NO: 2B0: BCQ .ÅEFDE3Hw1-27856OOÛ0 FOOOOOCQSuhB / .Dwårw / q / »ÜUïnfrbnsnwazßnhlnhnoooo 0 0 .AE89EFCD230167U5O000 ÉnvÛO0Å62F1.ïDÅDCÅQJUÉTÛÖSSUBÅÅÅÛÛOO CDÅBÛ1 | EFSS ~ JUQÅ7BÛÛOO D0ÜOO3ÛCBou / DU1.21._IE_ / 6U38765BÅÅÅ00ÛÛ Z COOO0DQ1CJ2FDDU87 / Cnw3ÅOJGQGQBB7EÅIAÅOOOO BCÅÅF0DEU5238967OO00 67cAÉEvICD7ÛG6O1EFOÛOÛ BOÛOÛÖäJPBPDB9fb532DCB9765U7776OÛO0 Û 67U5DECD67USFÛDEO00Û ÅOOnvÜÛC95GU20Q98ÛÛFr .CB7767766Û000 Û B967Û1 | EF9Å7823O10Ü0Û fx. 90nu00962ÉDB97ÛEDB321ÛÄ9B7776600O0 Û 0 7856F0DE896712FOO000 4 BÜO003FCBU2OE532O75U3EBA97766OO00 WMV ”Ö 3nw12wr0DEÅBQJÅÖ7Uf3Û0Û103J01BJ0FJ0J0J0J0J0J0J0J0J0J0J0J0JJJJJJJJJJJJJJJÖRHJJ 600ÛÛÖ2FBCÅB6B75UDBÅQÅAQIBÉÉBBOOOO. f 0 UCJ33 ~ | 1FOCÜÅBB967OÛOÛ. | _ 50ÛO0ÜCB531WIDDCÅQOFDCCBÅDJÉBïJBÛÛOrU ... l O e U523O <| EFBC9Å7Ü560OÛÛ .D UÛOOOQJÖZEÅÛÖÛBJOFÉDP. ÉÛOOÛQJFCSBBÖU1OEDÖSU.ÅBÅQJBOFFPOOÛO. 0 CJ E P C D 2.r C D E F C D E E C D O 0.0. .m ~ ¿. OO n.r_Q.š.1 2 FDB, b U ä.1 Q.nU7.§ # PC BA 0 PFF 0 0 0 0 O O-IÉFÛTEFÛ-IYYT-IFOOOÛO M .IÛOÛOÖZFBC / ßUÉBOJÛÖCBÅQEDCBÛFPFÛOOO 0 b OÛÛOUUYO. .n- v v u. I O z .. ..- OOÛOOOÛÛOOÛOOÛÛÛOÛÛÛ r. UOOOÛÛOÛÛOOOOOÛOÛOÛÛOOOOOOOÛÛOÛOO _.DEPAÛ.I2 JU.SG7BOJÅBCDFF d DJ01 ~ | ~ 23u56789ÅBCDEP1O125JUCJLu lQv9 | ABCDEV .. .A 22223333333333333333 ... nnuoøoøoÜnvøonuooøøoiaï-.l-l1 | 1a_ |. \ ... l1 | 1 | .l «| ..l« | 1. 24452388 00Û0FC73CÅ0É2O53FÉ2O32RUCCCC0000 ÛOOÛQÉBÛSBWFÛSOÛÛ 000O9§OD317575kB215U5UESCCCCOOOO 0O0O27C1531PD5D52 ÛÛOOCQUOÉC2OB7BÅ9ÛBÅOY21CCCCOOÛ0 OÛOOBÜSÅÉÉTFÅZÅQS OOAVQrOnÅDQSwJQ / q / DcnUPCE-.fnuznlwå f /. CCCCÛOÛO -... 000 014 953 531 80808 OOOOÛn / .Dgn / .OÖÜFPL21CIHEDSU7IOÜUDQJÜOOOO OOOODÜL7CECAB8OB1DU OOÛOFB7397DHü37GPETOTÉBÜBBQBÛOÛO ÛÜOOÖUOSECÅÜSDSEÅ OOOOBFÅBU2B66U975UB721U38898OO00 OOOOYUQEECÅBZÅZBD 0Û00C83ÛB9FDE9EC97BÅUBSSÜÜQÜOOOÛ 0ÖÛOBD27ÉCÅB08Û8Û Û0ÛÛ3FÅ61f5375Ä85597FÉ1Û33U30000 ÛÖ001ÖC175U2ÛB19O ÛOOOCQUOBÖCÅCÅFDQECBOÜÉTBÉUJOOOO 0O00ÅF5Ä75U2D5E62 00000C733175DCÛY0ï21CBEÛÉBUBOOÛÛ OÛOÛBBEÉYSUZÅZBÉS OÜÛÛQÖTDÅÛBC215U326ULDFÉ33U3ÛÛ0Û Ü0ÛÜC1ßB7531BO8OB OOOOQSOD- / lu bdgunj ~ lfß34lsqqlo3zonfoo others vooo 0O005B05ÛPDB81 | 91 | 8 OOOOBPÅÛEB2Û98CB658732U3OFÛ00O0Û 0000EU9EOFDB $ E6EA ÛOOOEZDÅQÖDBBQECCBFEEDOFOFUÛOOOO OOÛOOC730DU2OE31OE21OP10OFÛO000O Addressable logiktabcll ROH 40-3 ADD? 00 01 02 03 OH 05 06 07 08 09 OA OB OC OD OE OF. I. . .. ... I .. ... .- ... I. ... . ... - OOOOOOOOOOOOOOOOOOOOOOOÛÛRÛOOOOOO OOOOOOOOOOÛOOOOOO Û123U567B9ABCDEFO12ïU56789LBCDEF 0123U56789 ^ BCDEF0 22222272222222223333333333333333 00000000000000001 110: 120: 180: 2: U: U: U: 2: 2: 2: 2: 2: 2: 2: 2: 2: 2: 2: 1: 2: 1: 1: 1: 1: 1: 1: 1/1/1 | .UO 0 190: 1A0: 180 ICO: 1DO: 0 O OO OO 00 OO 00 00 00 OO 00 OO 00 OO 00 OO 230! 210: 006V. nu nu øL 1: nu nu nu nu nu nu nu 1: nu oothwf nu nu nu nu: J nUOnUD nu nu nu nu nu nu nu nu az Goal nu nu nu P »« | nu nu 01 P »0027 007D nu nu nu nu CJ .. _. _. .. 0000 nlwJus 2222 fi l. nl 0 280: 290: n ...

Balnßzß 1J «| ~ U3 nu w¿ 1¿ nu“ 208 a.

ZAO 280: 2 CO: 200: DC 8 390: 3h0: 320: 3F0: In another embodiment of the tone signaling receiver designed to receive PCM loop signaling tones, it is required that the addressable logic in read memory 40 can provide seven filter functions for frequencies which differs from the frequencies given above, whereby the addressable logic differs correspondingly.

Claims (11)

4> 071 FO (.: ~ | OO CO 26 Patent claim Signaling receiver for receiving pulse code modulated, PCM, tone signals, characterized by a receiving circuit (30) for receiving PCM signals from a selected channel, a circuit (10) for generating sets of control signals. each control signal in the set corresponding to a predetermined filter function in the signaling receiver, a digital filter circuit (30a) comprising a converter device (36) for converting each of the received PCH signals to. a corresponding linear binary signal with a plurality of bits, which digital filter circuit operates in dependence on the control signals and the linear-binary signals to provide a plurality of bandpass filter functions with respect to the linear binary signals in dependence on the control signals and generation of filter signals corresponding to the signal amplitudes of the linear signals with frequencies corresponding to the frequencies defined by the respective bandpass filter functions, and a translator circuit (50) receivable for the control signals and filter signals for detecting the presence of PCM signaling and translating said signaling into a data signal. predetermined signal code format. Receiver according to claim 1, characterized in that the translator circuit comprises a circuit (51-65) for integrating the filter signals for a predetermined period of time to obtain an integrated binary signal corresponding to an amplitude value for a series of each one of the filter functions, a temporary storage means (72) for temporarily storing the integrated binary signals, a storage means (71) with stored logical instructions at positions accessible under addresses, a processor (70) connected for reading said temporarily stored integrated secondary signals and said stored logic instructions, which processor is arranged to operate in accordance with said stored logic instructions for identifying the two largest of the temporarily stored integrated binary signals and comparing the identifiers. 588 27 the signals one with the other to determine the value of imbalance therebetween. Receiver according to claim 2, characterized in that the converter means also works for converting the received PCM signals into an output signal corresponding to an approximate quadratic value of the corresponding linear binary signal and that the processor can operate in accordance with said stored logic instructions for comparing the power signal with one of the identified signals for determining a signal-to-noise ratio of a size acceptable for valid multi-frequency signaling. _ A receiver according to claim 1, characterized in that the converter device also operates to convert the received PCM signals into binary power signals, each corresponding to an approximately square value of a corresponding one of the linear binary signals, and that the translator circuit comprises a circuit (51-65) for individually integrating the filter signals corresponding to each filter function and the power signals for a predetermined period of time to obtain an integrated binary signal corresponding to a series of each of the filter functions and the binary power signals, a temporary storage means (72) for temporarily storing the integrated binary signals, a storage means (71) with stored logical instructions at positions accessible under addresses, a processor (70) connected for reading said temporarily stored signals and said stored logical instructions, which processor can operate in accordance with said stored logical instructions for identifying the three largest of the stored integrated signals, comparing the two largest of the identified signals regarding a value of imbalance that is acceptably small for valid signaling, comparing the second largest identified signal with the smaller identified signal regarding a size difference acceptably large for valid signaling and comparing one of the largest identified signals with the binary power signals regarding a signal-to-noise ratio that is acceptably large for valid signaling. Receiver according to claim 1, characterized in that the digital filter circuit comprises a memory means (40) with groups of data bits stored at sub-address accessible positions therein, address ports (A) and data ports (D), a plurality of the address ports are connected to receive a portion of each of the control signals and the memory means is arranged to present selected by said bytes at the data ports in response to the signal states of the address ports, an accumulator circuit (41-42) connected to the data ports for accumulating the data bytes for a predetermined time interval for generating one of said amplitude signals, and input circuits (38, 39, 46k 47, 48, 49) connected for receiving the bits of the linear binary signals from the converter device and said amplitude signals, which input circuits are arranged to synchronously to the address gates with the current linear binary signal add the corresponding previous amplitude ignal and the corresponding previously preceding amplitude signal, each of said signals being applied in serial / parallel bit format. Receiver according to claim 1, characterized in that the digital filter circuit comprises a memory means (40) with groups of data bits stored at positions accessible below addresses therein, data ports (D) and a plurality of first (A0, A1), second (A2) , A3) and third (A4, A5) address ports and control address ports (A6-A9), the control address ports being connected to receive the control signals, the data bits being arranged to facilitate the filter functions selected by the control signals, and the memory means arranged to present selected data bit groups at the data ports depending on the signal states of the address ports, first input circuits (38, 39) connected between the converter device and the first address ports to sequentially supply the bits in each linear binary signal in parallel arrays of at least two to the first address ports at each occurrence of one of the control signals, an accumulator circuit (41, 42) connected to the data ports for accumulating the bytes during the duration of each individual control signal for generating a corresponding one of said amplitude signals, output circuits (44, 45) connected between the accumulator circuit and the translator circuit for sequential output of bits of each amplitude signal in said 452 388 29 'parallel arrays, second input circuits, 46, 47) connected between the output circuits and the second address ports for delaying the arrival of said parallel groupings of each amplitude signal to the second address ports for a predetermined period of time to synchronize each amplitude signal with a following corresponding linear binary signal and the occurrence of corresponding filter function , and third input circuits (48, 49) connected to the third address ports for delaying the arrival of said parallel arrays of each amplitude signal to the third address ports for a predetermined time to synchronize each amplitude signal with a corresponding signal next to the following spirit corresponds the linear binary signal and the occurrence of corresponding filter function 7 'lasting alarming amplitude signals are generated sequentially. Receiver according to claim 1, characterized in that the translator circuit comprises a processor (70) and a device (71) for causing the processor to determine the validity of the initial PCM multi-frequency signaling by performing a series of process functions requiring a first determined time period for its execution and to cause the processor to determine the continuity of ongoing PCM multi-frequency signaling by means of a second series of process functions, which require a shorter time period for re-execution than the first time period. Receiver according to claim 1 for receiving and translating PCM multi-frequency signaling into a signal code format compatible with a control device in a time division multiplexing switching equipment, characterized in that the receiver comprises a sequence and timing control circuit (10) connected to be synchronized with the switching equipment for generating a set of control signals on a repetitive basis and a time-divided filter circuit (30a) arranged to perform in dependence on the control signals a plurality of predetermined bandpass filter functions for a series of PCM signals received from the switching equipment and to generate a corresponding series of amplitude signals with respect to each of said filter functions, and that the signaling translator circuit (50) is arranged to determine, depending on the control signals and said amplitude signals, the occurrence of valid signaling and translation of said valid signaling into data signals with a predetermined tamed signal code format. A method of receiving pulse code modulated, PCM, tone signals for conversion to a signal code format compatible with a control device in a time division multiplexer switching apparatus, comprising a) receiving PCM signals selected by the switching equipment, and b) converting each of the received PCM signals to a corresponding linear binary signal with a plurality of bits, characterized by c) generating at least one set of control signals in connection with each occurrence of a frame in the PCM signal format, d) performing of a plurality of digital bandpass filter functions regarding the linear binary signals in accordance with the control signals and generating amplitude signals consisting of signal bits and the corresponding signal amplitudes of the linear binary signals with frequencies corresponding to the frequencies defined by the respective bandpass filter function , and e) detecting the frequency of multifrequency signaling from amplitude number och smna and the conversion of the multifaceted signal into the control signals into data signals in said signal format. The method of claim 9, wherein step d) is performed in a digital filter comprising a memory (40) having data bytes stored at sub-addressable positions therein, characterized in that the sueætcm reaches fi m fi zr: f) causing the memory to read out said bytes selected by address signals applied thereto, which address signals consist of signal bits and comprise a part of each of the control signals, g) storing the bytes read from the memory for a predetermined period of time to generate one of said amplitude signals, h generating a portion of each of said address signals - - wwr-efw-nnn 452 388 31 'from a current of said linear binary signals, corresponding to previous amplitude signal and corresponding before this previous amplitude signal, and i) supplying said sequentially in serial / parallel format in groups of at least six bits each to the memory during the predetermined time period. 11. ll. Method according to claim 9, characterized in that step e) is characterized by determining whether the signaling is initial or continuous and in the first case carrying out a series of processing functions for determining the validity of the signaling and in the second case carrying out another series of processing functions for determining the continuity of the current signaling with regard to immediately preceding signaling.