NL7905381A - Werkwijze voor het selectief modificeren van geintegreerde halfgeleiderinrichtingen. - Google Patents

Werkwijze voor het selectief modificeren van geintegreerde halfgeleiderinrichtingen. Download PDF

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Publication number
NL7905381A
NL7905381A NL7905381A NL7905381A NL7905381A NL 7905381 A NL7905381 A NL 7905381A NL 7905381 A NL7905381 A NL 7905381A NL 7905381 A NL7905381 A NL 7905381A NL 7905381 A NL7905381 A NL 7905381A
Authority
NL
Netherlands
Prior art keywords
ions
photo
passivation layer
layer
resistant layer
Prior art date
Application number
NL7905381A
Other languages
English (en)
Dutch (nl)
Original Assignee
Standard Microsyst Smc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Microsyst Smc filed Critical Standard Microsyst Smc
Publication of NL7905381A publication Critical patent/NL7905381A/nl

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/27ROM only
    • H10B20/30ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38Doping programmed, e.g. mask ROM
    • H10B20/387Source region or drain region doping programmed
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/091Laser beam processing of fets
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/143Shadow masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Non-Volatile Memory (AREA)
NL7905381A 1978-08-03 1979-07-10 Werkwijze voor het selectief modificeren van geintegreerde halfgeleiderinrichtingen. NL7905381A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93073978 1978-08-03
US05/930,739 US4208780A (en) 1978-08-03 1978-08-03 Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer

Publications (1)

Publication Number Publication Date
NL7905381A true NL7905381A (nl) 1980-02-05

Family

ID=25459689

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7905381A NL7905381A (nl) 1978-08-03 1979-07-10 Werkwijze voor het selectief modificeren van geintegreerde halfgeleiderinrichtingen.

Country Status (6)

Country Link
US (1) US4208780A (de)
JP (1) JPS5522890A (de)
DE (1) DE2916843A1 (de)
FR (1) FR2432767A1 (de)
GB (1) GB2028581B (de)
NL (1) NL7905381A (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4294001A (en) * 1979-01-08 1981-10-13 Texas Instruments Incorporated Method of making implant programmable metal gate MOS read only memory
US4342100A (en) * 1979-01-08 1982-07-27 Texas Instruments Incorporated Implant programmable metal gate MOS read only memory
US4294002A (en) * 1979-05-21 1981-10-13 International Business Machines Corp. Making a short-channel FET
US4282646A (en) * 1979-08-20 1981-08-11 International Business Machines Corporation Method of making a transistor array
US4514897A (en) * 1979-09-04 1985-05-07 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
US4364167A (en) * 1979-11-28 1982-12-21 General Motors Corporation Programming an IGFET read-only-memory
US4336647A (en) * 1979-12-21 1982-06-29 Texas Instruments Incorporated Method of making implant programmable N-channel read only memory
US4356042A (en) * 1980-11-07 1982-10-26 Mostek Corporation Method for fabricating a semiconductor read only memory
US4698899A (en) * 1983-10-19 1987-10-13 Gould Inc. Field effect transistor
WO1986001931A1 (en) * 1984-09-07 1986-03-27 Pa Consulting Services Limited Method and apparatus for loading information into an integrated circuit semiconductor device
EP0233862A1 (de) * 1985-08-27 1987-09-02 LOCKHEED MISSILES & SPACE COMPANY, INC. Verfahren zum ausrichten der gate bei der herstellung von halbleiteranordnungen
IT1186430B (it) * 1985-12-12 1987-11-26 Sgs Microelettrica Spa Rpocedimento per la realizzazione di memorie a sola lettura in tecnologia nmos programmate mediante impiantazione ionica e memoria a sola lettura ottenuta mediante tale procedimento
JPS62120127U (de) * 1986-01-22 1987-07-30
WO1990007794A1 (de) * 1988-12-23 1990-07-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Hochspannungstransistor-anordnung in cmos-technologie
IT1239707B (it) * 1990-03-15 1993-11-15 St Microelectrics Srl Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain
JP2835216B2 (ja) * 1991-09-12 1998-12-14 株式会社東芝 半導体装置の製造方法
JP2771057B2 (ja) * 1991-10-21 1998-07-02 シャープ株式会社 半導体装置の製造方法
EP0575688B1 (de) * 1992-06-26 1998-05-27 STMicroelectronics S.r.l. Programmierung von LDD-ROM-Zellen
US5306657A (en) * 1993-03-22 1994-04-26 United Microelectronics Corporation Process for forming an FET read only memory device
US5633202A (en) * 1994-09-30 1997-05-27 Intel Corporation High tensile nitride layer
US5459086A (en) * 1994-11-07 1995-10-17 United Microelectronics Corporation Metal via sidewall tilt angle implant for SOG
DE19505293A1 (de) * 1995-02-16 1996-08-22 Siemens Ag Mehrwertige Festwertspeicherzelle mit verbessertem Störabstand
TW335537B (en) * 1996-11-25 1998-07-01 United Microelectronics Corp The ROM unit and manufacture method
US6027978A (en) * 1997-01-28 2000-02-22 Advanced Micro Devices, Inc. Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US6093951A (en) * 1997-06-30 2000-07-25 Sun Microsystems, Inc. MOS devices with retrograde pocket regions
US6249027B1 (en) 1998-06-08 2001-06-19 Sun Microsystems, Inc. Partially depleted SOI device having a dedicated single body bias means
JP3137077B2 (ja) * 1998-06-16 2001-02-19 日本電気株式会社 半導体装置及びその製造方法
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6228777B1 (en) 1999-06-08 2001-05-08 Intel Corporation Integrated circuit with borderless contacts
US6960510B2 (en) * 2002-07-01 2005-11-01 International Business Machines Corporation Method of making sub-lithographic features

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1047390A (de) * 1963-05-20 1900-01-01
BE759057A (de) * 1969-11-19 1971-05-17 Philips Nv
US3775191A (en) * 1971-06-28 1973-11-27 Bell Canada Northern Electric Modification of channel regions in insulated gate field effect transistors
GB1534896A (en) * 1975-05-19 1978-12-06 Itt Direct metal contact to buried layer
US4080718A (en) * 1976-12-14 1978-03-28 Smc Standard Microsystems Corporation Method of modifying electrical characteristics of MOS devices using ion implantation

Also Published As

Publication number Publication date
JPS5522890A (en) 1980-02-18
US4208780A (en) 1980-06-24
DE2916843A1 (de) 1980-02-21
GB2028581A (en) 1980-03-05
JPS6260817B2 (de) 1987-12-18
DE2916843C2 (de) 1988-09-29
FR2432767B3 (de) 1982-01-22
FR2432767A1 (fr) 1980-02-29
GB2028581B (en) 1983-01-12

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Legal Events

Date Code Title Description
A85 Still pending on 85-01-01
BA A request for search or an international-type search has been filed
BB A search report has been drawn up
BC A request for examination has been filed
BV The patent application has lapsed