NL7706108A - Werkwijze voor het vormen van een patroon van geleiders op een op een substraat aangebrachte isolerende laag. - Google Patents

Werkwijze voor het vormen van een patroon van geleiders op een op een substraat aangebrachte isolerende laag.

Info

Publication number
NL7706108A
NL7706108A NL7706108A NL7706108A NL7706108A NL 7706108 A NL7706108 A NL 7706108A NL 7706108 A NL7706108 A NL 7706108A NL 7706108 A NL7706108 A NL 7706108A NL 7706108 A NL7706108 A NL 7706108A
Authority
NL
Netherlands
Prior art keywords
conductors
pattern
substrate
forming
insulating layer
Prior art date
Application number
NL7706108A
Other languages
English (en)
Dutch (nl)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of NL7706108A publication Critical patent/NL7706108A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01072Hafnium [Hf]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143Masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/106Masks, special
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/15Silicon on sapphire SOS
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
NL7706108A 1976-06-30 1977-06-03 Werkwijze voor het vormen van een patroon van geleiders op een op een substraat aangebrachte isolerende laag. NL7706108A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/701,451 US4076575A (en) 1976-06-30 1976-06-30 Integrated fabrication method of forming connectors through insulative layers

Publications (1)

Publication Number Publication Date
NL7706108A true NL7706108A (nl) 1978-01-03

Family

ID=24817435

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7706108A NL7706108A (nl) 1976-06-30 1977-06-03 Werkwijze voor het vormen van een patroon van geleiders op een op een substraat aangebrachte isolerende laag.

Country Status (10)

Country Link
US (1) US4076575A (fr)
JP (1) JPS533172A (fr)
BE (1) BE855162A (fr)
BR (1) BR7704314A (fr)
CA (1) CA1082370A (fr)
CH (1) CH614562A5 (fr)
DE (1) DE2729030C2 (fr)
FR (1) FR2357071A1 (fr)
IT (1) IT1115667B (fr)
NL (1) NL7706108A (fr)

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US4289834A (en) * 1977-10-20 1981-09-15 Ibm Corporation Dense dry etched multi-level metallurgy with non-overlapped vias
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
JPS6019608B2 (ja) * 1978-10-03 1985-05-17 シャープ株式会社 電極パタ−ン形成方法
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US4181755A (en) * 1978-11-21 1980-01-01 Rca Corporation Thin film pattern generation by an inverse self-lifting technique
US4275286A (en) * 1978-12-04 1981-06-23 Hughes Aircraft Company Process and mask for ion beam etching of fine patterns
US4202914A (en) * 1978-12-29 1980-05-13 International Business Machines Corporation Method of depositing thin films of small dimensions utilizing silicon nitride lift-off mask
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US4272561A (en) * 1979-05-29 1981-06-09 International Business Machines Corporation Hybrid process for SBD metallurgies
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US4371423A (en) * 1979-09-04 1983-02-01 Vlsi Technology Research Association Method of manufacturing semiconductor device utilizing a lift-off technique
JPS5710926A (en) * 1980-06-25 1982-01-20 Toshiba Corp Manufacture of semiconductor device
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4407859A (en) * 1980-10-17 1983-10-04 Rockwell International Corporation Planar bubble memory circuit fabrication
US4339305A (en) * 1981-02-05 1982-07-13 Rockwell International Corporation Planar circuit fabrication by plating and liftoff
DE3175488D1 (en) * 1981-02-07 1986-11-20 Ibm Deutschland Process for the formation and the filling of holes in a layer applied to a substrate
US4391849A (en) * 1982-04-12 1983-07-05 Memorex Corporation Metal oxide patterns with planar surface
US4517616A (en) * 1982-04-12 1985-05-14 Memorex Corporation Thin film magnetic recording transducer having embedded pole piece design
JPS58187260A (ja) * 1982-04-26 1983-11-01 Mitsubishi Electric Corp アルミニウム金属への半田被着法
US4446194A (en) * 1982-06-21 1984-05-01 Motorola, Inc. Dual layer passivation
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
US4415606A (en) * 1983-01-10 1983-11-15 Ncr Corporation Method of reworking upper metal in multilayer metal integrated circuits
GB2141582B (en) * 1983-06-16 1986-10-29 Plessey Co Plc A method of producing a layered structure
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US4451326A (en) * 1983-09-07 1984-05-29 Advanced Micro Devices, Inc. Method for interconnecting metallic layers
US4597177A (en) * 1984-01-03 1986-07-01 International Business Machines Corporation Fabricating contacts for flexible module carriers
KR960009090B1 (ko) * 1984-03-22 1996-07-10 에스지에스 톰슨 마이크로일렉트로닉스, 인코 오포레이티드 표준 배열의 접촉 패드를 가진 집적회로
US4627151A (en) * 1984-03-22 1986-12-09 Thomson Components-Mostek Corporation Automatic assembly of integrated circuits
US4548903A (en) * 1984-03-30 1985-10-22 The United States Of America As Represented By The Secretary Of The Air Force Method to reveal microstructures in single phase alloys
US4640738A (en) * 1984-06-22 1987-02-03 International Business Machines Corporation Semiconductor contact protection
JPS6276600A (ja) * 1985-09-29 1987-04-08 株式会社 アサヒ化学研究所 基板に導電回路を形成する方法
US4695853A (en) * 1986-12-12 1987-09-22 Hewlett-Packard Company Thin film vertical resistor devices for a thermal ink jet printhead and methods of manufacture
US5162191A (en) * 1988-01-05 1992-11-10 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5488394A (en) * 1988-01-05 1996-01-30 Max Levy Autograph, Inc. Print head and method of making same
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US20060252163A1 (en) * 2001-10-19 2006-11-09 Nano-Proprietary, Inc. Peelable photoresist for carbon nanotube cathode
KR20030068733A (ko) * 2002-02-16 2003-08-25 광전자 주식회사 평탄화 구조를 갖는 반도체 소자 및 그 제조방법
US6569763B1 (en) * 2002-04-09 2003-05-27 Northrop Grumman Corporation Method to separate a metal film from an insulating film in a semiconductor device using adhesive tape
WO2004097915A1 (fr) * 2003-04-25 2004-11-11 Semiconductor Energy Laboratory Co., Ltd. Dispositif de decharge de gouttelettes, procede de formation de motifs et procede de production d'un dispositif a semi-conducteur
US7273773B2 (en) * 2004-01-26 2007-09-25 Semiconductor Energy Laboratory Co., Ltd. Display device, method for manufacturing thereof, and television device
US7462514B2 (en) 2004-03-03 2008-12-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same, liquid crystal television, and EL television
US7642038B2 (en) * 2004-03-24 2010-01-05 Semiconductor Energy Laboratory Co., Ltd. Method for forming pattern, thin film transistor, display device, method for manufacturing thereof, and television apparatus
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EA029641B1 (ru) * 2015-02-04 2018-04-30 Открытое акционерное общество "ИНТЕГРАЛ"-управляющая компания холдинга "ИНТЕГРАЛ" Металлизация интегральной схемы
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US3451867A (en) * 1966-05-31 1969-06-24 Gen Electric Processes of epitaxial deposition or diffusion employing a silicon carbide masking layer
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US3837907A (en) * 1972-03-22 1974-09-24 Bell Telephone Labor Inc Multiple-level metallization for integrated circuits
JPS529513B2 (fr) * 1972-06-23 1977-03-16
DE2235749C3 (de) * 1972-07-21 1979-09-20 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen eines Leitbahnenmusters
US3877051A (en) * 1972-10-18 1975-04-08 Ibm Multilayer insulation integrated circuit structure
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask

Also Published As

Publication number Publication date
CH614562A5 (fr) 1979-11-30
DE2729030A1 (de) 1978-01-05
CA1082370A (fr) 1980-07-22
IT1115667B (it) 1986-02-03
JPS533172A (en) 1978-01-12
DE2729030C2 (de) 1982-07-01
BE855162A (fr) 1977-09-16
BR7704314A (pt) 1978-05-16
US4076575A (en) 1978-02-28
FR2357071B1 (fr) 1980-12-19
FR2357071A1 (fr) 1978-01-27

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