NL7302989A - - Google Patents

Info

Publication number
NL7302989A
NL7302989A NL7302989A NL7302989A NL7302989A NL 7302989 A NL7302989 A NL 7302989A NL 7302989 A NL7302989 A NL 7302989A NL 7302989 A NL7302989 A NL 7302989A NL 7302989 A NL7302989 A NL 7302989A
Authority
NL
Netherlands
Application number
NL7302989A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL7302989A publication Critical patent/NL7302989A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Casings For Electric Apparatus (AREA)
NL7302989A 1972-03-22 1973-03-02 NL7302989A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2213915A DE2213915A1 (de) 1972-03-22 1972-03-22 Gehaeuse fuer halbleitersysteme

Publications (1)

Publication Number Publication Date
NL7302989A true NL7302989A (en:Method) 1973-09-25

Family

ID=5839779

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7302989A NL7302989A (en:Method) 1972-03-22 1973-03-02

Country Status (9)

Country Link
JP (1) JPS496880A (en:Method)
AT (1) AT327989B (en:Method)
CA (1) CA979122A (en:Method)
CH (1) CH548109A (en:Method)
DE (1) DE2213915A1 (en:Method)
FR (1) FR2176661B1 (en:Method)
GB (1) GB1397330A (en:Method)
IT (1) IT982542B (en:Method)
NL (1) NL7302989A (en:Method)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
GB2146174B (en) * 1983-09-06 1987-04-23 Gen Electric Hermetic power chip packages

Also Published As

Publication number Publication date
IT982542B (it) 1974-10-21
FR2176661A1 (en:Method) 1973-11-02
ATA1012972A (de) 1975-05-15
JPS496880A (en:Method) 1974-01-22
CH548109A (de) 1974-04-11
AT327989B (de) 1976-02-25
CA979122A (en) 1975-12-02
FR2176661B1 (en:Method) 1977-12-30
DE2213915A1 (de) 1973-10-04
GB1397330A (en) 1975-06-11

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