NL7204741A - - Google Patents

Info

Publication number
NL7204741A
NL7204741A NL7204741A NL7204741A NL7204741A NL 7204741 A NL7204741 A NL 7204741A NL 7204741 A NL7204741 A NL 7204741A NL 7204741 A NL7204741 A NL 7204741A NL 7204741 A NL7204741 A NL 7204741A
Authority
NL
Netherlands
Application number
NL7204741A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to NL7204741A priority Critical patent/NL7204741A/xx
Priority to CA167,713A priority patent/CA970478A/en
Priority to US347806A priority patent/US3900350A/en
Priority to AU54064/73A priority patent/AU463001B2/en
Priority to IT67984/73A priority patent/IT980775B/it
Priority to DE19732317087 priority patent/DE2317087C3/de
Priority to GB1631073A priority patent/GB1421212A/en
Priority to JP48039625A priority patent/JPS5212070B2/ja
Priority to FR7312668A priority patent/FR2179864B1/fr
Publication of NL7204741A publication Critical patent/NL7204741A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/037Diffusion-deposition
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/043Dual dielectric
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/114Nitrides of silicon
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/122Polycrystalline
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/151Simultaneous diffusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
NL7204741A 1972-04-08 1972-04-08 NL7204741A (hu)

Priority Applications (9)

Application Number Priority Date Filing Date Title
NL7204741A NL7204741A (hu) 1972-04-08 1972-04-08
CA167,713A CA970478A (en) 1972-04-08 1973-04-02 Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, and semiconductor devices manufactured in this manner
US347806A US3900350A (en) 1972-04-08 1973-04-04 Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, wherein an intermediate layer of polycrystalline silicon is provided between the substrate and the oxidation mask
AU54064/73A AU463001B2 (en) 1972-04-08 1973-04-04 Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, and semiconductor devices manufactured in this manner
IT67984/73A IT980775B (it) 1972-04-08 1973-04-05 Procedimento per la fabbricazione di dispositivi semiconduttori e di spositivi ottenuti con il procedi mento
DE19732317087 DE2317087C3 (de) 1972-04-08 1973-04-05 Verfahren zur Herstellung von Halbleiteranordnungen, bei dem in Silizium versenkte Siliziumoxidgebiete durch maskierende Oxydation gebildet werden
GB1631073A GB1421212A (en) 1972-04-08 1973-04-05 Semiconductor device manufacture
JP48039625A JPS5212070B2 (hu) 1972-04-08 1973-04-09
FR7312668A FR2179864B1 (hu) 1972-04-08 1973-04-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7204741A NL7204741A (hu) 1972-04-08 1972-04-08

Publications (1)

Publication Number Publication Date
NL7204741A true NL7204741A (hu) 1973-10-10

Family

ID=19815806

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7204741A NL7204741A (hu) 1972-04-08 1972-04-08

Country Status (8)

Country Link
US (1) US3900350A (hu)
JP (1) JPS5212070B2 (hu)
AU (1) AU463001B2 (hu)
CA (1) CA970478A (hu)
FR (1) FR2179864B1 (hu)
GB (1) GB1421212A (hu)
IT (1) IT980775B (hu)
NL (1) NL7204741A (hu)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2409910C3 (de) * 1974-03-01 1979-03-15 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen einer Halbleiteranordnung
JPS5824951B2 (ja) * 1974-10-09 1983-05-24 ソニー株式会社 コウガクソウチ
JPS6022497B2 (ja) * 1974-10-26 1985-06-03 ソニー株式会社 半導体装置
JPS5187979A (ja) * 1975-01-31 1976-07-31 Hitachi Ltd Bunryosankabutsuryoikiojusuru handotaisochinoseizohoho
JPS5197385A (en) * 1975-02-21 1976-08-26 Handotaisochino seizohoho
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
US3961999A (en) * 1975-06-30 1976-06-08 Ibm Corporation Method for forming recessed dielectric isolation with a minimized "bird's beak" problem
JPS5246784A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Process for production of semiconductor device
JPS5253679A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Productin of semiconductor device
JPS5261972A (en) * 1975-11-18 1977-05-21 Mitsubishi Electric Corp Production of semiconductor device
JPS5922381B2 (ja) * 1975-12-03 1984-05-26 株式会社東芝 ハンドウタイソシノ セイゾウホウホウ
US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
US4401691A (en) * 1978-12-18 1983-08-30 Burroughs Corporation Oxidation of silicon wafers to eliminate white ribbon
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS5645051A (en) * 1979-09-20 1981-04-24 Toshiba Corp Manufacture of semiconductor device
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
US4465705A (en) * 1980-05-19 1984-08-14 Matsushita Electric Industrial Co., Ltd. Method of making semiconductor devices
EP0048175B1 (en) * 1980-09-17 1986-04-23 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
US4508757A (en) * 1982-12-20 1985-04-02 International Business Machines Corporation Method of manufacturing a minimum bird's beak recessed oxide isolation structure
JPS6054453A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体集積回路装置の製造方法
US4541167A (en) * 1984-01-12 1985-09-17 Texas Instruments Incorporated Method for integrated circuit device isolation
US4691222A (en) * 1984-03-12 1987-09-01 Harris Corporation Method to reduce the height of the bird's head in oxide isolated processes
US4612701A (en) * 1984-03-12 1986-09-23 Harris Corporation Method to reduce the height of the bird's head in oxide isolated processes
US4630356A (en) * 1985-09-19 1986-12-23 International Business Machines Corporation Method of forming recessed oxide isolation with reduced steepness of the birds' neck
US4824795A (en) * 1985-12-19 1989-04-25 Siliconix Incorporated Method for obtaining regions of dielectrically isolated single crystal silicon
JPS6410644A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Manufacture of semiconductor device
US5039625A (en) * 1990-04-27 1991-08-13 Mcnc Maximum areal density recessed oxide isolation (MADROX) process
KR960005556B1 (ko) * 1993-04-24 1996-04-26 삼성전자주식회사 반도체장치의 소자분리방법
JP4746639B2 (ja) * 2008-02-22 2011-08-10 株式会社東芝 半導体デバイス

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1147014A (en) * 1967-01-27 1969-04-02 Westinghouse Electric Corp Improvements in diffusion masking
NL169121C (nl) * 1970-07-10 1982-06-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon.
US3719535A (en) * 1970-12-21 1973-03-06 Motorola Inc Hyperfine geometry devices and method for their fabrication
US3784847A (en) * 1972-10-10 1974-01-08 Gen Electric Dielectric strip isolation for jfet or mesfet depletion-mode bucket-brigade circuit

Also Published As

Publication number Publication date
IT980775B (it) 1974-10-10
JPS5212070B2 (hu) 1977-04-04
CA970478A (en) 1975-07-01
FR2179864A1 (hu) 1973-11-23
GB1421212A (en) 1976-01-14
FR2179864B1 (hu) 1976-09-10
US3900350A (en) 1975-08-19
AU463001B2 (en) 1975-07-10
AU5406473A (en) 1974-10-10
DE2317087A1 (de) 1973-10-18
DE2317087B2 (de) 1976-11-04
JPS4917977A (hu) 1974-02-16

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