NL163064C - Halfgeleidergeheugeninrichting omvattende een samenge- stelde isolerende laag die een eerste isolerende laag van siliciumdioxyde en een op de eerste isolerende laag aangebrachte tweede isolerende laag met invangniveaux bevat. - Google Patents

Halfgeleidergeheugeninrichting omvattende een samenge- stelde isolerende laag die een eerste isolerende laag van siliciumdioxyde en een op de eerste isolerende laag aangebrachte tweede isolerende laag met invangniveaux bevat.

Info

Publication number
NL163064C
NL163064C NL7217144.A NL7217144A NL163064C NL 163064 C NL163064 C NL 163064C NL 7217144 A NL7217144 A NL 7217144A NL 163064 C NL163064 C NL 163064C
Authority
NL
Netherlands
Prior art keywords
insulating
coating
semi
memory device
silicon dioxide
Prior art date
Application number
NL7217144.A
Other languages
English (en)
Dutch (nl)
Other versions
NL7217144A (de
NL163064B (nl
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of NL7217144A publication Critical patent/NL7217144A/xx
Publication of NL163064B publication Critical patent/NL163064B/xx
Application granted granted Critical
Publication of NL163064C publication Critical patent/NL163064C/xx

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356008Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
NL7217144.A 1971-12-17 1972-12-15 Halfgeleidergeheugeninrichting omvattende een samenge- stelde isolerende laag die een eerste isolerende laag van siliciumdioxyde en een op de eerste isolerende laag aangebrachte tweede isolerende laag met invangniveaux bevat. NL163064C (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10308271A JPS4866943A (de) 1971-12-17 1971-12-17
JP10308371A JPS5144869B2 (de) 1971-12-17 1971-12-17

Publications (3)

Publication Number Publication Date
NL7217144A NL7217144A (de) 1973-06-19
NL163064B NL163064B (nl) 1980-02-15
NL163064C true NL163064C (nl) 1980-07-15

Family

ID=26443741

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7217144.A NL163064C (nl) 1971-12-17 1972-12-15 Halfgeleidergeheugeninrichting omvattende een samenge- stelde isolerende laag die een eerste isolerende laag van siliciumdioxyde en een op de eerste isolerende laag aangebrachte tweede isolerende laag met invangniveaux bevat.

Country Status (6)

Country Link
JP (2) JPS5144869B2 (de)
CA (1) CA1000404A (de)
DE (1) DE2261522C3 (de)
FR (1) FR2163682B1 (de)
GB (1) GB1391640A (de)
NL (1) NL163064C (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53150469U (de) * 1977-05-02 1978-11-27
JPS5484575U (de) * 1977-11-29 1979-06-15
JPS555478U (de) * 1978-06-26 1980-01-14
JPS617816U (ja) * 1984-06-19 1986-01-17 松下電器産業株式会社 押釦装置
JPH06326323A (ja) * 1993-05-14 1994-11-25 Nec Corp 不揮発性トンネルトランジスタおよびメモリ回路
US6303940B1 (en) 1999-01-26 2001-10-16 Agere Systems Guardian Corp. Charge injection transistor using high-k dielectric barrier layer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2791761A (en) * 1955-02-18 1957-05-07 Bell Telephone Labor Inc Electrical switching and storage
CA813537A (en) * 1967-10-17 1969-05-20 Joseph H. Scott, Jr. Semiconductor memory device

Also Published As

Publication number Publication date
NL7217144A (de) 1973-06-19
FR2163682A1 (de) 1973-07-27
FR2163682B1 (de) 1976-10-29
CA1000404A (en) 1976-11-23
DE2261522A1 (de) 1973-07-12
JPS4866943A (de) 1973-09-13
JPS5144869B2 (de) 1976-12-01
NL163064B (nl) 1980-02-15
JPS4866944A (de) 1973-09-13
DE2261522B2 (de) 1977-07-07
DE2261522C3 (de) 1982-03-04
GB1391640A (en) 1975-04-23

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Legal Events

Date Code Title Description
V4 Lapsed because of reaching the maxim lifetime of a patent