NL147884B - Werkwijze voor de vervaardiging van halfgeleiderinrichtingen met een vlak systeem van een of meer geleidende en isolerende lagen. - Google Patents

Werkwijze voor de vervaardiging van halfgeleiderinrichtingen met een vlak systeem van een of meer geleidende en isolerende lagen.

Info

Publication number
NL147884B
NL147884B NL707018740A NL7018740A NL147884B NL 147884 B NL147884 B NL 147884B NL 707018740 A NL707018740 A NL 707018740A NL 7018740 A NL7018740 A NL 7018740A NL 147884 B NL147884 B NL 147884B
Authority
NL
Netherlands
Prior art keywords
conductive
manufacture
semiconductor devices
insulating layers
flat system
Prior art date
Application number
NL707018740A
Other languages
English (en)
Other versions
NL7018740A (nl
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of NL7018740A publication Critical patent/NL7018740A/xx
Publication of NL147884B publication Critical patent/NL147884B/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
NL707018740A 1969-12-25 1970-12-23 Werkwijze voor de vervaardiging van halfgeleiderinrichtingen met een vlak systeem van een of meer geleidende en isolerende lagen. NL147884B (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP45001690A JPS4913914B1 (nl) 1969-12-25 1969-12-25

Publications (2)

Publication Number Publication Date
NL7018740A NL7018740A (nl) 1971-06-29
NL147884B true NL147884B (nl) 1975-11-17

Family

ID=11508499

Family Applications (1)

Application Number Title Priority Date Filing Date
NL707018740A NL147884B (nl) 1969-12-25 1970-12-23 Werkwijze voor de vervaardiging van halfgeleiderinrichtingen met een vlak systeem van een of meer geleidende en isolerende lagen.

Country Status (4)

Country Link
US (1) US3737340A (nl)
JP (1) JPS4913914B1 (nl)
GB (1) GB1333610A (nl)
NL (1) NL147884B (nl)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) * 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
US4005240A (en) * 1975-03-10 1977-01-25 Aeronutronic Ford Corporation Germanium device passivation
US4115799A (en) * 1977-01-26 1978-09-19 Westinghouse Electric Corp. Thin film copper transition between aluminum and indium copper films
JPS5678130A (en) * 1979-11-30 1981-06-26 Hitachi Ltd Semiconductor device and its manufacture
EP0166027B1 (de) * 1984-06-19 1990-06-13 Siemens Aktiengesellschaft In C-MOS-Technik realisierte Basiszelle
US4622576A (en) * 1984-10-22 1986-11-11 National Semiconductor Corporation Conductive non-metallic self-passivating non-corrodable IC bonding pads
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
DE10223359B4 (de) * 2002-05-25 2011-08-11 Robert Bosch GmbH, 70469 Mikromechanisches Bauteil und Verfahren zur Herstellung einer Anti-Haftschicht auf einem mikromechanischen Bauteil

Also Published As

Publication number Publication date
NL7018740A (nl) 1971-06-29
JPS4913914B1 (nl) 1974-04-03
DE2061209B2 (de) 1972-07-27
US3737340A (en) 1973-06-05
GB1333610A (en) 1973-10-10
DE2061209A1 (de) 1971-07-08

Similar Documents

Publication Publication Date Title
NL151560B (nl) Werkwijze voor het vervaardigen van een halfgeleiderinrichting voorzien van een isolerende glaslaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
NL152114B (nl) Werkwijze voor de vervaardiging van een meerlaagshalfgeleiderinrichting en met deze werkwijze vervaardigde halfgeleiderinrichting.
CA925224A (en) Semiconductor device and method of manufacturing the same
NL173907C (nl) Grondplaat met geleiderpatroon en werkwijze voor het vervaardigen daarvan.
NL161617C (nl) Halfgeleiderinrichting met vlak oppervlak en werkwijze voor het vervaardigen daarvan.
NL162246B (nl) Halfgeleiderinrichting met een halfgeleiderweerstand en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting.
NL169250C (nl) Keten voor het in een blokkerende toestand brengen van een in geleidende toestand verkerende stuurbare halfgeleidergelijkrichter met een halfgeleiderlichaam met vier lagen van afwisselend tegengesteld geleidingstype.
ES381370A1 (es) Un metodo de fabricar un dispositivo semiconductor.
NL157954B (nl) Werkwijze en inrichting voor het vervaardigen van een pooltapijt.
GB1343794A (en) Multilayer semiconductor devices
NL158325B (nl) Halfgeleiderinrichting, omvattende een halfgeleiderlichaam met een veelvoud van geleidende lagen, met een vooraf bepaald patroon van geleiders.
NL147884B (nl) Werkwijze voor de vervaardiging van halfgeleiderinrichtingen met een vlak systeem van een of meer geleidende en isolerende lagen.
NL168654B (nl) Halfgeleiderinrichting voorzien van een halfgeleider- lichaam van een eerste geleidingstype met een door dif- fusie gevormd oppervlaktegebied van een tweede gelei- dingstype.
NL164157C (nl) Geintegreerde halfgeleiderschakeling van het ladings- gekoppelde type en werkwijze voor het vervaardigen van een dergelijke halfgeleiderschakeling.
NL154866B (nl) Werkwijze voor het vervaardigen van een halfgeleiderinrichting alsmede halfgeleiderinrichting, vervaardigd volgens de werkwijze.
NL171759C (nl) Werkwijze ter vervaardiging van lichtemitterende halfgeleiderinrichtingen.
NL166171C (nl) Werkwijze voor het vervaardigen van, uit meerdere lagen opgebouwde, gedrukte schakelingen en inrichting ter realisering van deze werkwijze.
CA921611A (en) Optical-electronic semiconductor devices
IT971409B (it) Impianto di frenatura elettronico antislittamento
NL161613C (nl) Foto-elektrische geleiderinrichting en werkwijze voor het vervaardigen daarvan.
NL162420B (nl) Werkwijze voor het bekleden van een geleidend substraat.
CA918300A (en) Semiconductor device and method of manufacturing the device
IT960696B (it) Impianto elettronico di frenatura antislittamento
NL162512C (nl) Halfgeleiderinrichting en werkwijze voor de vervaar- diging ervan.
NL145096B (nl) Werkwijze voor het vervaardigen van een halfgeleiderstelsel en het met deze werkwijze verkregen halfgeleiderstelsel.

Legal Events

Date Code Title Description
V1 Lapsed because of non-payment of the annual fee
NL80 Information provided on patent owner name for an already discontinued patent

Owner name: FUJITSU