NL161302C - Werkwijze voor het vervaardigen van een halfgeleiderin- richting. - Google Patents

Werkwijze voor het vervaardigen van een halfgeleiderin- richting.

Info

Publication number
NL161302C
NL161302C NL7403940.A NL7403940A NL161302C NL 161302 C NL161302 C NL 161302C NL 7403940 A NL7403940 A NL 7403940A NL 161302 C NL161302 C NL 161302C
Authority
NL
Netherlands
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Application number
NL7403940.A
Other languages
English (en)
Other versions
NL7403940A (nl
NL161302B (nl
Inventor
Kousi Nomura
Satoru Kawazu
Yoshihiko Hirose
Isao Inoue
Yoshihiko Watari
Koichi Kijima
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3319173A external-priority patent/JPS5317390B2/ja
Priority claimed from JP3706473A external-priority patent/JPS5648980B2/ja
Priority claimed from JP5531073A external-priority patent/JPS5652453B2/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of NL7403940A publication Critical patent/NL7403940A/xx
Publication of NL161302B publication Critical patent/NL161302B/nl
Application granted granted Critical
Publication of NL161302C publication Critical patent/NL161302C/nl

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/416—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness
NL7403940.A 1973-03-23 1974-03-22 Werkwijze voor het vervaardigen van een halfgeleiderin- richting. NL161302C (nl)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3319173A JPS5317390B2 (nl) 1973-03-23 1973-03-23
JP3706473A JPS5648980B2 (nl) 1973-03-31 1973-03-31
JP5531073A JPS5652453B2 (nl) 1973-05-18 1973-05-18

Publications (3)

Publication Number Publication Date
NL7403940A NL7403940A (nl) 1974-09-25
NL161302B NL161302B (nl) 1979-08-15
NL161302C true NL161302C (nl) 1980-01-15

Family

ID=27287995

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7403940.A NL161302C (nl) 1973-03-23 1974-03-22 Werkwijze voor het vervaardigen van een halfgeleiderin- richting.

Country Status (6)

Country Link
US (1) US3966501A (nl)
DE (1) DE2414033C3 (nl)
FR (1) FR2222754B1 (nl)
GB (1) GB1469436A (nl)
IT (1) IT1007685B (nl)
NL (1) NL161302C (nl)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982262A (en) * 1974-04-17 1976-09-21 Karatsjuba Anatoly Prokofievic Semiconductor indicating instrument
JPS5197385A (en) * 1975-02-21 1976-08-26 Handotaisochino seizohoho
US4002511A (en) * 1975-04-16 1977-01-11 Ibm Corporation Method for forming masks comprising silicon nitride and novel mask structures produced thereby
US4179311A (en) * 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
IT1089298B (it) * 1977-01-17 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
US4098618A (en) * 1977-06-03 1978-07-04 International Business Machines Corporation Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
US4157268A (en) * 1977-06-16 1979-06-05 International Business Machines Corporation Localized oxidation enhancement for an integrated injection logic circuit
NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
DE2803431A1 (de) * 1978-01-26 1979-08-02 Siemens Ag Verfahren zur herstellung von mos-transistoren
US4282647A (en) * 1978-04-04 1981-08-11 Standard Microsystems Corporation Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask
US4148133A (en) * 1978-05-08 1979-04-10 Sperry Rand Corporation Polysilicon mask for etching thick insulator
JPS559414A (en) * 1978-07-05 1980-01-23 Toshiba Corp Manufacturing method of semiconductor device
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4170500A (en) * 1979-01-15 1979-10-09 Fairchild Camera And Instrument Corporation Process for forming field dielectric regions in semiconductor structures without encroaching on device regions
US4255207A (en) * 1979-04-09 1981-03-10 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4670769A (en) * 1979-04-09 1987-06-02 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
AT387474B (de) * 1980-12-23 1989-01-25 Philips Nv Verfahren zur herstellung einer halbleitervorrichtung
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
US4557036A (en) * 1982-03-31 1985-12-10 Nippon Telegraph & Telephone Public Corp. Semiconductor device and process for manufacturing the same
US4470190A (en) * 1982-11-29 1984-09-11 At&T Bell Laboratories Josephson device fabrication method
EP0126292B1 (en) * 1983-04-21 1987-12-02 Kabushiki Kaisha Toshiba Semiconductor device having an element isolation layer and method of manufacturing the same
US4615746A (en) * 1983-09-29 1986-10-07 Kenji Kawakita Method of forming isolated island regions in a semiconductor substrate by selective etching and oxidation and devices formed therefrom
US5008215A (en) * 1989-07-07 1991-04-16 Industrial Technology Research Institute Process for preparing high sensitivity semiconductive magnetoresistance element
JP2726502B2 (ja) * 1989-08-10 1998-03-11 株式会社東芝 半導体装置の製造方法
US6780718B2 (en) 1993-11-30 2004-08-24 Stmicroelectronics, Inc. Transistor structure and method for making same
TW344897B (en) * 1994-11-30 1998-11-11 At&T Tcorporation A process for forming gate oxides possessing different thicknesses on a semiconductor substrate
US5780347A (en) * 1996-05-20 1998-07-14 Kapoor; Ashok K. Method of forming polysilicon local interconnects
US7060581B2 (en) * 2003-10-09 2006-06-13 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device
WO2005062365A1 (en) * 2003-12-04 2005-07-07 Bae Systems Information And Electronic Systems Integration, Inc. Gan-based permeable base transistor and method of fabrication
JP2008147576A (ja) * 2006-12-13 2008-06-26 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JPWO2012098759A1 (ja) * 2011-01-17 2014-06-09 住友電気工業株式会社 炭化珪素半導体装置の製造方法
TWI588918B (zh) * 2014-04-01 2017-06-21 亞太優勢微系統股份有限公司 具精確間隙機電晶圓結構與及其製作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915377B1 (nl) * 1968-10-04 1974-04-15
US3575745A (en) * 1969-04-02 1971-04-20 Bryan H Hill Integrated circuit fabrication
US3748187A (en) * 1971-08-03 1973-07-24 Hughes Aircraft Co Self-registered doped layer for preventing field inversion in mis circuits

Also Published As

Publication number Publication date
DE2414033A1 (de) 1974-10-03
US3966501A (en) 1976-06-29
NL7403940A (nl) 1974-09-25
DE2414033B2 (de) 1977-06-23
IT1007685B (it) 1976-10-30
FR2222754A1 (nl) 1974-10-18
DE2414033C3 (de) 1979-08-09
NL161302B (nl) 1979-08-15
GB1469436A (en) 1977-04-06
FR2222754B1 (nl) 1978-01-06

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Legal Events

Date Code Title Description
NL80 Information provided on patent owner name for an already discontinued patent

Owner name: MITSUB DENKI

V4 Discontinued because of reaching the maximum lifetime of a patent