MXPA04002479A - Limitador programable de ancho de banda con el uso de supresion de acuerdo inicial. - Google Patents

Limitador programable de ancho de banda con el uso de supresion de acuerdo inicial.

Info

Publication number
MXPA04002479A
MXPA04002479A MXPA04002479A MXPA04002479A MXPA04002479A MX PA04002479 A MXPA04002479 A MX PA04002479A MX PA04002479 A MXPA04002479 A MX PA04002479A MX PA04002479 A MXPA04002479 A MX PA04002479A MX PA04002479 A MXPA04002479 A MX PA04002479A
Authority
MX
Mexico
Prior art keywords
handshake
signal
reset signal
generate
suppression
Prior art date
Application number
MXPA04002479A
Other languages
English (en)
Inventor
Leon Simpson David
Original Assignee
Thomson Licensing Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa filed Critical Thomson Licensing Sa
Publication of MXPA04002479A publication Critical patent/MXPA04002479A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/4013—Management of data rate on the bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

Un aparato (62) para limitar el ancho de banda de transferencia de datos mediante la supresion de acuerdo inicial, el cual esta configurado para generar una primera senal de reinicio, generar una segunda senal de reinicio, un numero predeterminado de ciclos de reloj despues de generar una primera senal de reinicio, generar una cuenta de acuerdo inicial que representa un numero de recepciones, entre la primera senal de reinicio y la segunda senal de reinicio de una primera senal de acuerdo inicial Lista para enviar (RTS) y una primera senal de acuerdo inicial Lista para recibir (RTR), y deshabilitar la segunda senal de acuerdo inicial RTR y la primera senal de acuerdo inicial RTS con base en una comparacion de la cuenta de acuerdo inicial y un valor maximo.
MXPA04002479A 2001-09-19 2002-09-19 Limitador programable de ancho de banda con el uso de supresion de acuerdo inicial. MXPA04002479A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32327201P 2001-09-19 2001-09-19
PCT/US2002/029755 WO2003034194A1 (en) 2001-09-19 2002-09-19 Programmable bandwidth limiter using handshake suppression

Publications (1)

Publication Number Publication Date
MXPA04002479A true MXPA04002479A (es) 2004-05-31

Family

ID=23258446

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA04002479A MXPA04002479A (es) 2001-09-19 2002-09-19 Limitador programable de ancho de banda con el uso de supresion de acuerdo inicial.

Country Status (9)

Country Link
US (1) US6839779B2 (es)
EP (1) EP1428109B1 (es)
JP (1) JP4009594B2 (es)
KR (1) KR100903905B1 (es)
CN (1) CN100392561C (es)
BR (1) BR0212570A (es)
DE (1) DE60229863D1 (es)
MX (1) MXPA04002479A (es)
WO (1) WO2003034194A1 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7822009B2 (en) * 2005-05-09 2010-10-26 Industrial Technology Research Institute Distributed medium access protocol for wireless mesh networks
EP1960903A4 (en) * 2005-11-28 2009-01-28 Commvault Systems Inc SYSTEMS AND METHOD FOR CLASSIFICATION AND TRANSFER OF INFORMATION IN A STORAGE NETWORK
CN101430645B (zh) * 2007-11-06 2012-07-04 上海摩波彼克半导体有限公司 基于计算机实现数据卡软件下载和升级的方法
US8578078B1 (en) * 2008-03-21 2013-11-05 Altera Corporation Valid latency for programmable chip components
CN110381596B (zh) * 2019-09-02 2023-04-18 北京百佑科技有限公司 点对点无线通信控制方法、装置、终端及可读存储介质

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873703A (en) * 1985-09-27 1989-10-10 Hewlett-Packard Company Synchronizing system
JPH0744567B2 (ja) * 1986-08-27 1995-05-15 日産自動車株式会社 通信インタ−フエイス装置
JPH077375B2 (ja) * 1988-06-17 1995-01-30 日本電気株式会社 バス制御方式
AU7453491A (en) * 1990-03-29 1991-10-21 Sf2 Corporation Method and apparatus for scheduling access to a csma communication medium
US5485455A (en) * 1994-01-28 1996-01-16 Cabletron Systems, Inc. Network having secure fast packet switching and guaranteed quality of service
US5619544A (en) * 1994-06-03 1997-04-08 Texas Instruments Incorporated Universal asynchronous receive/transmit circuit with flow control
US5862352A (en) * 1997-02-06 1999-01-19 Lsi Logic Corporation Variable period and assertion width REQ/ACK pulse generator for synchronous SCSI data transfers
US5881248A (en) * 1997-03-06 1999-03-09 Advanced Micro Devices, Inc. System and method for optimizing system bus bandwidth in an embedded communication system
US6105083A (en) * 1997-06-20 2000-08-15 Avid Technology, Inc. Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements
JPH1155084A (ja) * 1997-07-29 1999-02-26 Matsushita Electric Works Ltd 出力遅延回路
JPH1185632A (ja) * 1997-09-12 1999-03-30 Hitachi Ltd データ通信方法
KR100257712B1 (ko) * 1997-12-31 2000-06-01 서평원 인터넷을 이용한 프로세스 간의 정보교환 장치
JPH11250005A (ja) * 1998-03-05 1999-09-17 Nec Corp バス制御方法、バス制御装置及びバス制御プログラムを記憶した記憶媒体
US6141691A (en) 1998-04-03 2000-10-31 Avid Technology, Inc. Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements
US6415347B1 (en) * 1999-06-30 2002-07-02 Adaptec, Inc. Hardware attention management circuit and method for parallel SCSI host adapters
US6363444B1 (en) * 1999-07-15 2002-03-26 3Com Corporation Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory
US6438633B1 (en) * 2000-04-20 2002-08-20 Sony Corporation System for providing deterministic performance from a non-deterministic device

Also Published As

Publication number Publication date
CN100392561C (zh) 2008-06-04
BR0212570A (pt) 2004-10-13
JP4009594B2 (ja) 2007-11-14
US6839779B2 (en) 2005-01-04
DE60229863D1 (de) 2008-12-24
EP1428109A4 (en) 2006-05-24
WO2003034194A1 (en) 2003-04-24
EP1428109A1 (en) 2004-06-16
EP1428109B1 (en) 2008-11-12
KR20040041162A (ko) 2004-05-14
JP2005506015A (ja) 2005-02-24
US20040236882A1 (en) 2004-11-25
KR100903905B1 (ko) 2009-06-19
CN1556945A (zh) 2004-12-22

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