MX376908B - Transmisor y metodo de permutacion de paridad del mismo. - Google Patents
Transmisor y metodo de permutacion de paridad del mismo.Info
- Publication number
- MX376908B MX376908B MX2017011153A MX2017011153A MX376908B MX 376908 B MX376908 B MX 376908B MX 2017011153 A MX2017011153 A MX 2017011153A MX 2017011153 A MX2017011153 A MX 2017011153A MX 376908 B MX376908 B MX 376908B
- Authority
- MX
- Mexico
- Prior art keywords
- bit groups
- group
- parity
- wise
- parity bits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
Se proporciona un transmisor. El transmisor incluye: Un codificador de Comprobación de Paridad de Baja Densidad (LDPC) configurado para codificar bits de entrada para generar bits de paridad; un permutador de paridad configurado para intercalar a nivel de grupo una pluralidad de grupos de bits incluyendo los bits de paridad; y una perforadora configurada para seleccionar algunos de los bits de paridad en los grupos de bits intercalados a nivel de grupo y perforar los bits de paridad seleccionados, en donde el permutador de paridad intercala a nivel de grupo los grupos de bits de modo que algunos de los grupos de bits en posiciones predeterminadas en los grupos de bits antes de la intercalación a nivel de grupo quedan colocados en serie después de la intercalación a nivel de grupo y un resto de los grupos de bits antes de la intercalación a nivel de grupo quedan colocados sin un orden después de la intercalación a nivel de grupo de modo que la perforadora selecciona bits de paridad incluidos en algunos de los grupos de bits en secuencia y selecciona bits de paridad incluidos en el resto de los grupos de bits sin un orden.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562127014P | 2015-03-02 | 2015-03-02 | |
| KR1020150137188A KR102426780B1 (ko) | 2015-03-02 | 2015-09-27 | 송신 장치 및 그의 패리티 퍼뮤테이션 방법 |
| PCT/KR2016/002091 WO2016140513A1 (en) | 2015-03-02 | 2016-03-02 | Transmitter and parity permutation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| MX2017011153A MX2017011153A (es) | 2017-11-09 |
| MX376908B true MX376908B (es) | 2025-03-07 |
Family
ID=56950313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2017011153A MX376908B (es) | 2015-03-02 | 2016-03-02 | Transmisor y metodo de permutacion de paridad del mismo. |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR102426780B1 (es) |
| CN (1) | CN107567692B (es) |
| CA (1) | CA2978535C (es) |
| MX (1) | MX376908B (es) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN121079947A (zh) * | 2023-05-16 | 2025-12-05 | 高通股份有限公司 | 用于低功率设备的发射机结构 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7706455B2 (en) * | 2005-09-26 | 2010-04-27 | Intel Corporation | Multicarrier transmitter for multiple-input multiple-output communication systems and methods for puncturing bits for pilot tones |
| KR101503058B1 (ko) * | 2008-02-26 | 2015-03-18 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치 |
| CN101807966B (zh) * | 2009-02-13 | 2012-12-12 | 瑞昱半导体股份有限公司 | 奇偶校验码解码器及接收系统 |
| ES2749970T3 (es) * | 2010-05-11 | 2020-03-24 | Electronics & Telecommunications Res Inst | Método de transmisión de información de rango de canal de enlace descendente a través de un canal compartido de enlace ascendente físico |
| KR20150005426A (ko) * | 2013-07-05 | 2015-01-14 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
| KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
-
2015
- 2015-09-27 KR KR1020150137188A patent/KR102426780B1/ko active Active
-
2016
- 2016-03-02 CA CA2978535A patent/CA2978535C/en active Active
- 2016-03-02 MX MX2017011153A patent/MX376908B/es active IP Right Grant
- 2016-03-02 CN CN201680025662.1A patent/CN107567692B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| MX2017011153A (es) | 2017-11-09 |
| CN107567692B (zh) | 2020-09-04 |
| CA2978535C (en) | 2023-10-17 |
| CN107567692A (zh) | 2018-01-09 |
| KR102426780B1 (ko) | 2022-07-29 |
| CA2978535A1 (en) | 2016-09-09 |
| KR20160106476A (ko) | 2016-09-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FG | Grant or registration |