MX2017016202A - Asignacion de bloques de instruccion en ventanas de instruccion basandose en el tamaño de bloque. - Google Patents

Asignacion de bloques de instruccion en ventanas de instruccion basandose en el tamaño de bloque.

Info

Publication number
MX2017016202A
MX2017016202A MX2017016202A MX2017016202A MX2017016202A MX 2017016202 A MX2017016202 A MX 2017016202A MX 2017016202 A MX2017016202 A MX 2017016202A MX 2017016202 A MX2017016202 A MX 2017016202A MX 2017016202 A MX2017016202 A MX 2017016202A
Authority
MX
Mexico
Prior art keywords
instruction
block
blocks
size table
mapping
Prior art date
Application number
MX2017016202A
Other languages
English (en)
Inventor
Smith Aaron
C Burger Douglas
Gray Jan
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of MX2017016202A publication Critical patent/MX2017016202A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Digital Computer Display Output (AREA)
  • Image Analysis (AREA)

Abstract

Un núcleo de procesador en una microarquitectura basada en bloque de instrucción utiliza bloques de instrucción que tienen encabezados que incluyen un índice para un cuadro de tamaño que puede expresarse utilizando uno de memoria, registro, lógica o secuencia de código. Una unidad de control en el núcleo de procesador determina cuántas instrucciones hay que extraer para un bloque de instrucción actual para asignación a una ventana de instrucción basándose en el tamaño de bloque que se indica a partir del cuadro de tamaño. Ya que los tamaños de bloque de instrucción están desigualmente distribuidos para un programa dado, la utilización del cuadro de tamaño permite mayor flexibilidad para hacer coincidir los bloques de instrucción con los tamaños de ranuras disponibles en la ventana de instrucción según comparado con arreglos en donde los bloques de instrucción tienen un tamaño fijo o se dimensionan con menos granularidad. Dicha flexibilidad puede permitir un empaquetado de instrucción más denso que incrementa toda la eficiencia al reducir el número de nops (no operaciones, tal como funciones nulas) en un bloque de instrucción dado.
MX2017016202A 2015-06-26 2016-06-23 Asignacion de bloques de instruccion en ventanas de instruccion basandose en el tamaño de bloque. MX2017016202A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/752,768 US9952867B2 (en) 2015-06-26 2015-06-26 Mapping instruction blocks based on block size
PCT/US2016/038849 WO2016210026A1 (en) 2015-06-26 2016-06-23 Mapping instruction blocks into instruction windows based on block size

Publications (1)

Publication Number Publication Date
MX2017016202A true MX2017016202A (es) 2018-03-01

Family

ID=56511878

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2017016202A MX2017016202A (es) 2015-06-26 2016-06-23 Asignacion de bloques de instruccion en ventanas de instruccion basandose en el tamaño de bloque.

Country Status (16)

Country Link
US (1) US9952867B2 (es)
EP (1) EP3314405A1 (es)
JP (1) JP2018519597A (es)
KR (1) KR102575938B1 (es)
CN (1) CN107771318B (es)
AU (1) AU2016281598A1 (es)
BR (1) BR112017024335A2 (es)
CA (1) CA2985495A1 (es)
CL (1) CL2017003264A1 (es)
CO (1) CO2017013251A2 (es)
HK (1) HK1246430A1 (es)
IL (1) IL256176A (es)
MX (1) MX2017016202A (es)
PH (1) PH12017550125A1 (es)
TW (1) TW201717021A (es)
WO (1) WO2016210026A1 (es)

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US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US9940136B2 (en) 2015-06-26 2018-04-10 Microsoft Technology Licensing, Llc Reuse of decoded instructions
US9952867B2 (en) * 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US9720693B2 (en) * 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US10346168B2 (en) * 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US10095519B2 (en) 2015-09-19 2018-10-09 Microsoft Technology Licensing, Llc Instruction block address register
CN110750856B (zh) * 2019-09-06 2023-06-06 东南大学 一种基于机器学习的有效指令窗口大小评估方法

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