MX169964B - Instalacion para sincronizacion rapida de marco y fase - Google Patents

Instalacion para sincronizacion rapida de marco y fase

Info

Publication number
MX169964B
MX169964B MX011733A MX1173388A MX169964B MX 169964 B MX169964 B MX 169964B MX 011733 A MX011733 A MX 011733A MX 1173388 A MX1173388 A MX 1173388A MX 169964 B MX169964 B MX 169964B
Authority
MX
Mexico
Prior art keywords
derived
values
oscillation
post
oscillations
Prior art date
Application number
MX011733A
Other languages
English (en)
Inventor
Kalman Zsechenyi
Original Assignee
Alcatel Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Nv filed Critical Alcatel Nv
Publication of MX169964B publication Critical patent/MX169964B/es

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0054Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0058Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0602Systems characterised by the synchronising information used
    • H04J3/0605Special codes used as synchronising signal
    • H04J3/0608Detectors therefor, e.g. correlators, state machines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Communication Control (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

La presente invención se refiere a la instalación para sincronización de marco en el extremo receptor y para sincronización de la fase del reloj de muestreo en el extremo receptor con la fase de reloj de una corriente de caracteres recibida a través de una trayectoria de transmisión y que contiene una palabra única a intervalo de tiempos regulares, que comprende un correlacionador digital para formar una función de correlación transversal a partir de la corriente de caracteres recibida, muestreada a la velocidad de repetición de reloj de muestreo, y, la palabra única almacenada en el extremo receptor, un circuito de detección de marco para determinar el reloj de marco ubicando las máximas de la función de correlación transversal que recurren a intervalos de interior de un período de marco, un circuito de sincronización de fase que derive información de control para ajustar la fase del reloj de muestreo a partir de valores de la función de correlación transversal en la cercanía del máximo recurrente detectado y ajusta la fase con el mismo y, un elemento de decisión para regenerar los caracteres, caracterizada en que se proporciona una unidad de evaluación que determina los valores de corrección a partir de los caracteres regenerados y a partir de coeficientes de transmisión de la trayectoria de transmisión y, que corrige con los mismos los valores usados para derivar la información de control y, en que los valores de corrección toman en cuenta la influencias ocasionadas por preoscilaciones y pososcilaciones de caracteres que preceden y siguen a la palabra única.
MX011733A 1987-06-12 1988-06-01 Instalacion para sincronizacion rapida de marco y fase MX169964B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19873719659 DE3719659A1 (de) 1987-06-12 1987-06-12 Einrichtung zur schnellen rahmen- und phasensynchronisation

Publications (1)

Publication Number Publication Date
MX169964B true MX169964B (es) 1993-08-03

Family

ID=6329580

Family Applications (1)

Application Number Title Priority Date Filing Date
MX011733A MX169964B (es) 1987-06-12 1988-06-01 Instalacion para sincronizacion rapida de marco y fase

Country Status (11)

Country Link
US (1) US4878229A (es)
EP (1) EP0294713B1 (es)
JP (1) JPH0691521B2 (es)
KR (1) KR960007403B1 (es)
CN (1) CN1009410B (es)
AT (1) ATE95356T1 (es)
AU (1) AU592935B2 (es)
CA (1) CA1299680C (es)
DE (2) DE3719659A1 (es)
ES (1) ES2046238T3 (es)
MX (1) MX169964B (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2531272B2 (ja) * 1988-08-11 1996-09-04 日本電気株式会社 フレ―ム同期制御方式
DE3832946A1 (de) * 1988-09-28 1990-04-05 Siemens Ag Verfahren zur verschluesselung digitaler zeitmultiplexsignale
ATE110507T1 (de) * 1988-09-29 1994-09-15 Siemens Ag Schaltungsanordnung zum entzerren von in analoger form empfangener digitalsignale.
US5539751A (en) * 1992-03-31 1996-07-23 The Commonwealth Of Australia Of C/-The Secretary Of Defence Demultiplexer synchronizer
AU668149B2 (en) * 1992-03-31 1996-04-26 Commonwealth Of Australia, The Demultiplexer synchroniser
US6324225B1 (en) * 1997-12-22 2001-11-27 Stmicroelectronics, Inc. Timing recovery for data sampling of a detector
US6363129B1 (en) * 1998-11-09 2002-03-26 Broadcom Corporation Timing recovery system for a multi-pair gigabit transceiver
US6804317B2 (en) * 2002-01-04 2004-10-12 Intel Corporation Digital frame determination method and apparatus
US7349507B2 (en) * 2003-06-09 2008-03-25 Intel Corporation Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit
US7924952B2 (en) * 2004-05-20 2011-04-12 Panasonic Corporation Signal detection device, signal detection circuit, signal detection method, and program
CN101594180B (zh) * 2009-06-30 2012-12-19 北京华力创通科技股份有限公司 接收机的电文的位同步和帧同步实现方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2478914B1 (fr) * 1980-03-19 1986-01-31 Ibm France Procede et dispositif pour l'ajustement initial de l'horloge d'un recepteur de donnees synchrone
JPS5840386A (ja) * 1981-06-30 1983-03-09 ユニオン・カ−バイド・コ−ポレ−シヨン 高硫黄デカントオイルから低硫黄高品位コ−クスを製造する方法
DE3201934A1 (de) * 1982-01-22 1983-08-04 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt System zur uebertragung von digitalen informatonssignalen
DE3227151C2 (de) * 1982-07-21 1986-04-17 Standard Elektrik Lorenz Ag, 7000 Stuttgart Einrichtung zur empfangsseitigen Phasensynchronisation des Abtasttaktes auf die Phasenlage der Zeichen eines empfangenen Zeitmultiplex-Zeichenstroms
DE3333714A1 (de) * 1983-09-17 1985-04-04 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zur rahmen- und phasensynchronisation eines empfangsseitigen abtasttaktes
JPH0681167B2 (ja) * 1984-07-28 1994-10-12 富士通株式会社 ディジタル無線通信用の受信装置
US4627080A (en) * 1984-11-23 1986-12-02 At&T Bell Laboratories Adaptive timing circuit

Also Published As

Publication number Publication date
JPS63318840A (ja) 1988-12-27
KR890001320A (ko) 1989-03-20
DE3884465D1 (de) 1993-11-04
KR960007403B1 (ko) 1996-05-31
DE3719659A1 (de) 1988-12-29
CN88103487A (zh) 1988-12-28
AU592935B2 (en) 1990-01-25
ES2046238T3 (es) 1994-02-01
ATE95356T1 (de) 1993-10-15
JPH0691521B2 (ja) 1994-11-14
CA1299680C (en) 1992-04-28
EP0294713B1 (de) 1993-09-29
US4878229A (en) 1989-10-31
CN1009410B (zh) 1990-08-29
EP0294713A3 (en) 1990-05-09
AU1675788A (en) 1988-12-15
EP0294713A2 (de) 1988-12-14

Similar Documents

Publication Publication Date Title
MX169964B (es) Instalacion para sincronizacion rapida de marco y fase
DE3269514D1 (en) Apparatus for selectively compensating burst errors of variable length in successive data words
DE3166703D1 (en) Circuit for correcting the distortion of read signals from a pcm transmission apparatus, particularly from a digital audio disc
GB1248639A (en) Data transmission method and system
ES538240A0 (es) Un metodo de corregir valores erroneos de muestras de una senal muestreada equidistantemente mediante interpolacion.
JPS5596748A (en) Adaptive signal discrimination unit
KR870001725A (ko) 비데오신호 처리장치
DK394281A (da) Fremgangsmaade til fremstilling af et antibiotikum bmg 162-af2.
AU631077B2 (en) Method and apparatus for adaptively retiming and regenerating digital pulse signals
JPS53122078A (en) Position controlling method
DK557084D0 (da) Apparat til fremfoering af en genstand med frit haengende, traadformedefremspring, f.eks. en fiskeline med forfang
DE3369045D1 (en) Adaptive auto-orthogonalising equalisation system in the discrete frequency domain, and equaliser for effecting the system
SE7908626L (sv) Korrektionskrets for samplingsklocka
JPS5437617A (en) Error correcting method
JPS59182643A (ja) 自動レベル制御回路
DE3231768A1 (de) Entzerrer mit adaptiver quantisierter rueckkopplung
JP2792077B2 (ja) 補助伝送信号誤り訂正回路
JPH0221751A (ja) バイアス歪を測定及び解消する配置
IT1071212B (it) Procedimento e dispositivo per la equalizzazione non lineare di segnali numerici
IT1078647B (it) Procedimento e dispositivo per l'equalizzazione non lineare di segnali numerici
JPS5343456A (en) Automatic equalizer
PETROVA Collocation by a least-squares method and the estimation of parameters with errors in initial data
JPS53136808A (en) Distortion compensating system of video signal
Dworak Forty Eclipsing Binaries Probably Within 100 ps from the Sun with Unknown Trigonometric Parallaxes
IT1118072B (it) Procedimento e dispositivo per l equalizzazione non lineare di segnali numerici