ES2046238T3 - Equipo para la sincronizacion rapida de trama y de fase. - Google Patents

Equipo para la sincronizacion rapida de trama y de fase.

Info

Publication number
ES2046238T3
ES2046238T3 ES198888108867T ES88108867T ES2046238T3 ES 2046238 T3 ES2046238 T3 ES 2046238T3 ES 198888108867 T ES198888108867 T ES 198888108867T ES 88108867 T ES88108867 T ES 88108867T ES 2046238 T3 ES2046238 T3 ES 2046238T3
Authority
ES
Spain
Prior art keywords
derived
values
oscillation
post
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198888108867T
Other languages
English (en)
Inventor
Kalman Szechenyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Deutschland AG
Original Assignee
Alcatel SEL AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SEL AG filed Critical Alcatel SEL AG
Application granted granted Critical
Publication of ES2046238T3 publication Critical patent/ES2046238T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Communication Control (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

EL PRESENTE INVENTO NECESITA LOS SIGUIENTE CONCEPTOS BASICOS: LA CONSIGNA MARCO RK RECIBIDA CONTIENE TANTO LA TECLA MARCO RT COMO TAMBIEN LA TECHA DE INDICACION ZT. EN EL RECORRIDO DE TRANSMISION SE DISTORSIONA LA CONSIGNA MARCO EN UN MODO MUY DETERMINADO. EXPLORANDO ESTA CONSIGNA MARCO DISTORSIONADA CON UNA TECLA DE EXPLORACION AFECTADA DE ERROR FASICO PUEDE DETERMINARSE EL ERROR FASICO DEL VALOR EXPLORADO. LAS INDICACIONES QUE SE DERIVAN Y SIGUEN A LA CONSIGNA MARCO FORMAN DURANTE LA DISTORSION EN EL RECORRIDO DE TRANSMISION OSCILACIONES ANTERIORES Y POSTERIORES QUE SE SOBREPONEN A LA CONSIGNA MARCO Y DIFICULTAN SU VALORACION. A NIVEL DE LA TECNICA ESTAS OSICLACIONES ANTERIORES Y POSTERIORES SE CONSIDERAN POR FORMACION DE VALOR MEDIO SOBRE VARIOS MARCOS. SEGUN LOS CONCEPTOS BASICOS DEL INVENTO LOS VALORES DE ESTAS OSCILACIONES ANTERIORES Y POSTERIORES SE CALCULAN HACIA LOS PUNTOS TEMPORALES DE EXPLORACION Y SE RESTAN COMO VALORES DE CORRECCION DE LOS VALORES DE EXPLORACION MEDIDOS DEMODO QUE SOLAMENTE PERMANEZCA LA INFLUENCIA DE LA CONSIGNA MARCO DISTORSIONADA. YA DE LA PRIMERA CONSIGNA MARCO CONOCIDA SE OBTIENE UNA TAL INFORMACION IMPOSITIVA UTILIZABLE PARA AJUSTE DE LA FASE DE LA TECLA DE EXPLORACION. DE MODO VENTAJOSO NO SE CORRIGEN SOLAMENTE LOS VALORES DE EXPLORACION SINO LOS TAMAÑOS DERIVADOS DE ELLOS POR LOS VALORES DE CORRECCION (DERIVADOS). LAS OSCILACIONES ANTERIORES Y POSTERIORES SE OBTIENEN DE LAS INDICACIONES REGENERADAS MEDIANTE EL COEFICIENTE DE TRANSMISION CK DEL RECORRIDO DE TRANSMISION. LOS COEFICIENTES DE TRANSMISION SE PRETENDEN O BIEN FIJOS O DERIVADOS DEL COEFICIENTE DE DISTORSION CK DE UNA DISTORSION ADAPTADA.
ES198888108867T 1987-06-12 1988-06-03 Equipo para la sincronizacion rapida de trama y de fase. Expired - Lifetime ES2046238T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19873719659 DE3719659A1 (de) 1987-06-12 1987-06-12 Einrichtung zur schnellen rahmen- und phasensynchronisation

Publications (1)

Publication Number Publication Date
ES2046238T3 true ES2046238T3 (es) 1994-02-01

Family

ID=6329580

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198888108867T Expired - Lifetime ES2046238T3 (es) 1987-06-12 1988-06-03 Equipo para la sincronizacion rapida de trama y de fase.

Country Status (11)

Country Link
US (1) US4878229A (es)
EP (1) EP0294713B1 (es)
JP (1) JPH0691521B2 (es)
KR (1) KR960007403B1 (es)
CN (1) CN1009410B (es)
AT (1) ATE95356T1 (es)
AU (1) AU592935B2 (es)
CA (1) CA1299680C (es)
DE (2) DE3719659A1 (es)
ES (1) ES2046238T3 (es)
MX (1) MX169964B (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2531272B2 (ja) * 1988-08-11 1996-09-04 日本電気株式会社 フレ―ム同期制御方式
DE3832946A1 (de) * 1988-09-28 1990-04-05 Siemens Ag Verfahren zur verschluesselung digitaler zeitmultiplexsignale
ATE110507T1 (de) * 1988-09-29 1994-09-15 Siemens Ag Schaltungsanordnung zum entzerren von in analoger form empfangener digitalsignale.
US5539751A (en) * 1992-03-31 1996-07-23 The Commonwealth Of Australia Of C/-The Secretary Of Defence Demultiplexer synchronizer
AU668149B2 (en) * 1992-03-31 1996-04-26 Commonwealth Of Australia, The Demultiplexer synchroniser
US6324225B1 (en) * 1997-12-22 2001-11-27 Stmicroelectronics, Inc. Timing recovery for data sampling of a detector
US6363129B1 (en) * 1998-11-09 2002-03-26 Broadcom Corporation Timing recovery system for a multi-pair gigabit transceiver
US6804317B2 (en) * 2002-01-04 2004-10-12 Intel Corporation Digital frame determination method and apparatus
US7349507B2 (en) * 2003-06-09 2008-03-25 Intel Corporation Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit
US7924952B2 (en) * 2004-05-20 2011-04-12 Panasonic Corporation Signal detection device, signal detection circuit, signal detection method, and program
CN101594180B (zh) * 2009-06-30 2012-12-19 北京华力创通科技股份有限公司 接收机的电文的位同步和帧同步实现方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2478914B1 (fr) * 1980-03-19 1986-01-31 Ibm France Procede et dispositif pour l'ajustement initial de l'horloge d'un recepteur de donnees synchrone
JPS5840386A (ja) * 1981-06-30 1983-03-09 ユニオン・カ−バイド・コ−ポレ−シヨン 高硫黄デカントオイルから低硫黄高品位コ−クスを製造する方法
DE3201934A1 (de) * 1982-01-22 1983-08-04 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt System zur uebertragung von digitalen informatonssignalen
DE3227151C2 (de) * 1982-07-21 1986-04-17 Standard Elektrik Lorenz Ag, 7000 Stuttgart Einrichtung zur empfangsseitigen Phasensynchronisation des Abtasttaktes auf die Phasenlage der Zeichen eines empfangenen Zeitmultiplex-Zeichenstroms
DE3333714A1 (de) * 1983-09-17 1985-04-04 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zur rahmen- und phasensynchronisation eines empfangsseitigen abtasttaktes
JPH0681167B2 (ja) * 1984-07-28 1994-10-12 富士通株式会社 ディジタル無線通信用の受信装置
US4627080A (en) * 1984-11-23 1986-12-02 At&T Bell Laboratories Adaptive timing circuit

Also Published As

Publication number Publication date
JPS63318840A (ja) 1988-12-27
KR890001320A (ko) 1989-03-20
DE3884465D1 (de) 1993-11-04
MX169964B (es) 1993-08-03
KR960007403B1 (ko) 1996-05-31
DE3719659A1 (de) 1988-12-29
CN88103487A (zh) 1988-12-28
AU592935B2 (en) 1990-01-25
ATE95356T1 (de) 1993-10-15
JPH0691521B2 (ja) 1994-11-14
CA1299680C (en) 1992-04-28
EP0294713B1 (de) 1993-09-29
US4878229A (en) 1989-10-31
CN1009410B (zh) 1990-08-29
EP0294713A3 (en) 1990-05-09
AU1675788A (en) 1988-12-15
EP0294713A2 (de) 1988-12-14

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