LU101371B1 - Terahertz detector based on NxM DRA array and NxM NMOSFET array and antenna design method - Google Patents
Terahertz detector based on NxM DRA array and NxM NMOSFET array and antenna design method Download PDFInfo
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- LU101371B1 LU101371B1 LU101371A LU101371A LU101371B1 LU 101371 B1 LU101371 B1 LU 101371B1 LU 101371 A LU101371 A LU 101371A LU 101371 A LU101371 A LU 101371A LU 101371 B1 LU101371 B1 LU 101371B1
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000000903 blocking effect Effects 0.000 claims abstract description 24
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 230000005540 biological transmission Effects 0.000 claims description 33
- 239000010410 layer Substances 0.000 claims description 28
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000004088 simulation Methods 0.000 claims description 9
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 230000005284 excitation Effects 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000005672 electromagnetic field Effects 0.000 claims description 4
- 238000005457 optimization Methods 0.000 claims description 4
- 238000012938 design process Methods 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000395 magnesium oxide Substances 0.000 claims description 3
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000001902 propagating effect Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 abstract description 18
- 230000035945 sensitivity Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005855 radiation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
- G01J1/46—Electric circuits using a capacitor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/28—Investigating the spectrum
- G01J3/42—Absorption spectrometry; Double beam spectrometry; Flicker spectrometry; Reflection spectrometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/48—Earthing means; Earth screens; Counterpoises
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q13/00—Waveguide horns or mouths; Slot antennas; Leaky-waveguide antennas; Equivalent structures causing radiation along the transmission path of a guided wave
- H01Q13/10—Resonant slot antennas
- H01Q13/18—Resonant slot antennas the slot being backed by, or formed in boundary wall of, a resonant cavity ; Open cavity antennas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0006—Particular feeding systems
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0006—Particular feeding systems
- H01Q21/0075—Stripline fed arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
- H01Q21/064—Two dimensional planar arrays using horn or slot aerials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0485—Dielectric resonator antennas
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/90—Non-optical transmission systems, e.g. transmission systems employing non-photonic corpuscular radiation
Abstract
The present invention discloses a terahertz detector based on an NxM DRA array and an NxM NMOSFET array, comprising a NxM on-chip DRA array, a matching network MN, an NxM NMOSFET array, a first DC blocking capacitor, a low noise preamplifier and a voltage feedback loop that are sequentially connected, a second bias resistor and a second bias voltage connected thereto being provided between the first DC blocking capacitor and the low noise preamplifier. The present invention also proposes an antenna design method. Compared with the prior art, the technical solution of the present invention can cause the terahertz detector based on the NxM NMOSFET array detection to achieve higher detection sensitivity.
Description
| 1 BL-5108 LU101371 TERAHERTZ DETECTOR BASED ON NxM DRAARRAY AND NxM NMOSFET
ARRAY AND ANTENNA DESIGN METHOD Technical field The present invention relates to the technical field of terahertz detectors, and in particular to a terahertz detector based on an NxM DRA array and an NxM NMOSFET array, and an antenna design method. Technical background A terahertz frequency band refers to a region of electromagnetic radiation having a frequency of 0.1 to 10 THz and a wavelength of 30 pm to 3 mm and between millimeter waves and infrared light. For a long time, due to the lack of effective detection methods and large-power terahertz radiation sources, the research and understanding of the terahertz frequency band has been very limited. Microwave millimeter waves and infrared optics develop relatively mature, whereas terahertz waves are between the microwave millimeter waves and the infrared band, namely, a blank area between electronics and photonics, which is called the terahertz "blank" in the electromagnetic spectrum". At present, the terahertz technology and its application have become research hotspots, and have broad application prospects in public safety, environmental detection, biomedicine, large-capacity data communication and so on. The terahertz detection technology is an extension of terahertz science applications. At present, terahertz detection based on NMOSFET has proved to be very feasible. However, due to a low gain and a narrow impedance matching bandwidth of a conventional terahertz antenna such as an on-chip patch, low sensitivity based on a single NMOSFET detection and the like, the sensitivity of existing detectors that perform terahertz detection based on NMOSFET is difficult to meet the actual requirements. Therefore, how to solve the problems that the conventional terahertz antenna such as an on-chip patch has a low gain and a
BL-5108 LU101371 narrow impedance matching bandwidth, and the detection sensitivity based on a single NMOSFET is low, and how to improve the detection sensitivity based on NMOSFET detection are technical problems that are currently urgently needed to be solved.
Summary of the invention A main object of the present invention is to propose a terahertz detector based on an NxM DRA array and an NxM NMOSFET array, and the present invention also proposes an antenna design method, which aims to cause the terahertz detector based on the NxM NMOSFET array detection to achieve higher detection sensitivity. To achieve the above object, the present invention proposes a terahertz detector based on an NxM DRA array and an NxM NMOSFET array, comprising an NxM on-chip DRA array, wherein the NxM on-chip DRA array is connected to one end of a first transmission line of a matching network MN; the other end of the first transmission line is connected to the NxM NMOSFET array; the first transmission line is further connected to one end of a second transmission line; the other end of the second transmission line is grounded; the other end of the NxM NMOSFET | array is connected to one end of a first DC blocking capacitor; the other end of the first DC blocking capacitor is connected to a positive electrode of a low noise preamplifier and a second bias resistor; the other end of the second bias resistor is connected to a second bias voltage; two ends of a first resistor are connected to a negative electrode and an output terminal of the low noise preamplifier, respectively; | one end of the first resistor is further connected to one end of a second resistor; the other end of the second resistor is connected to one end of a second DC blocking | capacitor; the other end of the second DC blocking capacitor is grounded, the other end of the first resistor is connected to one end of a second DC blocking capacitor, and the other end of the second DC blocking capacitor is grounded. Preferably, the NxM NMOSFET array comprises NxM NMOSFET units, a source of each NMOSFET unit is connected to one end of the first transmission line of the matching network MN, a gate of each NMOSFET unit is connected to a third bias | |
| | 3 BL-5108 LU101371 resistor through a switch, the other end of the third bias resistor is connected to a third bias voltage, and a drain of each NMOSFET unit is connected to a Vout terminal through a switch.
Preferably, each NMOSFET unit specifically comprises a first NMOSFET and a second NMOSFET, a gate of the first NMOSFET is connected to one end of a first bias resistor and a third transmission line, the other end of the first bias resistor is connected to a first bias voltage, a drain of the first NMOSFET is connected to a source of the second NMOSFET, a gate of the second NMOSFET is connected to an SEL terminal, and a drain of the second NMOSFET is connected to a Vout terminal. Preferably, the NxM on-chip DRA array is an NxM antenna array formed on a rectangular integrated process top-layer metal, where both N and M are even numbers. Preferably, the NxM on-chip DRA array is a 2x2 on-chip DRA array; the NxM on-chip DRA array comprises four on-chip H-shaped slot structures having a same structure that are formed on four corners of a surface of the rectangular integrated process top-layer metal, respectively; four rectangular dielectric resonator blocks having a same shape are fixed on the four on-chip H-shaped slot structures by an insulating adhesive layer, respectively; one lead-out slot of a first on-chip H-shaped slot structure located at an upper left end portion is connected to one lead-out slot of a second on-chip H-shaped slot structure located at a lower left end portion | through a first connection slot; another lead-out slot of the first on-chip H-shaped slot structure is connected to one lead-out slot of a third on-chip H-shaped slot structure located at an upper right end portion through a second connection slot; another lead-out slot of the third on-chip H-shaped slot structure is connected to one lead-out slot of a fourth on-chip H-shaped slot structure located at a lower right end portion through a third connection slot, and the other lead-out slot of the second on-chip H-shaped slot structure and the other lead-out slot of the fourth on-chip H-shaped slot structure respectively form a connection terminal through a first lead-out slot and a second lead-out slot for the antenna array to connect an external circuit.
| 4 BL-5108 LU101371 Preferably, the first connection slot, the second connection slot, the third connection slot, the first lead-out slot, and the second lead-out slot form a 4-way GCPW power division network; a phase difference between a phase of the first connection slot and the second connection slot at a junction of the first on-chip H-shaped slot structure and a phase of the first connection slot and the first lead-out slot at a junction of the second on-chip H-shaped slot structure is 180°; and a phase difference between a phase of the second connection slot and the third connection slot at a junction of the third on-chip H-shaped slot structure and a phase of the third connection slot and the second lead-out slot at a junction of the fourth on-chip H-shaped slot structure is 180°. Preferably, the four on-chip H-shaped slot structures having the same structure each comprise a left vertical slot and a right vertical slot disposed in parallel; an inverted L-shaped left side slot and an inverted L-shaped right side slot are correspondingly formed on opposite sides of the left vertical slot and the right vertical slot, respectively; horizontal portions in the inverted L-shaped left side slot and the inverted L-shaped right side slot are connected at corresponding middle portions of the left vertical slot and the right vertical slot; and vertical portions in the inverted L-shaped left side slot and the inverted L-shaped right side slot form two lead-out slots connected to the first connection slot or the second connection slot or the third connection slot or the first lead-out slot or the second lead-out slot, respectively.
Preferably, the on-chip H-shaped slot structure is designed and processed by selecting and using a silicon-based integrated process; the insulating adhesive layer having good thermal stability fixes the rectangular dielectric resonator block to an on-chip excitation structure; the rectangular dielectric resonator block is processed to a specific size by selecting and using an insulating material having a relative dielectric constant of >5 to couple and radiate an electromagnetic field to a space; a rectangular dielectric resonant mode is selected as a mode of TEs13. the on-chip DRA array is designed to have a center frequency of 300 GHz; magnesium oxide with a relative dielectric constant of 9.65 is selected and used as a material of | | | }
| |
BL-5108 LU101371 the rectangular dielectric resonator block; and the on-chip structure is designed by selecting and using 0.18mGeSi BiCMOS process parameters, and there are six layers of metal Metal1-Metal6 and five layers of metal vias Via1-ViaS in the process. 5 The present invention also proposes a method of designing the dielectric resonant antenna of NxM on-chip DRA described above, comprising steps of: step 1: designing a rectangular dielectric resonator block, wherein a resonance mode is in a mode of Tea, and the size of the rectangular dielectric resonator block can be solved by solving a transcendental equation (1): k, tan( EF ons = We. = Dk, = R? 2 (1) k,, „lm zn ZZ KK +k = c Lorna 2H, 2) wherein Equation (2) is an explanation of parameters of Equation (1), where © is the speed of light, and Jom is an operating frequency of the rectangular dielectric resonator block in this mode, a high-order resonance mode of TEs. mode is selected and used as the resonance mode of the rectangular dielectric resonator block, and then the transcendental equation (1) is solved by programming with mathematical software Matlab to obtain the size of the rectangular dielectric resonator block; step 2: designing an on-chip excitation structure, wherein in the design process, a top-layer metal Metal 6 is selected and used to design a slot structure while a bottom-layer metal Metal1 is selected and used as a metal base plate to suppress an electromagnetic wave from propagating toward a high-loss silicon-based substrate, and intermediate metal layers and metal vias are stacked to form a metal shielding cavity surrounding the H-shaped slot structure to suppress electromagnetic leakage and reduce a loss, and various size parameters of the | | |
BL-5108 LU101371 H-shaped slot structure are finally determined; step 3: selecting thin insulating adhesive, wherein thermal stability insulating adhesive with a relative dielectric constant is selected and used as insulating adhesive, and the rectangular dielectric resonator block is combined with the on-chip H-shaped slot structure; step 4: designing a 4-way GCPW power division network, wherein a GCPW transmission line structure composed of the top-layer metal Metal6 and the bottom-layer metal Metal1 is adopted to design the 4-way GCPW power division network, and then parameters are optimized by means of high-frequency structure simulation analysis software to meet impedance matching and port phase requirements of the GCPW power division network; and step 5: performing co-simulation and optimization of the 4-way GCPW power division network and the NxM on-chip DRA array, and obtaining a return loss S11 and a gain of the NxM on-chip DRA array as a function frequency by co-simulation.
The technical solution of the present invention has the following advantages over the prior art: The technical solution of the present invention combines a rectangular dielectric resonator block in a TEs15 mode of a high-order mode with low loss characteristics and an on-chip slot feed structure to design and form an NxM on-chip dielectric resonant terahertz antenna array, and then the optimization of the impedance matching through the GCPW power division network and the superposition of vibration source antennas in the space electromagnetic field can effectively overcome the technical problem of low on-chip terahertz antenna gain and narrow on-chip terahertz antenna impedance matching bandwidth existed when designing the on-chip terahertz antenna.
Compared with the conventional | NMOSFET terahertz detectors based on the terahertz antennas such as on-chip | patches etc. or the conventional single NMOSFET terahertz detector based on a single on-chip DRA, the technical solution of the present invention can achieve | |
| 7 BL-5108 LU101371 higher on-chip terahertz antenna gain and wider on-chip terahertz antenna impedance matching bandwidth.
In addition, by introducing an NxM NMOSFET array, the present invention enables aterahertz detector based on NxM NMOSFET array detection to achieve a higher terahertz detection sensitivity compared with a terahertz detector based on a single NMOSFET detection.
In the NxM NMOSFET array, the number of NMOSFETs is precisely controlled by row selection control switches and column selection control switches, and the output of any one NMOSFET unit (such as DNM, NMOSFET unit of the Nth row and the Mth column) can be tested.
In each NMOSFET unit, the width-to-length ratio W/L of the first NMOSFET (the gate is biased with a resistor and a voltage) may be the same, or may be different, and can be adjusted according to actual detection requirements, and the width-to-length ratio W/L of the second NMOSFET (the gate is not biased with a resistor and a voltage) is generally the same, similarly to an effect of a switch.
Brief description of the drawings In order to more clearly illustrate the technical solutions in embodiments of the present invention or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly described below.
Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and other accompanying drawings can be obtained by ordinary persons skilled in the art from the structures illustrated in these accompanying drawings without any inventive efforts.
Fig. 1 is a schematic structural view of a terahertz detector based on a 2x2 on-chip DRA array and an NxM NMOSFET array according to an embodiment of the present invention;
Fig. 2 is a schematic structural view of an NxM NMOSFET array according to the embodiment of the present invention; Fig. 3 is a schematic structural view of a 2x2 on-chip DRA array according to the | |
| I 8 BL-5108 LU101371 embodiment of the present invention; Fig. 4 is a schematic structural view of an on-chip DRA unit according to the embodiment of the present invention;
Fig. 5 is a schematic structural view of an on-chip H-shaped slot structure according to the embodiment of the present invention; Fig. 6 is a schematic structural view of a 4-way GCPW power division network in Fig. 2; Fig. 7 is a schematic structural view of a rectangular dielectric resonator block according to the embodiment of the present invention; Fig. 8 is a diagram showing an S parameter of a 4-way GCPW power division network according to the embodiment of the present invention as a function of frequency; Fig. 9 is a diagram showing a phase between ports of a 4-way GCPW power division network according to the embodiment of the present invention as a function of frequency; Fig. 10 is a diagram showing a return loss S11 of a 2x2 on-chip DRA array according to the embodiment of the present invention as a function of frequency;
Fig. 11 is a diagram showing a gain of a 2x2 on-chip DRA array according to the embodiment of the present invention as a function of frequency, and Fig. 12 is a radiation direction of a 2x2 on-chip DRA array according to the embodiment of the present invention.
Description of the reference symbols: | |
BL-5108 LU101371 1 On-chip H-shaped slot | 11 Left vertical slot Lee TE 3 Rectangular dielectric | 13 Left side slot Pres TE TE 4 Integrated process top-layer | 14 Right side slot
PTE PE EEE Rectangular integrated | 15 Metal cavity i LL First connection slot 101 Integrated process PTT meme 7 Second connection slot A1 First on-chip H-shaped slot PO (EEE ee RE Third connection slot A2 Second on-chip H-shaped PO (TEE ee First lead-out slot A3 Third on-chip H-shaped Com ee Second lead-out slot A4 Fourth on-chip H-shaped PE (TETE me UE The implementation, functional features and advantages of the object of the present invention will be further described with reference to the accompanying drawing. 5 Detailed description of the embodiments The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in 10 the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all the | embodiments. All other embodiments obtained by ordinary persons skilled in the art based on the embodiments in the present invention without creative efforts are | |
| | 10 BL-5108 LU101371 within the scope of the present invention. It should be noted that if there is a directional indication (such as up, down, left, right, front, back, ...) mentioned in the embodiments of the present invention, the directional indication is only used to explain the relative positional relationship between components, motion status, and the like in a specific posture (as shown in the drawing), and if the specific posture changes, the directional indication also changes accordingly.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of the "first", "second", etc. is used for the purpose of description only, and is not to be construed as an its relative importance or implicit indication of the number of technical features indicated. Thus, the features defined by "first" or "second" may include at least one of the features, either explicitly or implicitly. In addition, the technical solutions among the various embodiments may be combined with each other, but must be based on the enablement of the ordinary persons skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist, and is not within the scope of protection claimed by the present invention.
The present invention proposes a terahertz detector based on an NxM DRA array and an NxM NMOSFET array.
In an embodiment of the present invention, the technical solution of the present invention is described in detail with a terahertz detector based on a 2x2 on-chip DRA array and an NxM NMOSFET array. As shown in Fig. 1, a the terahertz detector based on the 2x2 on-chip DRA array and the NxM NMOSFET array of the present embodiment includes a 2x2 on-chip DRA array, a matching network MN, an NxM NMOSFET array, a second bias resistor Rb2, a second bias voltage Vb2, a first DC blocking capacitor C1, a low noise preamplifier and a voltage feedback loop of the low noise preamplifier. Specifically, the 2x2 on-chip DRA array of the present embodiment is connected to one end of a first transmission line TL1 of the matching network MN; the other end of the first transmission line TL1 is connected | |
| ! 11 BL-5108 LU101371 to the NxM NMOSFET array; the first transmission line TL1 is further connected to one end of a second transmission line TL2; the other end of the second transmission line TL2 is grounded; the other end of the NxM NMOSFET array is connected to one end of a first DC blocking capacitor C1; the other end of the first DC blocking capacitor C1 is connected to a positive electrode of a low noise preamplifier and the second bias resistor Rb2; the other end of the second bias resistor Rb2 is connected to the second bias voltage Vb2; two ends of a first resistor Rf are connected to a negative electrode and an output terminal of the low noise preamplifier, respectively; one end of the first resistor Rf is further connected to one end of a second resistor Rg; the other end of the second resistor Rg is connected to one end of a second DC blocking capacitor C2; the other end of the second DC blocking capacitor C2 is grounded; the other end of the first resistor Rf is connected to one end of a second DC blocking capacitor C3, and the other end of the second DC blocking capacitor C3 is grounded.
As shown in Fig. 2, the NxM NMOSFET array specifically includes NxM NMOSFET units (numbered as D11, D12, D13, ..., DNM), that is, there are N row selection control switches (Row1, Row2, Row3, …, RowN) in a lateral direction and there are M column selection control switches (Column1, Column2, Column3, ..., ColumnM) in a longitudinal direction. A source of each NMOSFET unit is connected to one end of the first transmission line TL1 of the matching network MN, a gate of each NMOSFET unit is connected to the third bias resistor Rb3 through a switch, and the other end of the third bias resistor Rb3 is connected to the third bias voltage Vb3, and a drain of each NMOSFET unit is connected to a Vout terminal through a switch. As shown in Fig. 2, preferably, each NMOSFET unit of the present embodiment specifically includes two NMOSFETSs, a first bias voltage Vb1, a first bias resistor Rb1, and an open quarter-wavelength third transmission line TL3, where the two NMOSFETs are a first NMOSFET and a second NMOSFET, respectively. Specifically, a fixed first bias voltage Vb1 and a first bias resistor Rb1 are loaded on a gate of the first NMOSFET, and an open quarter-wavelength third transmission line TL3 is connected between the gate of the first NMOSFET and the bias resistor Rb1. That is, the gate of the first NMOSFET is connected to one end of the first bias i i
I 12 BL-5108 LU101371 resistor Rb1 and the third transmission line TL3, and the other end of the first bias resistor Rb1 is connected to the first bias voltage Vb1, wherein the third transmission line TL3 is used to eliminate the influence of the gate DC bias on the impedance matching between the antenna and the transistor.
A drain of the first NMOSFET is connected to a source of the second NMOSFET, a gate of the second NMOSFET is connected to an SEL terminal, and a drain of the second NMOSFET is connected to a Vout terminal.
Referring to Figs. 1 and 2, the matching network MN is composed of two microstrip transmission lines, i.e. the first transmission line TL1 and the second transmission line TL2. The matching network MN is mainly used to improve power transmission efficiency between the antenna and the transistors of the NxM NMOSFET array and provide a DC ground for the sources M1 of the transistors of the NxM NMOSFET array.
The left end of the first transmission line TL1 is connected to the 2x2 on-chip DRA array, and the right end of the first transmission line TL1 is connected to input terminals M1 (Array) of the NxM NMOSFET array.
The first DC blocking capacitor C1, the second bias voltage Vb2, and the second bias resistor Rb2 are connected between output terminals Vout (Array) of the NxM NMOSFET array and a positive input terminal of the low noise preamplifier, wherein the second bias resistor Rb2 and the second bias voltage Vb2 are used to supply power to the low noise preamplifier.
The voltage feedback loop of the low noise preamplifier is mainly composed of the first resistor Rf, the second resistor Rg, the second DC blocking capacitor C2 and the third DC blocking capacitor C3, wherein the gain of the low noise preamplifier can be adjusted by changing the resistance value(s) of the first resistor Rf and/or the second resistor Rg.
The output voltage signal of the terahertz detector based on the 2x2 on-chip DRA array and the NxM NMOSFET array of the present embodiment is a DC voltage signal, and the magnitude of the DC voltage signal is proportional to the radiation intensity of the terahertz signal, so that the intensity information of the incident terahertz signal can be obtained according to the magnitude of the output voltage signal of the terahertz detector, thereby realizing terahertz detection. i |
| 13 BL-5108 LU101371 As shown in Figs. 3, 4 and 5, the 2x2 on-chip DRA array of the present embodiment is a 2x2 antenna array formed on an rectangular integrated process top-layer metal 5, which includes four on-chip H-shaped slot structures (A1, A2, A3 and A4) having the same structure that are formed on four corners of a surface of the rectangular integrated process top-layer metal 5, respectively, and four rectangular dielectric resonator blocks 3 having the same shape are fixed to the four on-chip H-shaped slot structures (A1, A2, A3 and A4) by an insulating adhesive layer 2, respectively.
One lead-out slot of a first on-chip H-shaped slot structure A1 located at an upper left end portion is connected to one lead-out slot of a second on-chip H-shaped slot structure A2 located at a lower left end portion through a first connection slot 6; another lead-out slot of the first on-chip H-shaped slot structure A1 is connected to one lead-out slot of a third on-chip H-shaped slot structure A3 located at an upper right end portion through a second connection slot 7; another lead-out slot of the third on-chip H-shaped slot structure A3 is connected to one lead-out slot of a fourth on-chip H-shaped slot structure A4 located at a lower right end portion through a third connection slot 8; and the other lead-out slot of the second on-chip H-shaped slot structure A2 and the other lead-out slot of the fourth on-chip H-shaped slot structure A4 respectively form a connection terminal through a first lead-out slot 9 and a second lead-out slot 10 for the antenna array to connect an external circuit.
As shown in Figs. 3 and 6, the first connection slot 6, the second connection slot 7, the third connection slot 8, the first lead-out slot 9, and the second lead-out slot 10 form a 4-way GCPW power division network, wherein a phase difference between a phase of the first connection slot 6 and the second connection slot 7 at a junction of the first on-chip H-shaped slot structure A1 and a phase of the first connection slot 6 and the first lead-out slot 9 at a junction of the second on-chip H-shaped slot structure A2 is 180°, and a phase difference between a phase of the second connection slot 7 and the third connection slot 8 at a junction of the third on-chip H-shaped slot structure A3 and a phase of the third connection slot 8 and the second lead-out slot 10 at a junction of the fourth on-chip H-shaped slot structure A4 is 180°. Preferably, Referring to Fig. 5, the four on-chip H-shaped slot structures A1, A2, A3 | |
| 14 BL-5108 LU101371 and A4 having the same structure of the present embodiment each comprise a left vertical slot 11 and a right vertical slot 12 disposed in parallel. An inverted L-shaped left side slot 13 and an inverted L-shaped right side slot 14 are correspondingly formed on opposite sides of the left vertical slot 11 and the right vertical slot 12, respectively. Horizontal portions in the inverted L-shaped left side slot 13 and the inverted L-shaped right side slot 14 are connected at corresponding middle portions of the left vertical slot 11 and the right vertical slot 12. Vertical portions in the inverted L-shaped left side slot 13 and the inverted L-shaped right side slot 14 form two lead-out slots connected to the first connection slot 6 or the second connection slot 7 or the third connection slot 8 or the first lead-out slot 9 or the second lead-out slot 10, respectively.
Referring to Figs. 4 and 7, the on-chip H-shaped slot structure 1 of the present embodiment is designed and processed by using a silicon-based integrated process to excite the rectangular dielectric resonator block 3 covering an upper portion thereof and optimize the impedance matching effect. The insulating adhesive layer 2 has good thermal stability and is used to fix the rectangular dielectric resonator block 3 to the on-chip excitation structure 1. Preferably, the rectangular dielectric resonator block 3 of the present embodiment is processed to a specific size by selecting and using an insulating material with a larger relative dielectric constant (preferably, a relative dielectric constant of >5) to couple and radiate an electromagnetic field to a space. Also, in the present invention, the rectangular dielectric resonance mode is selected as a mode of Ts, Acenter frequency of a 2x2 on-chip DRA array design according an embodiment of the present invention is 300 GHz, and magnesium oxide having a relative dielectric constant of 9.65 is selected and used as the material of the rectangular dielectric resonator block. The on-chip structure is designed by selecting and using the
0.18mGeSi BiCMOS process (Towerjazz SBC18H3) parameters, and there are six layers of metal Metal1-Metal6 and five layers of metal vias Via1-Via5 in the process.
The present invention also proposes a method of designing the dielectric resonant i |
| | 15 BL-5108 LU101371 antenna of 2x2 on-chip DRA, and its specific design steps are as described below: Step 1: design a rectangular dielectric resonator block.
A resonance mode is in a mode of TEs, and the size of the rectangular dielectric resonator block as shown in Fig. 7 can be solved by solving a transcendental equation (1): k, tan ont io Tie, Zi? 2 (1) b= El fom Ek en RARE ek, c Lor 2H pra (2)
wherein Equations (2) is the explanation for parameters of Equation (1), where ¢ is the speed of light, and Som is the operating frequency of the rectangular dielectric resonator block in this mode.
A high-order resonant mode of TEs 15 mode is selected as the resonant mode of the rectangular dielectric resonator block of the present invention, and has a higher gain than the base mode.
Then, the transcendental equation (1) is solved by programming with the mathematical software Matlab, obtaining the sizes of the rectangular dielectric resonator block at 300 GHz as: Wor =250um, Ly, = 250um, H pp = 400m Step 2: design an on-chip excitation structure.
An on-chip H-shaped slot structure is shown in Fig. 5. In the design process, only a top-layer metal Metal6 can be selected and used to design the slot structure while a bottom-layer metal Metal1 is selected and used as a metal base plate to suppress the electromagnetic wave from propagating toward a high-loss silicon substrate, and intermediate metal layers and metal vias are stacked to form a metal shield cavity surrounding the H-shaped slot structure, to suppress electromagnetic leakage and reduce a loss.
The dimension parameters of the H-shaped slot structure are: I, =70ym,l, =220ym,w, =9.5ym, w, =15ym, w, = 10m, w, = 104m
| |
! | 16 BL-5108 LU101371 Step 3: select thin insulating adhesive. Thermal stability insulating adhesive with a relative dielectric constant of 2.4 and a thickness of 104 js selected and used as the insulating adhesive for combining the rectangular dielectric resonator block with the on-chip H-shaped slot structure.
Step 4: design a 4-way GCPW power division network. A GCPW transmission line structure composed of the top-layer metal Metal6 and the bottom-layer metal Metal1 is adopted to design the 4-way GCPW power division network, and then parameters are optimized by means of high-frequency structure simulation analysis software (HFSS) to meet impedance matching and port phase requirements of the GCPW power division network, wherein Fig. 8 is a diagram showing an S parameter of the 4-way GCPW power division network as a function of frequency, and Fig. 9 is a diagram showing a phase between ports of the 4-way GCPW power division network as a function of frequency.
Step 5: perform co-simulation and optimization of the 4-way GCPW power division network and the 2x2 on-chip DRA array. The return loss S11 and the gain of the 2x2 on-chip DRA array as a function of frequency obtained by co-simulation are as shown in Figs. 10 and 11, respectively, wherein the 2x2 on-chip DRA array has a matching bandwidth of 20.1% (268 to 328GHz) at an impedance of -10dB, and the 2x2 on-chip DRA array has a peak gain of 9.91dBi and a gain bandwidth of 16% (266 to 314GHz) at 3dB. The radiation direction of the 2x2 on-chip DRA array is as shown in Fig. 12. It has a narrower lobe width and better directionality, and at the same time, its radiation efficiency is as high as 51%.
The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. All equivalent structural variants made by using the description and drawings of the present invention, or direct or indirect applications thereof in other related technical fields, in the concept of the present invention, are encompassed within the scope of patent protection of the present invention.
Claims (9)
1. A terahertz detector based on an NxM DRA array and an NxM NMOSFET array, s characterized in that it comprises an NxM on-chip DRA array, wherein the NxM on-chip DRA array is connected to one end of a first transmission line of a matching network MN; the other end of the first transmission line is connected to the NxM NMOSFET array; the first transmission line is further connected to one end of a second transmission line; the other end of the second transmission line is grounded, the other end of the NxM NMOSFET array is connected to one end of a first DC blocking capacitor; the other end of the first DC blocking capacitor is connected to a positive electrode of a low noise preamplifier and a second bias resistor; the other end of the second bias resistor is connected to a second bias voltage; two ends of a first resistor are connected to a negative electrode and an output terminal of the low noise preamplifier, respectively; one end of the first resistor is further connected to one end of a second resistor; the other end of the second resistor is connected to one end of a second DC blocking capacitor; the other end of the second DC blocking capacitor is grounded; the other end of the first resistor is connected to one end of a second DC blocking capacitor, and the other end of the second DC blocking capacitor is grounded.
2. The terahertz detector of claim 1, characterized in that the NxM NMOSFET array comprises NxM NMOSFET units, a source of each NMOSFET unit is connected to one end of the first transmission line of the matching network MN, a gate of each NMOSFET unit is connected to a third bias resistor through a switch, the other end of the third bias resistor is connected to a third bias voltage, and a drain of each NMOSFET unit is connected to a Vout terminal through a switch.
3. The terahertz detector of claim 2, characterized in that each NMOSFET unit specifically comprises a first NMOSFET and a second NMOSFET, a gate of the first NMOSFET is connected to one end of a first bias resistor and a third transmission line, the other end of the first bias resistor is connected to a first bias voltage, a drain of the first NMOSFET is connected to a source of the second NMOSFET, a gate of the second NMOSFET is connected to an SEL terminal, and a drain of the 1 |
| 18 BL-5108 LU101371 second NMOSFET is connected to a Vout terminal.
4. The terahertz detector of claim 3, characterized in that the NxM on-chip DRA array is an NxM antenna array formed on a rectangular integrated process top-layer metal, where both N and M are even numbers.
5 The terahertz detector of claim 4, characterized in that the NxM on-chip DRA array is a 2x2 on-chip DRA array; the NxM on-chip DRA array comprises four on-chip H-shaped slot structures having a same structure that are formed on four corners of a surface of the rectangular integrated process top-layer metal, respectively; four rectangular dielectric resonator blocks having a same shape are fixed on the four on-chip H-shaped slot structures by an insulating adhesive layer, respectively; one lead-out slot of a first on-chip H-shaped slot structure located at an upper left end portion is connected to one lead-out slot of a second on-chip H-shaped slot structure located at a lower left end portion through a first connection slot; another lead-out slot of the first on-chip H-shaped slot structure is connected to one lead-out slot of a third on-chip H-shaped slot structure located at an upper right end portion through a second connection slot; another lead-out slot of the third on-chip H-shaped slot structure is connected to one lead-out slot of a fourth on-chip H-shaped slot structure located at a lower right end portion through a third connection slot; and the other lead-out slot of the second on-chip H-shaped slot structure and the other lead-out slot of the fourth on-chip H-shaped slot structure respectively form a connection terminal through a first lead-out slot and a second lead-out slot for the antenna array to connect an external circuit.
6. The terahertz detector of claim 5, characterized in that the first connection slot, the second connection slot, the third connection slot, the first lead-out slot, and the second lead-out slot form a 4-way GCPW power division network; a phase difference between a phase of the first connection slot and the second connection slot at a junction of the first on-chip H-shaped slot structure and a phase of the first | connection slot and the first lead-out slot at a junction of the second on-chip H-shaped slot structure is 180°; and a phase difference between a phase of the second connection slot and the third connection slot at a junction of the third on-chip H-shaped slot structure and a phase of the third connection slot and the | !
BL-5108 LU101371 second lead-out slot at a junction of the fourth on-chip H-shaped slot structure is 180°.
7. The terahertz detector of claim 6, characterized in that the four on-chip H-shaped slot structures having the same structure each comprise a left vertical slot and a right vertical slot disposed in parallel; an inverted L-shaped left side slot and an inverted L-shaped right side slot are correspondingly formed on opposite sides of the left vertical slot and the right vertical slot, respectively; horizontal portions in the inverted L-shaped left side slot and the inverted L-shaped right side slot are connected at corresponding middle portions of the left vertical slot and the right vertical slot, and vertical portions in the inverted L-shaped left side slot and the inverted L-shaped right side slot form two lead-out slots connected to the first connection slot or the second connection slot or the third connection slot or the first lead-out slot or the second lead-out slot, respectively.
8. The terahertz detector of claim 7, characterized in that the on-chip H-shaped slot structure is designed and processed by selecting and using a silicon-based | integrated process; the insulating adhesive layer having good thermal stability fixes the rectangular dielectric resonator block to an on-chip excitation structure; the rectangular dielectric resonator block is processed to a specific size by selecting and using an insulating material having a relative dielectric constant of >5 to couple and radiate an electromagnetic field to a space; a rectangular dielectric resonant mode is selected as a mode of Tps; the on-chip DRA array is designed to have a center frequency of 300 GHz; magnesium oxide with a relative dielectric constant of 9.65 is selected and used as a material of the rectangular dielectric resonator block; and the on-chip structure is designed by selecting and using 0.18mGesSi BiCMOS process parameters, and there are six layers of metal Metal1-Metal6 and five layers of metal vias Via1-Via5 in the process.
9. A method of designing the dielectric resonant antenna of NxM on-chip DRA of claim 7, characterized in that it comprises the steps of: step 1: designing a rectangular dielectric resonator block, wherein a resonance | |
BL-5108 LU101371 mode is in a mode of TEs. and the size of the rectangular dielectric resonator block can be solved by solving a transcendental equation (1): ke, tan Pons) = fee, Da, -# 2 (1)
ko =m pom Ek =n HK HK =,
c Lg, 2H pp, (2) wherein Equation (2) is an explanation of parameters of Equation (1), where © is the speed of light, and om is an operating frequency of the rectangular dielectricresonator block in this mode, a high-order resonance mode of TEs. mode is selected and used as the resonance mode of the rectangular dielectric resonator block, and then the transcendental equation (1) is solved by programming with mathematical software Matlab to obtain the size of the rectangular dielectric resonator block;
step 2: designing an on-chip excitation structure, wherein in the design process, a top-layer metal Metal 6 is selected and used to design a slot structure while a bottom-layer metal Metal1 is selected and used as a metal base plate to suppress an electromagnetic wave from propagating toward a high-loss silicon-basedsubstrate, and intermediate metal layers and metal vias are stacked to form a metalshielding cavity surrounding the H-shaped slot structure to suppress electromagnetic leakage and reduce a loss, and various size parameters of the H-shaped slot structure are finally determined,
step 3: selecting thin insulating adhesive, wherein thermal stability insulating adhesive with a relative dielectric constant is selected and used as insulating adhesive, and the rectangular dielectric resonator block is combined with the on-chip H-shaped slot structure;
step 4: designing a 4-way GCPW power division network, wherein a GCPW transmission line structure composed of the top-layer metal Metal6 and the
| |
: 21 BL-5108 LU101371 bottom-layer metal Metal is adopted to design the 4-way GCPW power division network, and then parameters are optimized by means of high-frequency structure simulation analysis software to meet impedance matching and port phase requirements of the GCPW power division network; and step 5: performing co-simulation and optimization of the 4-way GCPW power division network and the NxM on-chip DRA array, and obtaining a return loss S11 and a gain of the NxM on-chip DRA array as a function of frequency by co-simulation.
| |
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