LU101196B1 - A high-output-power and high-efficiency power amplifier - Google Patents
A high-output-power and high-efficiency power amplifier Download PDFInfo
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- LU101196B1 LU101196B1 LU101196A LU101196A LU101196B1 LU 101196 B1 LU101196 B1 LU 101196B1 LU 101196 A LU101196 A LU 101196A LU 101196 A LU101196 A LU 101196A LU 101196 B1 LU101196 B1 LU 101196B1
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- hbt transistor
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- 230000005540 biological transmission Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 18
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000013461 design Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009022 nonlinear effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/61—Indexing scheme relating to amplifiers the cascode amplifier has more than one common gate stage
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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Abstract
The present invention discloses a high-output-power and high-efficiency power amplifier, wherein a HBT stack structure based on a SiGe process being stacked in series by three layers of HBTs is adopted; the power amplifier comprises a second HBT transistor, a third HBT transistor, a fourth HBT transistor and a resistor divider network; the second HBT transistor has an emitter being grounded, a collector connected to an emitter of the third HBT transistor, and a base separately connected to a second DC blocking capacitor and a first choke inductor; the third HBT transistor has a collector connected to an emitter of the fourth HBT transistor, and a base connected to a third bias resistor and a second grounded capacitor, and a second inductor and a third DC blocking capacitor are connected between the base and the emitter of the third HBT transistor; a third inductor and a fourth DC blocking capacitor are connected between the base and the emitter of the fourth HBT transistor; the base of the fourth HBT transistor is connected to a second bias resistor and a third grounded capacitor; the collector of the fourth HBT transistor is connected to the first resistor, a second choke inductor and a fifth DC blocking capacitor.
Description
A HIGH-OUTPUT-POWER AND HIGH-EFFICIENCY POWER AMPLIFIER
Technical field
The present invention relates to the technical field of wireless communication power amplifiers, and more particularly to a high-output-power and high-efficiency power amplifier.
Technical background
In recent years, with the rapid development of the communication industry, the performance requirements of communication transceivers are becoming more and more. A RF power amplifier is a critical hardware module at a transmitter end, and many indicators thereof such as output power, efficiency, linearity, etc. are very important for wireless communication. Thus, its design is especially critical [1], The output power of the RF power amplifier determines the length of the transmission distance, and the efficiency of the RF power amplifier determines its operating and maintenance costs. In order to realize high-performance RF functional amplifiers, a process of lll-V group compounds such as GaAs or GaN is often used at home and abroad. Although such a process can achieve a high output power, its production cost is high, its product yield is low, and it is not easy to integrate, which is not advantageous for large-scale production and application. Although the traditional CMOS process has the advantages of low cost and high integration, the transistor has low breakdown voltage, high power consumption, and poor linearity. Since its high frequency performance is poor, it is not suitable for achieving high output power and high efficiency at high frequencies.
At present, a heterojunction bipolar transistor (HBT) based on a SiGe process has defects such as a low breakdown voltage and a small maximum current density [2], so there are certain difficulties in designing amplifiers with high output power. In order to solve the problem of high power output of an on-chip power amplifier, commonly used methods include power synthesis, connecting a number of transistors in parallel, etc. However, there is a problem that the circuit structure is complicated and the chip area is larger.
Based on the above technical problems, the present invention designs a power amplifier with a stack structure of heterojunction bipolar transistors (HBTs) based on the SiGe process on the premise of saving the chip area, and adds a circuit structure for canceling parasitic capacitance between stages to correct a phase deviation caused by the parasitic capacitance, thereby further improving the output power and efficiency.
[References] [1] Baoyong Chi, Zhiping Yu, and Bingxue Shi, “Analysis and Design of RF Integrated Circuits” [M], Tsinghua University Press, 2006.
[2] Michael Chang, “A 26 to 40GHz Wideband SiGe Balanced Power Amplifier IC IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu, pp. 729 -732, 3-5 June 2007.
[3] David Fritsche, Robert Wolf, and Frank Ellinger, “Analysis and Design of a Stacked Power Amplifier With Very High Bandwidth,” IEEE Transactions on Microwave Theory and Techniques, vol.60, no.10, pp. 3223 - 3231, Oct. 2012.
Summary of the invention
An object of the present invention is to overcome the deficiencies in the prior art and provide a high-output-power and high-efficiency power amplifier related to the field of RF power amplifiers and integrated circuits, wherein a transistor stack structure is used to achieve high output power and reduce the chip area; in the millimeter wave band, the problem of mismatch between stacked transistor layers is effectively solved, thereby greatly improving efficiency; and the SiGe process is used to design, which is applicable for higher operating frequencies and is advantageous for integration.
The object of the present invention is achieved by the following technical solutions. A high-output-power and high-efficiency power amplifier of the present invention adopts a HBT stack structure based on a SiGe process being stacked in series by three layers of HBTs; the power amplifier comprises a second HBT transistor, a third HBT transistor, a fourth HBT transistor and a resistor divider network, the resistor divider network is composed of a first resistor, a second resistor and a third resistor connected in series sequentially, and the third Resistor is grounded; the second HBT transistor has an emitter being grounded, a collector connected to an emitter of the third HBT transistor, and a base separately connected with a second DC blocking capacitor and a first choke inductor, the second DC blocking capacitor is connected to the base of the second HBT transistor at one end and is connected to a signal input port at the other end, and the first choke inductor is connected to the base of the second HBT transistor at one end and is connected to a second voltage source at the other end; a collector of the third HBT transistor is connected to an emitter of the fourth HBT transistor, and a second inductor and a third DC blocking capacitor connected in series to each other are connected between a base and an emitter of the third HBT transistor, the base of the third HBT transistor is also separately connected with a third bias resistor and a second grounded capacitor, the third bias resistor is connected to the base of the third HBT transistor at one end, and is connected between a second resistor and a third resistor at the other end, and the second grounded capacitor is connected to the base of the third HBT transistor at one end and is grounded at the other end; a third inductor and a fourth DC blocking capacitor connected in series to each other are connected between the base and the emitter of the fourth HBT transistor; the base of the fourth HBT transistor is also separately connected with a second bias resistor and a third grounded capacitor, the second bias resistor is connected to the base of the fourth HBT transistor at one end, and is connected between a first resistor and a second resistor at the other end, the third grounded capacitor is connected to the base of the fourth HBT transistor at one end, and is grounded at the other end; the collector of the fourth HBT transistor is separately connected to the first resistor, a second choke inductor and a fifth DC blocking capacitor, the second choke inductor is connected to the collector of the fourth HBT transistor at one end and is connected to a first voltage source at the other end, and the fifth DC blocking capacitor is connected to the collector of the fourth HBT transistor at one end, and is connected to a signal output port at the other end.
The first choke inductor and the second choke inductor each adopt a quarter-wavelength transmission line, and the first inductor, the second inductor, and the third inductor each adopt a transmission line.
The second HBT transistor is disposed on a bottom layer, the third HBT transistor is disposed in a middle layer, and the fourth HBT transistor is disposed on a top layer.
Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
The present invention uses a heterojunction bipolar transistor (HBT) based on a SiGe process for RF power amplifier design, which is applicable for higher operating frequencies. By adding a compensation structure for a transmission line between the base and the emitter of the transistor in each layer of the stack structure, the parasitic effect of the transistor at a high frequency is effectively compensated, and a power amplifier with high output power and high efficiency is realized. The circuit structure adopted by the present invention is simple, the chip area is effectively reduced, and the circuit cost is saved.
Brief description of the drawings
Fig. 1 is a partial schematic circuit diagram of a single transistor being connected in parallel with an inductor.
Fig. 2 is a schematic circuit diagram of a high-output-power and high-efficiency power amplifier of the present invention.
Reference signs: R1: first bias resistor; R5: second bias resistor; R6: third bias resistor; R2: first resistor; R3: second resistor; R4: third resistor; C1 : first grounded capacitor; C6: second grounded capacitor; C7: third grounded capacitor; C2: first DC blocking capacitor; C3: second DC blocking capacitor; C4: third DC blocking capacitor; C5: fourth DC blocking capacitor; C8: fifth DC blocking capacitor; Q1 first HBT transistor; Q2: second HBT transistor; Q3: third HBT transistor; Q4: fourth HBT transistor; TL1 : first inductor; TL3: second inductor; TL4: third inductor; TL2: first choke inductor; TL5: second choke inductor; VCC: first voltage source; Vb: second voltage source.
Detailed description of the embodiments
In order to more clearly explain the technical solutions of the present invention, the present invention will be further described below in conjunction with the accompanying drawings. Other drawings may also be obtained from these drawings by an ordinary person skilled in the art without creative efforts.
Fig. 1 is a partial schematic circuit diagram of a single transistor being connected in parallel with an inductor, including a first bias resistor R1, a first grounded capacitor C1, a first DC blocking capacitor C2, a first inductor TL1, and a first HBT transistor Q1. In order to solve the limitation of the low breakdown voltage and the small current density of the SiGe process, the present invention uses the technology of transistor stacking to increase the power output of a power amplifier, and at the same time, a method of connecting an inductor between a base and a emitter of each layer of transistor is used to effectively reduce the influence of the parasitic capacitance of the transistor, further increasing power output and efficiency. It is as shown in Fig. 2. A high-output-power and high-efficiency power amplifier of the present invention adopts a stack structure of HBTs (heterojunction bipolar transistors) based on the SiGe process, which is stacked by three layers of HBTs connected in series (i.e. collectors and emitters of three layers of HBTs being connected), increasing the optimal impedance value of the overall amplifier, thereby reducing the difficulty of matching. The stack structure is powered by a resistor divider method, so that each layer of HBT is biased in class AB. This method saves the number of DC power supply pads and reduces the chip area in the actual layout. At the same time, the base of each layer of transistor is connected to a resistor to convert the voltage into the current for power supply.
The high-output-power and high-efficiency power amplifier of the present invention includes a second HBT transistor Q2, a third HBT transistor Q3, a fourth HBT transistor Q4, and a resistor divider network. The second HBT transistor Q2 is disposed on a bottom layer, the third HBT transistor Q3 is disposed in a middle layer, and the fourth HBT transistor Q4 is disposed on a top layer. The resistor divider network is composed of a first resistor R2, a second resistor R3 and a third resistor R4 connected in series sequentially, and the voltage of a first voltage source VCC is divided into the bases of the layers to provide bias voltages for the three HBT transistors. The resistor divider network is connected to a collector of the fourth HBT transistor Q4 at one end, that is, the first resistor R2 is connected to a collector of the fourth HBT transistor Q4, and it is grounded at the other end, that is, the third resistor R4 is grounded to GND.
The second HBT transistor Q2 has an emitter being grounded GND, a collector connected to an emitter of the third HBT transistor Q3,and a base separately connected with a second DC blocking capacitor C3 and a first choke inductor TL2, the second DC blocking capacitor C3 is connected to the base of the second HBT transistor Q2 at one end and is connected to a signal input port RFin at the other end, and the first choke inductor TL2 is connected to the base of the second HBT transistor Q2 at one end and is connected to a second voltage source Vb at the other end. A collector of the third HBT transistor Q3 is connected to an emitter of the fourth HBT transistor Q4, and a second inductor TL3 and a third DC blocking capacitor C4 connected in series to each other are connected between a base and an emitter of the third HBT transistor Q3, the base of the third HBT transistor Q3 is also separately connected with a third bias resistor R6 and a second grounded capacitor C6, the third bias resistor R6 is connected to the base of the third HBT transistor Q3 at one end, and is connected between a second resistor R3 and a third resistor R4 at the other end, and the second grounded capacitor C6 is connected to the base of the third HBT transistor Q3 at one end and is grounded GND at the other end.
A third inductor TL4 and a fourth DC blocking capacitor C5 connected in series to each other are connected between the base and the emitter of the fourth HBT transistor Q4. The base of the fourth HBT transistor Q4 is further connected with a second bias resistor R5 and a third grounded capacitor C7, the second bias resistor R5 is connected to the base of the fourth HBT transistor Q4 at one end, and is connected between a first resistor R2 and a second resistor R3 at the other end, and the third grounded capacitor C7 is connected to the base of the fourth HBT transistor Q4 at one end and is grounded GND at the other end. The collector of the fourth HBT transistor Q4 is separately connected to the first resistor R2, a second choke inductor TL5 and a fifth DC blocking capacitor C8. The second choke inductor TL5 is connected to the collector of the fourth HBT transistor Q4 at one end, and is connected to the first voltage source VCC at the other end. The first voltage source VCC supplies power to the entire circuit through the second choke inductor TL5, and a signal flows in from the second DC blocking capacitor C3 and finally flows out through the fifth DC blocking capacitor C8 via the collector of the fourth HBT transistor Q4. The fifth DC blocking capacitor C8 is connected to the collector of the fourth HBT transistor Q4 at one end, and is connected to a signal output port RFout at the other end.
Among them, the first choke inductor TL2 and the second choke inductor TL5 each adopt a quarter-wavelength transmission line, and play a function of blocking AC while allowing DC to pass, and the first inductor TL1, the second inductor TL3 and the third Inductor TL4 each adopts a transmission line. The second grounded capacitor C6 and the third grounded capacitor C7 are used to adjust the size of the optimal input impedance and have a certain function of adjusting the consistency of the output voltage phase of the collector in each layer. The second inductor TL3 and the third inductor TL4 are used to reduce the influence of the parasitic capacitance between the bases and the emitters of the third HBT transistor Q3 and the fourth HBT transistor Q4, respectively.
The supply voltage of the first voltage source VCC is divided by the resistor divider network to provide a suitable static working point for the stacked HBTs of each layer; and a base of a HBT of an upper layer in the stack structure is connected to a collector of a HBT of a lower layer through a transmission line and a DC blocking capacitor acting as an inductor.
As the operating frequency increases, the nonlinear effect caused by the parasitic capacitance of the transistors increases, causing the base voltage to be distorted, thereby resulting in distortion of the output collector current waveform. In order to effectively compensate for the effect of parasitic capacitance at high frequencies, the phases of the output voltages of the stack structure and the motor are adjusted to ensure that the output voltage of each layer of HBT is in phase. As a result, the amplitude of the collector output voltage of the uppermost layer of HBT is maximized, thereby achieving high power output and high efficiency. As shown in Fig. 2, the inductor is connected between the base and the emitter to form a parallel resonant network with the parasitic capacitance Cbe, and the resulting equivalent capacitance Ceq is much smaller than the parasitic capacitance Cbe. The relationship between the equivalent capacitance and the parasitic capacitance Cbe and the inductance L of the transmission lines (the first inductor TL1, the second inductor TL3, and the third inductor TL4) is as shown in Equation (1):
(1)
It can be seen from Equation (1) that the addition of the structure greatly reduces the influence of parasitic capacitance on the circuit. At the same time, a DC blocking capacitor is added to a branch of the transmission lines, so that the supply current of the base of each layer of transistor does not directly flow into a main trunk. It is ensured that the output voltage of each layer is in phase, thereby achieving the maximum power output.
In addition, since a large inductor having a choking effect occupies a large layout area and the layout is difficult, the present invention adopts a quarter-wavelength transmission line instead, connecting it to a power supply terminal, to achieve the effect of blocking AC while allowing DC to pass, and the layout area is effectively reduced at higher frequencies.
Although the functions and working processes of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the specific functions and working processes described above, and the specific embodiments given above are merely illustrative and not restrictive. Many forms may be made by those skilled in the art under the inspiration of the present invention without departing from the spirit and scope of the invention, and these are all within the protection of the present invention.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811101359.2A CN109167579A (en) | 2018-09-20 | 2018-09-20 | A kind of efficient power amplifier of high-output power |
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| LU101196B1 true LU101196B1 (en) | 2019-08-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109951162B (en) * | 2019-03-08 | 2023-04-28 | 成都中宇微芯科技有限公司 | Millimeter wave power amplifying unit and amplifier |
| JP2021090168A (en) * | 2019-12-05 | 2021-06-10 | 株式会社村田製作所 | Power amplifier circuit |
| CN111147033A (en) * | 2020-01-02 | 2020-05-12 | 尚睿微电子（上海）有限公司 | Power amplifier and electronic equipment based on HBT circuit structure |
| JP2021158641A (en) * | 2020-03-30 | 2021-10-07 | 株式会社村田製作所 | Power amplifier element |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8847689B2 (en) * | 2009-08-19 | 2014-09-30 | Qualcomm Incorporated | Stacked amplifier with diode-based biasing |
| US8368469B2 (en) * | 2010-03-10 | 2013-02-05 | Purdue Research Foundation | Silicon-on-insulator high power amplifiers |
| US8791759B2 (en) * | 2011-03-22 | 2014-07-29 | The United States Of America As Represented By The Secretary Of The Army | Bipolar stacked transistor architecture |
| CN105515542B (en) * | 2016-01-26 | 2019-01-25 | 广东工业大学 | A kind of radio-frequency power amplifier of stacked structure |
| CN108322194A (en) * | 2017-01-16 | 2018-07-24 | 天津大学（青岛）海洋工程研究院有限公司 | A kind of power amplifier of the high-output power high-gain based on current multiplexing technology |
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