CN204156827U - A kind of wideband power amplifer chip for radar system and amplifier - Google Patents
A kind of wideband power amplifer chip for radar system and amplifier Download PDFInfo
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- CN204156827U CN204156827U CN201420679919.3U CN201420679919U CN204156827U CN 204156827 U CN204156827 U CN 204156827U CN 201420679919 U CN201420679919 U CN 201420679919U CN 204156827 U CN204156827 U CN 204156827U
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Abstract
The utility model relates to technical field of electronic communication, be specifically related to a kind of wideband power amplifer chip for radar system and amplifier, comprise in chip substrate and be connected in series the first amplifying circuit and the second amplifying circuit, chip substrate is provided with the first chip operating voltage interface arranged in order, fine motion radio-frequency (RF) switch, first secondary control interface, control signal input port, constant voltage interface, first amplifying circuit switch, second chip operating voltage interface, first amplifying circuit input interface, first amplifying circuit interface of the ground wire, first amplifying circuit output interface, second amplifying circuit interface of the ground wire, second amplifying circuit input interface, second secondary control interface, second amplifying circuit output interface, total pair control switch and the second amplifying circuit switch.Chip is provided with adaptive bias circuit and negative-feedback circuit.The utility model solves low, the inefficient problem of the single-chip integration radio-frequency power amplifier chip linearity, improves power output and the efficiency of chip simultaneously.
Description
Technical field
The utility model relates to technical field of electronic communication, is specifically related to a kind of wideband power amplifer chip for radar system and amplifier.
Background technology
In prior art, along with developing rapidly of modern communication technology, 3G becomes main flow, and 4G brings into use, and 5G is stepping up research and development.Radio frequency integrated power amplifier is the important component part realizing radio-frequency front-end.Instantly, telecom operators have employed different wireless communication systems, and the frequency that different wireless communication systems uses requires different with mode of operation.High power Band Monolithic Integrated integrated RF power amplifier chip arises at the historic moment.
Existing integrated RF power amplifier chip often adopts CMOS, SiGe BiCMOS, GaAs technique.CMOS technology cost is minimum, but is difficult to produce high efficiency and high-power integrated RF power amplifier because of its low puncture voltage and hot carrier's effect.GaAs processing performance is best, but manufacturing cost is expensive.SiGe BiCMOS technique and CMOS technology are completely compatible, and have high breakdown voltage and cut-off frequency and more and more come into one's own.Conventional linearization technique comprises predistortion, adaptive-biased etc.The features such as adaptive-biased technology is simple because of its structure, improves the linearity obvious, low in energy consumption are generally used.The am-pm modulation technique compensating radio-frequency power amplifier can improve the linearity of power amplifier further.
Existing integrated RF power amplifier chip operation, in AB class state, takes into account efficiency and the linearity.Single-chip integration radio-frequency power amplifier chip circuit structure has and adopts single stage circuit structure, and also have multi-level pmultistage circuit structure, two-stage circuit structure is the most common.The ubiquitous problem of single-chip integration radio-frequency power amplifier chip is that the linearity is not high enough and power consumption is larger.
Existing integrated RF power amplifier chip on bandwidth of operation, have arrowband, broadband, ultra broadband point.Along with the lifting of device performance, the frequency band of single-chip integration radio-frequency power amplifier work is more and more wider, power output and efficiency more and more higher.
Utility model content
In order to overcome defect of the prior art, the utility model provides a kind of fully integrated, high linearity, broadband, low cost, miniaturized radio-frequency power amplifier chip.Using the wide-band radio frequency power amplifier chip of SiGe BiCMOS technique design to solve ubiquitous problem is that the linearity is not high enough.Obtain high linearity and take into account the wireless communication frequency band of different telecom operators better.The wideband power amplifer that the utility model provides belongs to fully integrated monolithic chip, improves power output, can be widely used in the fields such as radar, communication, WLAN.
The utility model is achieved by the following technical solution: a kind of wideband power amplifer chip for radar system, described chip comprises chip substrate, described chip substrate is connected in series the first amplifying circuit and the second amplifying circuit, described chip substrate is provided with the first chip operating voltage interface arranged in order, fine motion radio-frequency (RF) switch, first secondary control interface, control signal input port, constant voltage interface, first amplifying circuit switch, second chip operating voltage interface, first amplifying circuit input interface, first amplifying circuit interface of the ground wire, first amplifying circuit output interface, second amplifying circuit interface of the ground wire, second amplifying circuit input interface, second secondary control interface, second amplifying circuit output interface, total pair control switch and the second amplifying circuit switch.
Further, described chip is provided with adaptive bias circuit and negative-feedback circuit.
Further, described adaptive bias circuit comprises the biasing resistor, the 6th triode, the 4th triode and the 5th triode that are connected in series in order, 4th resistance one end is connected with the second chip operating voltage interface, the other end of described 4th resistance is connected with partially installing capacitor, and the described 4th is connected with described 6th transistor base between resistance and partially installing capacitor.
Further, described negative-feedback circuit comprises the negative feedback resistor, negative feedback loop transistor and the capacitance that are connected in series, described capacitance is connected with the collector electrode of the second triode, the base stage of described negative feedback loop transistor is connected with the 5th resistance and single-wire-protocol interface tandem in order, and described negative feedback resistor is connected with power input ports.
Further, described first amplifying circuit input interface is connected with the first application circuit, described second amplifying circuit output interface is connected with the second application circuit, and described first amplifying circuit output interface and the second amplifying circuit input interface are connected input and the output of the 3rd application circuit respectively.
Further, described first application circuit comprises the first application circuit signal input port, the first oscillator coil of the first application circuit, the first electric capacity of the first application circuit, the second electric capacity of the first application circuit and the described first amplifying circuit input interface that sequential series connects, and connects the second oscillator coil of the first application circuit of ground connection between the first electric capacity of described first application circuit and the second electric capacity of the first application circuit.
Further, described second application circuit comprises the first electric capacity of the second application circuit be connected in series with described second amplifying circuit output interface, the second electric capacity of the second application circuit, the second oscillator coil of the second application circuit and the second application circuit signal output port; The oscillating circuit be made up of the 3rd electric capacity of the first oscillator coil of the second application circuit and the second application circuit is connected with between described second amplifying circuit output interface and the first electric capacity of the second application circuit; The 3rd oscillator coil of the second application circuit of ground connection is connected with between first electric capacity of described second application circuit and the second electric capacity of the second application circuit.
Further, described 3rd application circuit comprises the first electric capacity and the second amplifying circuit input interface connecting circuit of the 3rd application circuit be linked in sequence with the first amplifying circuit output interface, is connected with the first resistance of the first oscillator coil of the 3rd application circuit be connected in parallel, the second electric capacity of the 3rd application circuit and the 3rd application circuit between described first amplifying circuit output interface and the first condenser network of the 3rd application circuit.
Further, the utility model additionally provides a kind of for radar system wideband power amplifer, and the wideband power amplifer chip of described any one for radar system installed by described amplifier.
Compared with prior art, superior effect is: the utility model solves low, the inefficient problem of the single-chip integration radio-frequency power amplifier chip linearity, the am-pm modulator approach of a kind of adaptive-biased structure and compensation radio-frequency power amplifier is applied in the chip design of radar system wideband power amplifer, has improve power output and the efficiency of chip.
Accompanying drawing explanation
Fig. 1 is wideband power amplifer chip circuit rough schematic view described in the utility model;
Fig. 2 is wideband power amplifer chip circuit schematic diagram described in the utility model;
Fig. 3 is the pin figure of wideband power amplifer chip described in the utility model;
Fig. 4 is wideband power amplifer chip application circuit diagram described in the utility model.
Reference numeral is as follows:
1-signal input port, 2-first amplifying circuit, 3-second amplifying circuit, 4-signal output port, 5-adaptive bias circuit, 6-negative-feedback circuit, 7-first operating voltage interface, 8-mirror image circuit interface, 9-control signal input, 10-power input ports, 11-negative feedback enable switch, 12-power stage port, 13-second operating voltage interface, 14-chip substrate, 14-1-first chip operating voltage interface, 14-2-fine motion radio-frequency (RF) switch, the secondary control interface of 14-3-first, 14-4-control signal input port, 14-5-constant voltage interface, 14-6-first amplifying circuit switch, 14-7-second chip operating voltage interface, 14-8-first amplifying circuit input interface, 14-9-first amplifying circuit interface of the ground wire, 14-10-first amplifying circuit output interface, 14-11-second amplifying circuit interface of the ground wire, 14-12-second amplifying circuit input interface, 14-13-second pair control switch, 14-14-second amplifying circuit output interface, the total secondary control interface of 14-15-, 14-16-second amplifying circuit switch, 15-first application circuit, 15-1-first application circuit signal input port, the first oscillator coil of 15-L1-first application circuit, the second oscillator coil of 15-L2-first application circuit, first electric capacity of 15-C1-first application circuit, the second electric capacity of 15-C2-first application circuit, 16-second application circuit, 16-1 second application circuit signal output port, 16-2-second application circuit operating voltage port, first electric capacity of 16-C1-second application circuit, second electric capacity of 16-C2-second application circuit, the 3rd electric capacity of 16-C3-second application circuit, the first oscillator coil of 16-L1-second application circuit, second oscillator coil of 16-L2-second application circuit, the 3rd oscillator coil of 16-L3-second application circuit, 17-the 3rd application circuit, 17-1 the 3rd application circuit operating voltage port, the first electric capacity of 17-C1 the 3rd application circuit, the second electric capacity of 17-C2 the 3rd application circuit, first oscillator coil of 17-L1 the 3rd application circuit, the first resistance of 17-R1 the 3rd application circuit, Rb-biasing resistor, Rf-negative feedback resistor, R1-first resistance, R2-second resistance, R3-the 3rd resistance, R4-the 4th resistance, R5-the 5th resistance, Q1-first triode, Q2-second triode, Q3-the 3rd triode, Q4-the 4th triode, Q5-the 5th triode, Q6-the 6th triode, Cb-partially installing capacitor, Cf-capacitance, C1-first electric capacity, C2-second electric capacity, C3-the 3rd electric capacity, C4-the 4th electric capacity, L1-first oscillator coil, L2-second oscillator coil, L3-the 3rd oscillator coil, L4-the 4th oscillator coil, L5-the 5th oscillator coil, Mf-negative feedback loop transistor.
Embodiment
Below in conjunction with accompanying drawing, the utility model embodiment is described in further detail.
Shown in Figure of description 1-4, illustrate the utility model, the utility model provides a kind of wideband power amplifer chip for radar system, described chip comprises chip substrate 14, a kind of circuit structure adopting two-stage to amplify for radar system wideband power amplifer chip that the present embodiment provides.Two-stage circuit structure is the same, and just device parameters is different, and the emitter area of first order SiGe HBT power transistor is 230.4um
2(20 HBT unit, each HBT unit comprises 2 emitter junctions, the length of each emitter junction and be widely respectively 6.4um and 0.9um), the emitter area of second level SiGe HBT power transistor is 792.72um
2(30 HBT unit, each HBT unit comprises 4 emitter junctions, the length of each emitter junction and be widely respectively 7.34um and 0.9um).The chip exemplary voltages gain that the present embodiment provides is 14dB, Op1dB be 24dBm, PAE is 20%, noise factor 3.5dB, adopts 3.3V single power supply, consumes total current 100mA, chip area 0.84 × 0.73mm
2.The technical program reduces power consumption reaching under equal high linearity condition, and chip area is little simultaneously, and efficiency is higher, reduces cost, and practical bandwidth, field is wide.In order to solve the problems such as the single-chip integration radio-frequency power amplifier chip linearity is low, efficiency is poor, the am-pm modulator approach of a kind of adaptive-biased structure and compensation radio-frequency power amplifier is applied in the chip design of radar system wideband power amplifer, has improve power output and the efficiency of chip.As shown in Figure 1, this figure is omitted input, exports and the rough schematic view of interstage matched, comprises in described chip substrate 14 and is connected in series signal input port 1, first amplifying circuit 2, second amplifying circuit 3 and signal delivery port 4.As shown in Figure 3, described chip substrate 14 is provided with the first chip operating voltage interface 14-1 arranged in order, fine motion radio-frequency (RF) switch 14-2, first secondary control interface 14-3, control signal input port 14-4, constant voltage interface 14-5, first amplifying circuit switch 14-6, second chip operating voltage interface 14-7, first amplifying circuit input interface 14-8, first amplifying circuit interface of the ground wire 14-9, first amplifying circuit output interface 14-10, second amplifying circuit interface of the ground wire 14-11, second amplifying circuit input interface 14-12, second secondary control interface 14-13, second amplifying circuit output interface 14-14, total pair control switch 14-15 and the second amplifying circuit switch 14-16.Adaptive bias circuit 5 and negative-feedback circuit 6 is also provided with in chip described in the utility model.As shown in Figure 2, in figure, a structure of dotted line frame is adaptive bias circuit 5, and another is negative feedback structure 6, and adaptive bias circuit 5 is in order to increase the linearity of power amplifier.As shown in Figure 2, circuit of the present utility model comprises the first operating voltage interface 7, control signal input 9, power input ports 10, power stage port 12 and the second operating voltage interface 13 respectively, the present embodiment have employed two kinds of bias circuit constructions: mirror image circuit interface 8 (IREF) provides mirror image bias current by constant-voltage circuit (BandGap), for the base stage of the second triode Q2 provides bias voltage; As the adaptive bias circuit 5 in dotted line frame in Fig. 2, it sets the working direct current of the second triode Q2 together with mirror image biasing circuit.In mirror image biasing circuit, the effect of the first electric capacity C1 carries out filtering to bias current, to reduce the biased noise introduced, reduces the noise factor of power amplifier.When input signal increases, the base voltage of the 6th triode Q6 raises, and the emitter of the 6th triode Q6 is injected into the ER effect of the second triode Q2 base stage greatly, and therefore the dynamic duty electric current of the second triode Q2 can become large, and the linearity can improve.The linearity of adaptive bias circuit 5 pairs of power amplifiers improves obviously, and usually can improve 3-5dBm, and its static working current is less, the efficiency of PA can improve.The frequency band of this wideband power amplifer chip is 700M-2700M.With regard to product, NXP (grace intelligence Pu semiconductor) Products BGA7124 adopts single-stage silicon technology successfully to manufacture the broadband high linearity integrated power amplifier of 0.25W, and its static working current is more than 130mA; RFMD company adopts the broadband integrated power amplifier product SGA9089Z of SiGe HBT technique to export 1dB compression point representative value and reaches 23.7dBm, and its static working current has exceeded 200mA.Adaptive bias circuit 5 comprises the biasing resistor Rb, the 6th triode Q6, the 4th triode Q4 and the 5th triode Q5 that are connected in series in order, described 4th resistance R4 one end is connected with the second chip operating voltage interface 13, the other end of described 4th resistance R4 is connected with partially installing capacitor Cb, is connected between described 4th resistance R4 and described partially installing capacitor Cb with described 6th triode Q6 base stage.Described negative-feedback circuit 6 comprises the negative feedback resistor Rf, negative feedback loop transistor Mf and the capacitance Cf that are connected in series, described capacitance Cf is connected with the collector electrode of the second triode Q2, the base stage of described negative feedback loop transistor Mf is connected in series with the 5th resistance R5 and negative feedback enable switch 11 in order, described negative feedback resistor Rf is connected with power input ports 10 and improves power amplifier linearity, negative feedback loop transistor Mf can compensate the am-pm modulation of PA, improves the linearity of radio-frequency power amplifier.As shown in Figure 4, chip element numerical value is the component value being applied to the wireless radar system of S-band, can by changing sheet external component to meet the application requirement of different field and different frequency range.Described first amplifying circuit input interface 14-8 is connected with the first application circuit 15, described second amplifying circuit output interface 14-14 is connected with the second application circuit 16, and described first amplifying circuit output interface 14-10 and the second amplifying circuit input interface 14-12 are connected input and the output of the 3rd application circuit 17 respectively.Described first application circuit 15 comprises the first application circuit signal input port 15-1 of sequential series connection, the first oscillator coil 15-L1 value of the first application circuit is 2nH, the first electric capacity 15-C1 value of the first application circuit is 1.8pF, the second electric capacity 15-C2 value of the first application circuit signal is 1.8pF and described first amplifying circuit input interface 14-8, and the second oscillator coil 15-L2 value connecting the first application circuit of ground connection between the first electric capacity 15-C1 of described first application circuit and the second electric capacity 15-C2 of the first application circuit is 4.5nH.The first electric capacity 16-C1 value that described second application circuit 16 comprises the second application circuit be connected in series with described second amplifying circuit output interface 14-14 is 1.5pF, the second electric capacity 16-C2 value of the second application circuit is 1.5pF, the second oscillator coil 16-L2 value of the second application circuit is the signal output port 16-1 of 2.2nH and the second application circuit; The oscillating circuit that the 3rd electric capacity 16-C3 that to be connected with by the first oscillator coil 16-L1 value of the second application circuit between described second amplifying circuit output interface 14-14 and the first electric capacity 16-C1 of the second application circuit be 7nH and the second application circuit is formed, the first electric capacity 16-C1 value is 1.5pF; The 3rd oscillator coil 16-L3 value being connected with the second application circuit of ground connection between first electric capacity 16-C1 of described second application circuit and the second electric capacity 16-C2 of the second application circuit is 2.8nH, and the 3rd electric capacity 16-C3 value of the second application circuit is 1pF.Described 3rd application circuit 17 comprises the first electric capacity 17-C1 and the second amplifying circuit input interface 14-12 connecting circuit of the 3rd application circuit be linked in sequence with the first amplifying circuit output interface 14-10, first electric capacity 17-C1 value of the 3rd application circuit is 2Pf, the first oscillator coil 17-L1 of the 3rd application circuit be connected in parallel is connected with between described first amplifying circuit output interface 14-10 and the first electric capacity 17-C1 circuit of the 3rd application circuit, second electric capacity 17-C2 of the 3rd application circuit and the first resistance 17-R1 of the 3rd application circuit, second electric capacity 17-C2 value of the 3rd application circuit is 1Pf, the first resistance 17-R1 value 100 ohm of the 3rd application circuit, first oscillator coil 17-L1 value of the 3rd application circuit is 10nH.
As shown in Figure 2, second triode Q2 is the large scale amplifier transistor of power amplifier, capacitance Cf in negative-feedback circuit 6 in dotted line frame and transistor Rf forms resistive degeneration structure in parallel for improving the linearity of radio-frequency power amplifier, Cf is capacitance, the am-pm modulation of all right compensating power amplifier of dynamic parasitic capacitance when transistor Mf works, improves the linearity of radio-frequency power amplifier further.SWP is negative feedback enable switch.Power amplifier adopts open collector to export, and connects supply voltage by the load inductance outside chip, to make the second triode Q2 normally work, is completed the maximum power coupling of 50 ohm load impedance by the outer matching network of chip simultaneously.
The chip circuit provided in the utility model have employed two kinds of bias circuit constructions: mirror image circuit interface 8 (IREF) provides mirror image bias current by constant-voltage circuit (BandGap), for the base stage of the second triode Q2 provides bias voltage; As the adaptive bias circuit 5 in dotted line frame in Fig. 2, it sets the working direct current of the second triode Q2 together with mirror image biasing circuit.In mirror image biasing circuit, the effect of the first electric capacity C1 carries out filtering to bias current, to reduce the biased noise introduced, reduces the noise factor of power amplifier.When input signal increases, the base voltage of the 6th triode Q6 raises, and the emitter of the 6th triode Q6 is injected into the ER effect of the second triode Q2 base stage greatly, and therefore the dynamic duty electric current of the second triode Q2 can become large, and the linearity can improve.Adaptive bias circuit 5 can improve the linearity of power amplifier, usually can improve 3-5dBm, and reduces its static working current, and the efficiency of PA can improve.
The utility model additionally provides a kind of for radar system wideband power amplifer, and the above-mentioned wideband power amplifer chip for radar system installed by described amplifier.
The utility model is not limited to above-mentioned execution mode, and when not deviating from flesh and blood of the present utility model, any distortion that it may occur to persons skilled in the art that, improvement, replacement all fall into scope of the present utility model.
Claims (9)
1. the wideband power amplifer chip for radar system, it is characterized in that, described chip comprises chip substrate (14), described chip substrate (14) is connected in series the first amplifying circuit (2) and the second amplifying circuit (3), described chip substrate (14) is provided with the first chip operating voltage interface (14-1) arranged in order, fine motion radio-frequency (RF) switch (14-2), first secondary control interface (14-3), control signal input port (14-4), constant voltage interface (14-5), first amplifying circuit switch (14-6), second chip operating voltage interface (14-7), first amplifying circuit input interface (14-8), first amplifying circuit interface of the ground wire (14-9), first amplifying circuit output interface (14-10), second amplifying circuit interface of the ground wire (14-11), second amplifying circuit input interface (14-12), second secondary control interface (14-13), second amplifying circuit output interface (14-14), total pair control switch (14-15) and the second amplifying circuit switch (14-16).
2. according to claim 1 for the wideband power amplifer chip of radar system, it is characterized in that, described chip is provided with adaptive bias circuit (5) and negative-feedback circuit (6).
3. according to claim 2 for the wideband power amplifer chip of radar system, it is characterized in that, described adaptive bias circuit (5) comprises the biasing resistor (Rb) be connected in series in order, 6th triode (Q6), 4th triode (Q4) and the 5th triode (Q5), 4th resistance (R4) one end is connected with the second chip operating voltage interface (13), the other end of described 4th resistance (R4) is connected with partially installing capacitor (Cb), be connected with described 6th triode (Q6) base stage between described 4th resistance (R4) and partially installing capacitor (Cb).
4. according to claim 2 for the wideband power amplifer chip of radar system, it is characterized in that, described negative-feedback circuit (6) comprises the negative feedback resistor (Rf) be connected in series, negative feedback loop transistor (Mf) and capacitance (Cf), described capacitance (Cf) is connected with the collector electrode of the second triode (Q2), the base stage of described negative feedback loop transistor (Mf) is connected in series with the 5th resistance (R5) and single-wire-protocol interface (11) in order, described negative feedback resistor (Rf) is connected with power input ports (10).
5. according to claim 1 for the wideband power amplifer chip of radar system, it is characterized in that, described first amplifying circuit input interface (14-8) is connected with the first application circuit (15), described second amplifying circuit output interface (14-14) is connected with the second application circuit (16), and described first amplifying circuit output interface (14-10) and the second amplifying circuit input interface (14-12) are connected input and the output of the 3rd application circuit (17) respectively.
6. according to claim 5 for the wideband power amplifer chip of radar system, it is characterized in that, described first application circuit (15) comprises the first application circuit signal input port (15-1) that sequential series connects, first oscillator coil (15-L1) of the first application circuit, first electric capacity (15-C1) of the first application circuit, second electric capacity (15-C2) of the first application circuit and described first amplifying circuit input interface (14-8), second oscillator coil (15-L2) of the first application circuit of ground connection is connected between first electric capacity (15-C1) of described first application circuit and second electric capacity (15-C2) of the first application circuit.
7. according to claim 5 for the wideband power amplifer chip of radar system, it is characterized in that, described second application circuit (16) comprises first electric capacity (16-C1) of the second application circuit be connected in series with described second amplifying circuit output interface (14-14), second electric capacity (16-C2) of the second application circuit, second oscillator coil (16-L2) of the second application circuit and the second application circuit signal output port (16-1); The oscillating circuit be made up of the 3rd electric capacity (16-C3) of first oscillator coil (16-L1) of the second application circuit and the second application circuit is connected with between described second amplifying circuit output interface (14-14) and first electric capacity (16-C1) of the second application circuit; The 3rd oscillator coil (16-L3) of the second application circuit of ground connection is connected with between first electric capacity (16-C1) of described second application circuit and second electric capacity (16-C2) of the second application circuit.
8. according to claim 5 for the wideband power amplifer chip of radar system, it is characterized in that, described 3rd application circuit (17) comprises the first electric capacity (17-C1) and second amplifying circuit input interface (14-12) connecting circuit of the 3rd application circuit be linked in sequence with the first amplifying circuit output interface (14-10), first oscillator coil (17-L1) of the 3rd application circuit be connected in parallel is connected with between described first amplifying circuit output interface (14-10) and the first electric capacity (17-C1) circuit of the 3rd application circuit, second electric capacity (17-C2) of the 3rd application circuit and first resistance (17-R1) of the 3rd application circuit.
9. for a radar system wideband power amplifer, it is characterized in that, described amplifier has been installed according to the arbitrary described wideband power amplifer chip for radar system of claim 1-8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420679919.3U CN204156827U (en) | 2014-11-07 | 2014-11-07 | A kind of wideband power amplifer chip for radar system and amplifier |
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| CN201420679919.3U CN204156827U (en) | 2014-11-07 | 2014-11-07 | A kind of wideband power amplifer chip for radar system and amplifier |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378071A (en) * | 2014-11-07 | 2015-02-25 | 北京爱洁隆技术有限公司 | Wideband power amplifier chip for radar system and amplifier |
| US11431305B2 (en) | 2019-10-28 | 2022-08-30 | Murata Manufacturing Co., Ltd. | Power amplifier module and power amplification method |
-
2014
- 2014-11-07 CN CN201420679919.3U patent/CN204156827U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378071A (en) * | 2014-11-07 | 2015-02-25 | 北京爱洁隆技术有限公司 | Wideband power amplifier chip for radar system and amplifier |
| CN104378071B (en) * | 2014-11-07 | 2017-10-10 | 北京旋极星源技术有限公司 | A kind of wideband power amplifer chip and amplifier for radar system |
| US11431305B2 (en) | 2019-10-28 | 2022-08-30 | Murata Manufacturing Co., Ltd. | Power amplifier module and power amplification method |
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Address after: 100176, Beijing economic and Technological Development Zone, No. two, No. 29, Hai Lu, No. 8, building 3 Patentee after: Beijing Xingyuan Technology Co.,Ltd. spin pole Patentee after: Wan Jia Address before: 100176, Beijing Yizhuang Daxing District Economic Development Zone, No. two, No. 29, Hai Lu, No. 8, building 3 Patentee before: BEIJING AIJIELONG TECHNOLOGY Co.,Ltd. Patentee before: Wan Jia |
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Effective date of registration: 20230413 Address after: 2 / F, building 1, No.2, Keyuan south 2nd Road, high tech Zone, Chengdu, Sichuan 610000 Patentee after: CHENGDU WATERTEK STAR-SOURCE INFORMATION TECHNOLOGY CO.,LTD. Address before: 100176 3rd floor, building 8, yard 29, Jinghai 2nd Road, Beijing Economic and Technological Development Zone Patentee before: Beijing Xingyuan Technology Co.,Ltd. spin pole Patentee before: Wan Jia |