KR980006920A - The coefficient circuit of the semiconductor device - Google Patents

Abstract

The present invention relates to a coefficient circuit of a semiconductor device for increasing an initially input address signal to an interleaved mode and a linear mode, the method comprising: inputting the initial address signal and a mode selection signal to select one of the interleaved mode and the linear mode; A plurality of negative non-inverting means; A plurality of counting means for incrementing the initial address signal by taking an inverted signal of the output signal of the plurality of NAND devices as an input; A plurality of exclusive OR gates receiving the initial address signal and the plurality of counting means outputs; And a plurality of selection means for selectively outputting either one of the exclusive-OR means and the output of the count means in accordance with the mode selection signal, wherein the coefficient circuits in both modes are separately designed It is possible to select both modes through a mode selection signal in one counting circuit without needing to integrate them in a semiconductor device, thereby making it possible to improve the degree of integration of the semiconductor device and to eliminate the necessity of using an additional mask for metal wiring, It can be greatly reduced.

Description

The coefficient circuit of the semiconductor device

Since this is a trivial issue, I did not include the contents of the text.

FIG. 1 is a coefficient circuit diagram of a semiconductor device according to the present invention. FIG.

FIG. 5 is a signal waveform diagram of each part obtained by simulation of a linear coefficient mode of a coefficient circuit diagram according to the present invention. FIG.

Claims (6)

A coefficient circuit of a semiconductor device for increasing an initially input address signal to an interleaved mode and a linear mode, the coefficient circuit comprising: a plurality of input terminals for selecting either the interleaved mode or the linear mode; A negative logical product of; A plurality of counting means for incrementing the initial address signal by inputting the inverted signals of the plurality of NAND devices and an output signal; A plurality of exclusive OR gates receiving the initial address signal and the plurality of counting means outputs; And a plurality of selection means for selectively outputting either the exclusive OR means or the output of the count means in accordance with the mode selection signal. 2. The semiconductor device according to claim 1, wherein the selecting means comprises a plurality of transfer gates, 2. The semiconductor device according to claim 1, wherein the plurality of counting means is a 1-bit counting means for sequentially counting the input address signal by one bit, The counting circuit according to claim 3, characterized in that the counting means is applied with a load signal (LOAD) from the outside for blocking the counting means from the outside so that the initial address can be counted, The apparatus of claim 3, wherein the one counting means is applied with a clock signal (CLQB), which is an external synchronizing signal, at the clock terminal, and the one counting means output signal is applied to another counting means clock terminal Of the semiconductor device 3. The semiconductor device according to claim 2, wherein the transfer gate is controlled by a combination of the mode selection signal, the mode selection signal, and an inverted signal of the mode selection signal. ※ Note: It is disclosed by the contents of the first application.