JPS61224616A - Delay circuit - Google Patents

Abstract

PURPOSE:To improve the degree of freedom in the design of a semiconductor integrated logical circuit by constituting the titled circuit with a signal input terminal, a signal output terminal, a transfer gate comprising MOS transistors (TRs) connected in parallel between the signal input terminal and the signal output terminal, and a capacitor so as to control freely the signal transmission time. CONSTITUTION:Each one end of the transfer gate comprising MOS TRs 1, 2,-n connected in parallel with each other is connected to a logical circuit A, the other end is connected to a power supply Vcc via the capacitor C and also connected to a logical circuit B. Further, gate terminals 1g, 2g,-ng of the MOS TRs 1,2-n are connected directly to the external device to the semiconductor integrated logical circuit. When the ON-resistances of the transfer gates 1,2-,n are all, equal, the delay circuit having n-way of time constant is obtained according to the logical value of the signal fed to the gate terminals 1g,2g,-,n, and in selecting the ON-resistances of the transfer gates 1,2,-n differently, the delay circuit having n<2>-way of time constants is obtained depending on the n-way of logical values of the gate terminals 1g,2g,-ng.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a delay circuit.

[Conventional technology]

Conventionally, methods for controlling the transmission time of signals in a semiconductor integrated circuit include providing a plurality of delay circuits with different signal transmission times in the circuit, and selecting the transmission time of the target signal using a switching circuit. Alternatively, a method has been used in which another delay circuit is configured outside the circuit and controlled.

[Problem that the invention seeks to solve]

The former method has the disadvantage that a plurality of different delay circuits must be prepared, and the latter method has the disadvantage that these delay circuits must be prepared.

An object of the present invention is to provide a delay circuit that can freely control signal transmission time with a simple configuration.

[Means for solving problems]

The delay circuit of the present invention includes a signal input terminal, a signal output terminal, and a MOS transistor connected in parallel between the signal input terminal and the signal output terminal, and a signal for controlling the delay time is applied to the gate terminal. It consists of a plurality of transfer gates, one end of which is connected to a power supply, and the other end of which is commonly connected to the transfer gates.

Therefore, various delay times can be obtained depending on the on-resistance of each transfer gate and the logical value of the signal applied to the gate terminal of each transfer gate.

If the on-resistances of each transfer gate are all equal,
Depending on the logical value of the signal applied to the gate terminal, there are n ways (
If the on-resistance of each transfer gate is different, the delay circuit has n8 different time constants.

〔Example〕

The present invention will be described in detail with reference to the drawings.

FIG. 1 is an embodiment of the present invention, which is a circuit diagram of a semiconductor integrated logic circuit having a delay circuit. In this embodiment, one end of each gate of a transfer gate consisting of MOS transistors (1.2°..., n) connected in parallel is connected to a logic circuit A, and the other end is connected to a power supply VCC via a capacitor C.
and to logic circuit B. Also, each transfer game) 1, 2. . . , n gate terminals 1g, 8y, . . . , nJil are directly connected to the outside of the semiconductor integrated logic circuit.

Now, each transfer game) 1, 2. ..., the on-resistance of n is 10ne 20ne...t non,
If the capacitance of the capacitor fC is Ca, then the transfer game
) 1, 2. ..., n gate terminal 1g, 21°・
..., has a time constant of according to the logic value of the signal applied to ng.

And if the transfer game) 1, 2. ....

If the on-resistances 10ne 2 on,...o non of n are all equal, the gate terminals 19.2g,..., n
gK becomes a delay circuit with n different time constants according to the logical value of the applied signal, and also becomes a transfer gate) l
, 2. ..., if the on-resistances of n are all set to different values, the gate terminals 1g, zg, .

The n logical values of nl result in a delay circuit having - different time constants.

Strictly speaking, equation (1) shows that logic circuits A and B are ideal logic circuits, that is, the output impedance of the logic circuits is 0. This is true when the input impedance of logic circuit B is infinite and there is no influence from the capacitors included in logic circuits A and H, but even if logic circuits A and B are not ideal logic circuits, It goes without saying that the configuration of this embodiment provides a delay circuit having the same number of combinations of time constants as those described above.

Furthermore, by changing the number of transfer gates connected in parallel, it is possible to adjust the delay time even more finely.

FIG. 2 is a circuit diagram of another embodiment of the semiconductor integrated circuit of the present invention. In this embodiment, each transfer gate consisting of a MOS transistor shown in FIG.
The gate terminals 1g, 'ag, . . . , U are connected to respective outputs of the counter circuit, and the input e of the counter circuit is directly connected to the outside. In such a configuration, by inputting an appropriate number of pulse signals to the input e of the counter circuit, the transfer game (1),
2. . . , n and a capacitor C can form a delay circuit having a time constant, and by changing the number of pulse signals applied to the input e of the counter circuit, the transfer gate) 1, 2. . . , n change, resulting in delay circuits with various time constants.

Also, instead of the counter circuit, another logic circuit such as a decoder may be used, and furthermore, each transfer gate (1, 2) may be used once. ..., gate terminal 1g of n,
After changing the signals of 2fl,...ng and obtaining an appropriate delay time, the gate terminals 1 and 9 are connected using fuse elements, etc.
, 2p, ..., ng, if the signal values are fixed, then K
It goes without saying that it can be used as a delay circuit having a more desired delay time, that is, a constant delay time.

〔Effect of the invention〕

As explained above, the present invention is configured with a simple circuit consisting of a transfer gate made of a MOS transistor and a capacitor, so that the signal transmission time can be freely controlled, giving freedom in the design of semiconductor integrated logic circuits. It is extremely effective in improving the level of

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated logic circuit according to one embodiment of the present invention, and FIG. 2 is a schematic diagram of another embodiment of the present invention. 1, 2.・・・,n・・・・・・・・・・・・Transfer gate. C・・・・・・・・・・・・・・・・・・Capacitor. A, B・・・・・・・・・・・・・・・Logic circuit. K・・・・・・・・・・・・・・・・・・ Kakunta circuit. 1g, 2,9. ..., ng ......Gate terminal of each transfer gate 1゜2,・O・,n. Patent applicant: NEC Corporation Figure 2

Claims (1)

[Claims] a signal input terminal, a signal output terminal, a plurality of transfer gates each consisting of a MOS transistor connected in parallel between the signal input terminal and the signal output terminal, and to which a signal for controlling delay time is applied to the gate terminal; A delay circuit consisting of a capacitor whose other end is commonly connected to a power supply and the transfer gate.