JPS62145741A - Cmos gate array - Google Patents

Abstract

PURPOSE:To enable direct connection of the protective resistance or the parasitic capacity in an input/output buffer region from the internal region for forming a logic circuit by connecting each part used in the input/output buffer region independently to the terminal for connecting signals in a CMOS gate array. CONSTITUTION:Terminals 50-90 for connecting signals are drawn out to near a terminal 1 for connecting external signals and each terminal can arbitrarily be connected from outside. In these operations, the operation when the transistor or the inverter in an input/output buffer region is used for an output buffer or an input buffer is similar to the conventional one. Also, in a gate array, all the input/output buffer regions existing in a chip are rarely used and the unused input/output buffer regions often exist. In the example of connecting the resistance and the capacity in the unused input/output buffer region, an integrating circuit is formed by connecting a resistance 14 and a parasitic capacity 16 to the signal formed in an internal region 2. In this way, various circuits can be formed without adding a specific resistance or capacity.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to CMOS, which is one of semi-custom ICs.
This relates to gate arrays.

[Conventional technology]

Conventionally, there has been a CMOS gate array as shown in FIG. In the figure, 1 is a terminal for connecting an external signal, 2 is an internal area for forming a logic circuit, and 3 is a terminal for connecting an external signal 1
The input signal from the internal area 2 is transmitted to the internal area 2, or conversely, the output signal from the internal area 2 is transmitted to the external area.

This is a human output buffer area for transmitting signals to the signal connection terminal 1. Normally, the number of external signal connection terminals 1 and the number of output buffers in the human output buffer area 30 correspond one to one.

FIG. 4 shows an example of the input/output buffer circuit in the input/output buffer area 3. In the figure, 11 is a P-channel transistor for the output buffer, and 12 is an N-channel transistor for the output buffer. Their drains are connected to the external signal connection terminal 10, and the source potential of the transistor 11 is connected to one power supply ( VDD), and the source potential of the transistor 12 is connected to the other power supply (VDD).
) is connected to S. The signals connected to the gate potentials of transistors 11 and 12 differ depending on the purpose of the human output buffer circuit. Reference numeral 13 denotes an input inverter, the input of which is connected to the external signal connection terminal 10 via a resistor 14 for input protection. Only the signal connection terminals 20, 30, and 40 are used for connection to the internal region 2.

Next, the operation will be explained. When using the input/output buffer area 3 as an output buffer, the signal connection terminal 2
When operating by applying the necessary gate potential to 0.30 and using it as an input buffer, signal connection terminal 2 Q
'(r rHJ level, signal connection terminal krLl level, transistors 11 and 12 are turned off, and the signal of the external signal connection terminal 10 is transmitted to the internal area via the inverter 13. Internal area for forming a logic circuit The connection between 2 and the input/output buffer area 3 is the signal connection terminal 20°3.
This is done only with the 0.40 terminal, and connection with other signals within the output buffer area is not possible. Note that 15°16 is the parasitic capacitance associated with the transistors 11 and 12.

[Problem that the invention seeks to solve]

Conventional gate arrays are configured as described above, so even if you try to use the resistance in the input/output buffer area or the parasitic capacitance existing in the output buffer drain area as a circuit component, it is difficult to configure it in the internal area for forming the logic circuit. Since it cannot be directly connected to the logic circuit to be used, in such a case, there is a drawback that an external capacitor must be added.

This invention was made to solve the above-mentioned problems, and includes protection resistors in the input/output buffer area or 1.
The overall objective is to obtain a gate array in which the t' parasitic capacitance can be directly connected from the internal region for forming a logic circuit.

[Means for solving problems]

In the gate array according to the present invention, each component within the input/output buffer area is independently connected to a signal connection terminal.

[For production]

Direct connection between the signal connection terminal and the internal area for forming a logic circuit becomes possible.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.
The same symbols are used for parts that are the same as those in the figure.

50, 60, 70, 80, and 90 are signal connection terminals, which are drawn out to the vicinity of the external signal connection terminal 1, and the respective terminals can be arbitrarily connected from the outside.

Next, the operation will be explained. The operation of the transistors and inverters in the input/output buffer area when used as full output buffers or input buffers is the same as in the conventional example. In gate arrays, it is rare to use all the input/output buffer areas within the chip.
There are often unused overcrowded areas. FIG. 2 shows an example in which the resistors and capacitors in this unused output buffer area are connected. In the figure, a resistor 14 and a parasitic capacitor 16 are connected to a signal formed in the internal region 2 to form an integrating circuit.

In the above embodiment, a circuit using one type of resistor and parasitic capacitance is shown, but it is of course possible to connect a plurality of these, and various circuits can be constructed.

〔Effect of the invention〕

As described above, according to the present invention, the input protection resistor and the parasitic capacitance in the input/output buffer area can be connected to the internal area for forming the logic circuit, and the special resistance can be connected to the internal area for forming the logic circuit.

This has the effect that various circuits can be configured without adding capacitance.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an applied circuit, Fig. M3 is a configuration diagram of a CMOS gate array, and Fig. 4 is a circuit diagram showing an example of a conventional device. . 1.10...terminal for external signal connection, 2...internal area, 3...area for input/output buffer, 11.12...
...Transistor, 13...Inverter, 14.
... Resistance, Is, 16... Parasitic capacitance, 20,30
,40,50,60°70.80,90...Terminal for signal connection.

Claims (1)

[Claims] Used in the input/output buffer area in a CMOS gate array that has an external signal connection terminal, an internal area for forming a logic circuit, and an input/output buffer area that connects the external signal connection terminal and the internal area for forming the logic circuit. A CMO characterized by each component being independently connected to a signal connection terminal.
S gate array.