JPH0491517A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0491517A
JPH0491517A JP2208959A JP20895990A JPH0491517A JP H0491517 A JPH0491517 A JP H0491517A JP 2208959 A JP2208959 A JP 2208959A JP 20895990 A JP20895990 A JP 20895990A JP H0491517 A JPH0491517 A JP H0491517A
Authority
JP
Japan
Prior art keywords
output
pmos
nmos
terminal
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2208959A
Other languages
Japanese (ja)
Other versions
JP3089653B2 (en
Inventor
Takashi Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP02208959A priority Critical patent/JP3089653B2/en
Publication of JPH0491517A publication Critical patent/JPH0491517A/en
Application granted granted Critical
Publication of JP3089653B2 publication Critical patent/JP3089653B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To flexibly cope with numerous objects to be connected by using a single output device by providing a means which controls the characteristic of the output driver.
CONSTITUTION: When a low level is impressed upon a control terminal 103, the output signals 109 and 112 of an AND gate 105 and OR gate 108 are respectively fixed at a low and high levels and a PMOS 113 and NMOS 116 constituting an output driver are fixed to turned on states. Thus, the signal inputted to an input terminal 102 operates a CMOS inverter composed of a PMOS 114 and NMOS 115 and appears at an output terminal 117 as an inverted output. When a high level is impressed upon the input terminal 103, on the other hand, output signals 110 and 111 are respectively fixed at a low and high levels and the PMOS 114 and NMOS 115 are fixed to turned on states. Therefore, an input signal operates a CMOS inverter composed of the PMOS 113 and NMOS 116 and appears at the terminal 117 as an inverted output.
COPYRIGHT: (C)1992,JPO&Japio
JP02208959A 1990-08-07 1990-08-07 Semiconductor device Expired - Lifetime JP3089653B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02208959A JP3089653B2 (en) 1990-08-07 1990-08-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02208959A JP3089653B2 (en) 1990-08-07 1990-08-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0491517A true JPH0491517A (en) 1992-03-25
JP3089653B2 JP3089653B2 (en) 2000-09-18

Family

ID=16564986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02208959A Expired - Lifetime JP3089653B2 (en) 1990-08-07 1990-08-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3089653B2 (en)

Also Published As

Publication number Publication date
JP3089653B2 (en) 2000-09-18

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